25Q16BSIG

25Q16BSIG BEIJING | Alldatasheet

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◆ 16M-bit Serial Flash ◆ Program/Erase Speed -2048K-byte -Page Program time: 0.7ms typical -256 bytes per programmable page -Sector Erase time: 100ms typical -Block Erase time: 0.3/0.4/0.8s typical ◆ Standard, Dual, Quad SPI -Chip Erase time: 16s typical -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# -Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# ◆ Flexible Architecture -Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Sector of 4K-byte -Block of 32/64/128K-byte ◆ High Speed Clock Frequency -120MHz for fast read with 30PF load ◆ Low Power Consumption -Dual I/O Data transfer up to 180Mbits/s -20mA maximum active current -Quad I/O Data transfer up to 360Mbits/s -5uA maximum power down current ◆ Software/Hardware Write Protection ◆ Advanced security Features(1) -Write protect all/portion of memory via software -16-Bit Customer ID -Enable/Disable protection with WP# Pin -Security Architecture -Top or Bottom, Sector or Block selection ◆ Single Power Supply Voltage ◆ Minimum 100,000 Program/Erase Cycles -Full voltage range:2.7~3.6V Note: 1.Please contact Gigadevice for details. GENERAL DESCRIPTION The GD25Q16 (16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of 360Mbits/s. CONNECTION DIAGRAM CS# SO WP# VSS Top View VCC HOLD# SCLK SI 8–LEAD SOP/DIP 4 5

Dual and Quad Serial Flash GD25Q16 PIN DESCRIPTION Pin Name I/O Description CS# I Chip Select Input SO (IO1) I/O Data Output (Data Input Output 1) WP# (IO2) I/O Write Protect Input (Data Input Output 2) VSS Ground SI (IO0) I/O Data Input (Data Input Output 0) SCLK I Serial Clock Input HOLD# (IO3) I/O Hold Input (Data Input Output 3) VCC Power Supply BLOCK DIAGRAM SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Status Register Write Control Logic Byte Address Latch/Counter Column Decode And 256-Byte Page Buffer Write Protect Logic and Row Decode Flash Memory CS# SCLK SI(IO0) SO(IO1) HOLD#(IO3) WP#(IO2)

Dual and Quad Serial Flash GD25Q16 MEMORY ORGANIZATION Each device has Each block has Each sector has Each page has 2M 128/64/32K 4K 256 bytes 8K 512/256/128 16 - pages 512 32/16/8 - - sectors 16/32/64 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25Q16 64K Bytes Block Sector Architecture Block Sector Address range 511 1FF000H 1FFFFFH 496 1F0000H 1F0FFFH 495 1EF000H 1EFFFFH 480 1E0000H 1E0FFFH 47 02F000H 02FFFFH 32 020000H 020FFFH 31 01F000H 01FFFFH 16 010000H 010FFFH 15 00F000H 00FFFFH 0 000000H 000FFFH

Dual and Quad Serial Flash GD25Q16 DEVICE OPERATION SPI Mode Standard SPI The GD25Q16 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q16 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q16 supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non -volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure1. Hold Condition HOLD HOLD CS# SCLK HOLD#

Dual and Quad Serial Flash GD25Q16 Data Protection The GD25Q16 provide the following data protection methods: ◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) -Block Erase (BE) -Chip Erase (CE) ◆ Software Protection Mode: The Block Protect ( BP4, BP3, BP2, BP1, BP0) bits define the secti on of the memory array that can be read but not change. ◆ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. ◆ Deep Power-Down Mode: In Deep Power -Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Table1. GD25Q16 Protected area size Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 31 1F0000H-1FFFFFH 64KB Upper 1/32 0 0 0 1 0 30 to 31 1E0000H-1FFFFFH 128KB Upper 1/16 0 0 0 1 1 28 to 31 1C0000H-1FFFFFH 256KB Upper 1/8 0 0 1 0 0 24 to 31 180000H-1FFFFFH 512KB Upper 1/4 0 0 1 0 1 16 to 31 100000H-1FFFFFH 1M Upper 1/2 0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/32 0 1 0 1 0 0 to 1 000000H-01FFFFH 128KB Lower 1/16 0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/8 0 1 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/4 0 1 1 0 1 0 to 15 000000H-0FFFFFH 1M Lower 1/2 X X 1 1 X 0 to 31 000000H-1FFFFFH 2M ALL 1 0 0 0 1 31 1FF000H-1FFFFFH 4KB Top Block 1 0 0 1 0 31 1FE000H-1FFFFFH 8KB Top Block 1 0 0 1 1 31 1FC000H-1FFFFFH 16KB Top Block 1 0 1 0 X 31 1F8000H-1FFFFFH 32KB Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block 1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block 1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block

Dual and Quad Serial Flash GD25Q16 Status Register S15-S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Reserved QE SRP1 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress , when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Wri te Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect ( BP4, BP3, BP2, BP1, BP0) bits are non -volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect ( BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP) , Sector Erase (SE) and Block Era se (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non -volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock -down or one time programmable protection. SRP1 SRP0 #WP Status Register Description 0 0 X Software Protected The Status Register can be written to after a Write Enable command, WEL=1.(Default) 0 1 0 Hardware Protected WP#=0, the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. 1 0 X Power Supply Lock-Down(1) Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. 1 1 X One Time Program Status Register is permanently protected and can not be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. QE bit. The Quad Enable (QE) bit is a non -volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during stand ard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground)

Dual and Quad Serial Flash GD25Q16 COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one -byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Regist er or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data -out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power -Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes Write Enable 06H Write Disable 04H Read Status Register 05H (S7-S0) (continuous) Read Status Register-1 35H (S15-S8) (continuous) Write Status Register 01H (S7-S0) (S15-S8) Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous) Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous) Dual Output Fast Read 3BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(1) (continuous) Dual I/O Fast Read BBH A23-A8(2) A7-A0 M7-M0(2) (D7-D0)(1) (continuous) Quad Output Fast Read 6BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(3) (continuous) Quad I/O Fast Read EBH A23-A0 M7-M0(4) dummy(5) (D7-D0)(3) (continuous) Quad I/O Word Fast Read(7) E7H A23-A0 M7-M0(4) dummy(6) (D7-D0)(3) (continuous) Continuous Read Reset FFH Page Program 02 H A23-A16 A15-A8 A7-A0 D7-D0 Next byte Sector Erase 20H A23-A16 A15-A8 A7-A0 Block Erase(32K) 52H A23-A16 A15-A8 A7-A0 Block Erase(64K) D8H A23-A16 A15-A8 A7-A0 Block Erase(128K) D2H A23-A16 A15-A8 A7-A0 Chip Erase C7/60 H Program/Erase Suspend 75H Program/Erase Resume 7AH Deep Power-Down B9H Release From Deep Power-Down, And Read Device ID ABH dummy dummy dummy (ID7-ID0) (continuous) Release From Deep Power-Down ABH

Dual and Quad Serial Flash GD25Q16 Manufacturer/ Device ID 90H dummy dummy 00H (M7-M0) (ID7-ID0) (continuous) High Performance Mode A3H dummy dummy dummy Read Identification 9FH (M7-M0) (ID15-ID8) (ID7-ID0) (continuous) NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Fast Word Read Quad I/O Data: the lowest address bit must be 0. Table of ID Definitions: Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH C8 40 15 90H C8 14 ABH 14

Dual and Quad Serial Flash GD25Q16 Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes high. Figure2. Write Enable Sequence Diagram Command 0 1 2 3 4 5 6 7 06H CS# SCLK SI SO High-Z Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Figure3. Write Disable Sequence Diagram Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z Read Status Register (RDSR) (05H or 35H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read th e Status Register continuously . For command code “05H”, the SO will output Status Register bits S7~S0. he command code “35H”, the SO will output Status Register bits S15~S8. Figure4. Read Status Register Sequence Diagram Command 0 1 2 3 4 5 6 7 05H or 35H CS# SCLK SI SO High-Z 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB S7~S0 or S15~S8 out S7~S0 or S15~S8 out MSB

Dual and Quad Serial Flash GD25Q16 Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S15~S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Wri te Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Write Status Register cycle, and is 0 when i t is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect ( BP4, BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP 1 and SRP 0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect ( SRP1 and SRP 0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure5. Write Status Register Sequence Diagram Command 0 1 2 3 4 5 6 7 01H CS# SCLK SI SO High-Z 8 9 10 11 12 13 14 15 MSB 7 6 5 4 3 2 1 0 Status Register in 16 17 18 19 20 21 22 23 15 14 13 12 11 10 9 8 Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3 -byte address (A23-A0), each bit being latched -in during the rising edge of SCLK. Then the memory content, at that address, is shifted out o n SO, each bit being shifted out, at a Max frequency f R, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure6. Read Data Bytes Sequence Diagram Command 0 1 2 3 4 5 6 7 03H CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 32 MSB 3 2 1 0 34 35 36 3733 23 22 21 7 6 5 4 3 2 1 0 38 39 24-bit address MSB Data Out1 Data Out2

Dual and Quad Serial Flash GD25Q16 Read Data Bytes At Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure7. Read Data Bytes at Higher Speed Sequence Diagram Command 0 1 2 3 4 5 6 7 0BH CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 023 22 21 24-bit address MSB 34 35 36 3733 6 5 4 3 2 1 0 38 39 Data Out1 32 42 43 44 4541 46 4740 6 5 4 3 2 1 07 6 57 Data Out2 CS# SCLK SI SO MSB Dummy Byte Dual Output Fast Read (3BH) The Dual Output Fast Read co mmand is followed by 3 -byte address (A23 -A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure8. Dual Output Fast Read Sequence Diagram Command 0 1 2 3 4 5 6 7 3BH CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 023 22 21 24-bit address MSB 34 35 36 3733 5 3 1 7 5 3 1 38 39 Data Out1 32 42 43 44 4541 46 4740 Data Out2 CS# SCLK SI SO MSB Dummy Clocks 4 2 0 6 4 2 06 6

Dual and Quad Serial Flash GD25Q16 Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3 -byte address (A23 -A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure 9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure9. Quad Output Fast Read Sequence Diagram Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI(IO0) SO(IO1) High-Z 8 9 10 28 29 30 31 3 2 1 023 22 21 24-bit address 34 35 36 3733 1 5 1 5 1 5 1 38 39 Byte1 32 42 43 44 4541 46 4740 Dummy Clocks 0 4 0 4 0 4 04 4 WP#(IO2) High-Z HOLD#(IO3) High-Z CS# SCLK SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 2 6 2 6 2 6 26 6 3 7 3 7 3 7 37 7 Byte2 Byte3 Byte4 Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode ” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2 -bit per clock cycle from SI and SO. The command sequence is shown in followed Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read command. Dual I/O Fast Read With “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fa st Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure11. If the “Continuous Read Mode ” bits (M7-0) are any value other than AXH, the next command requires the first BB H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.

Dual and Quad Serial Flash GD25Q16 Figure10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) Command 0 1 2 3 4 5 6 7 BBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK Byte1 Byte2 Byte3 Byte4 Figure11. Dual I/O Fast Read Sequence Diagram (M7-0= AXH) 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS# 23 24 25 26 27 28 29 30 31 SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK Byte1 Byte2 Byte3 Byte4 15 16 17 18 19 20 21 22

Dual and Quad Serial Flash GD25Q16 Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Quad I/O Fast Read command. Quad I/O Fast Read With “Continuous Read Mode” The Quad I/O Fast Read comm and can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Read command (after CS# is raised and then l owered) does not require the EBH command code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode ” bits (M7-0) are any value other than AXH, the next command requires the first EBH command code, thus returning to normal operat ion. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure12. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) Dummy Byte1 Byte2 Figure13. Quad I/O Fast Read Sequence Diagram (M7-0= AXH) 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2

Dual and Quad Serial Flash GD25Q16 Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2 -dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for t he Quad I/O Word Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3h) must be executed once, prior to the Quad I/O Word Fast Read command. Quad I/O Word Fast Read With “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure15. If the “Continuous Read Mode ” bits (M7-0) are any value other than AXH, the next command requires the first E7H command code, thus returni ng to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH) Command 0 1 2 3 4 5 6 7 E7H CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) Dummy Byte1 Byte2 4 0 5 1 6 2 7 3 Byte3 Figure15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH) 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 4 0 5 1 6 2 7 3 Byte3

Dual and Quad Serial Flash GD25Q16 Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7 -A0) are not all zero, all tr ansmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7 -A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI  at least 1 byte data on SI  CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other byte s of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is not executed. Figure16. Page Program Sequence Diagram Command 0 1 2 3 4 5 6 7 02H CS# SCLK SI 8 9 10 28 29 30 31 3 2 1 023 22 21 24-bit address 42 43 44 4541 46 4740 50 51 52 5349 54 5548 6 5 4 3 2 1 07 CS# SCLK SI MSB Data Byte 2 32 33 34 35 7 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 07 6 5 4 3 2 1 07 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB MSB 36 37 38 39 2072 2073 2074 2075 2076 2077 2078 2079

Dual and Quad Serial Flash GD25Q16 Sector Erase (SE) (20H) The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure 17. CS# must be driven high after the eighth bit of the last address byte has been l atched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is t SE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table1) is not executed. Figure17. Sector Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 20H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0

24 Bits Address

32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on S I. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in ; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1) is not executed. Figure18. 32KB Block Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 52H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0

Dual and Quad Serial Flash GD25Q16 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on S I. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in ; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1) is not executed. Figure19. 64KB Block Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 D8H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 128KB Block Erase (BE) (D2H) The 128KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 128KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on S I. Any address inside the block is a valid address for t he 128KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 128KB Block Erase command sequence: CS# goes low  sending 128KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 128KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 128KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1) is not executed.

Dual and Quad Serial Flash GD25Q16 Figure20. 128KB Block Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 D2H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The command sequence is shown in Figure 21. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is t CE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self -timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure21. Chip Erase Sequence Diagram Command 0 1 2 3 4 5 6 7 60H or C7H CS# SCLK SI Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power -Down Mode can only be entered by executing the Deep Power -Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power -Down, and the device always Power -Up in the Standby Mode. The Deep Power -Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has

Dual and Quad Serial Flash GD25Q16 been latched in ; otherwise the Deep Power -Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to I CC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure22. Deep Power-Down Sequence Diagram Command 0 1 2 3 4 5 6 7 B9H CS# SCLK SI tDP Stand-by mode Deep Power-down mode Release From Deep Power-Down Or High Performance Mode And Read Device ID (RDI) (ABH) The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices ele ctronic identification (ID) number. To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the GD25Q16 is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure23. Release Power-Down Or High Performance Mode Sequence Diagram Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI RES1 Stand-by modeDeep Power-down mode t

Dual and Quad Serial Flash GD25Q16 Figure24. Release Power-Down/Read Device ID Sequence Diagram Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI 8 9 29 30 31 MSB 2 1 0

3 Dummy Bytes

Stand-by ModeDeep Power-down Mode High-Z Device ID Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power -Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90 H” followed by a 24 -bit address (A23-A0) of 000000 H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure25. Read Manufacture ID/ Device ID Sequence Diagram Command 0 1 2 3 4 5 6 7 90H CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 023 22 21 24-bit address MSB 34 35 36 3733 6 5 4 3 2 1 0 38 3932 42 43 44 4541 46 4740 Device ID CS# SCLK SI SO MSB Manufacturer ID 6 5 4 3 2 1 07

Dual and Quad Serial Flash GD25Q16 Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8 -bit manufacturer identific ation to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24 -bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure 26. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure26. Read Identification ID Sequence Diagram 0 1 2 3 4 5 6 7 CS# SCLK SI SO 8 9 10 MSB 18 19 20 2117 6 5 4 3 2 1 0 22 2316 26 27 28 2925 30 3124 Capacity ID7-ID0 CS# SCLK SI SO MSB Memory Type ID15-ID8 6 5 4 3 2 1 07 11 12 13 14 15 9FH 6 5 4 3 2 1 07 Manufacturer ID MSB High Performance Mode (HPM) (A3H) The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of internal charge pumps so the voltages required for accessing the flash memory array are readily available. The command sequence: CS# goes low Sending A3H command Sending 3-dummy byteCS# goes high. See Figure27. After the HPM command is executed, the device will maintain a slightly higher standby current ( Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby current (Icc1). In addition, Write Enable command (06H) and Power-Down command (B9H) will also release the device from HPM mode back to standard SPI standby state.

Dual and Quad Serial Flash GD25Q16 Figure27. High Performance Mode Sequence Diagram Command 0 1 2 3 4 5 6 7 A3H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 Continuous Read Mode Reset (CRMR) (FFH) The Dual/Quad I/O Fast Read operations , “Continuous Read Mode ” bits (M7-0) are implemented to further reduce command overhead. By setting the (M7 -0) to AXH, the nex t Dual/Quad I/O Fast Read operations do not require the BBH/EBH/E7H command code. Because the GD25Q16 has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q16 will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in Figure28. Figure28. Continuous Read Mode Reset Sequence Diagram 0 1 2 3 4 5 6 7 CS# SCLK SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) FFH Mode Bit Reset for Quad/Dual I/O Don\t Care Don\t Care Don\`t Care

Dual and Quad Serial Flash GD25Q16 Program/Erase Suspend (PES) (75H) The Erase/Program Suspend command “75H”, allows the system to interrupt a sector/block erase or page program operation and then read data from any other sector or block. The Write Status Register command (01H), Page Program (02H) and Erase commands (20H, 52H, D8H, D2H, C7H, 60H ) are not allowed during suspend. Erase/Program Suspend is valid only during the sector /block erase or page program operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. While the Erase/Program suspend cycle is in progress, the Read Status Register command may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Erase/Program suspend cycle and becomes a 0 when the cycle is finished and the device is ready to accept read command. A power -off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure29. Figure29. Program/Erase Suspend Sequence Diagram Command 0 1 2 3 4 5 6 7 75H CS# SCLK SI SO High-Z tSUS Accept read command Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the sector/block erase or program operation after a Program/Erase Suspend command. After issued the WIP bit in the status register will be set to 1 and the sector/block erase or program operation will completed. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure30. Figure30. Program/Erase Resume Sequence Diagram Command 0 1 2 3 4 5 6 7 7AH CS# SCLK SI SO Resume Erase/Program

Dual and Quad Serial Flash GD25Q16 POWER-ON TIMING Vcc(max) Vcc(min) VWI Reset State tPUW tVSL Chip Selection is not allowed Program, Erase and Write command are ignored Read command is allowed Device is fully accessible Time Table3. Power-Up Timing And Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC(min) To CS# Low 10 us tPUW Time Delay From VCC(min) To Write Instruction 1 10 ms VWI Write Inhibit Voltage VCC(min) 1 2.5 V INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). DATA RETENTION AND ENDURANCE Parameter Test Condition Min Units Minimum Pattern Data Retention Time 150℃ 10 Years 125℃ 20 Years Erase/Program Endurance -40 to 85℃ 100K Cycles LATCH UP CHARACTERISTICS Parameter Min Max Input Voltage Respect To VSS On I/O Pins -1.0V VCC+1.0V VCC Current -100mA 100mA

Dual and Quad Serial Flash GD25Q16 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 ℃ Storage Temperature -55 to 125 ℃ Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V VCC -0.5 to 4.0 V 0.8VCC 0.2VCC 0.7VCC 0.3VCC 0.5VCCAC Measurement Level Input timing reference level Output timing reference level Note: Input pulse rise and fall time ara<5ns CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 pF Input Rise And Fall time 5 ns Input Pause Voltage 0.2VCC to 0.8VCC V Input Timing Reference Voltage 0.3VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure31. Input Test Waveform And Measurement Level -0.5V 20ns 20ns 4.0V 3.6V Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform

Dual and Quad Serial Flash GD25Q16 DC CHARACTERISTIC Symbol Parameter Test Condition Min. Typ Max. Unit. ILI Input Leakage Current ±2 μA ILO Output Leakage Current ±2 μA ICC1 Standby Current CS#=VCC, VIN=VCC or VSS 1 5 μA ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS 1 5 μA ICC3 Operating Current (Read) CLK=0.1VCC / 0.9VCC at 90MHz, Q=Open(*1,*2,*4 I/O) 15 20 mA CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) 13 18 mA ICC4 Operating Current (PP) CS#=VCC 10 mA ICC5 Operating Current(WRSR) CS#=VCC 10 mA ICC6 Operating Current (SE) CS#=VCC 10 mA ICC7 Operating Current (BE) CS#=VCC 10 mA I CC8 High Performance Current 600 800 uA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL =1.6mA 0.4 V VOH Output High Voltage IOH =-100μA VCC-0.2 V

Dual and Quad Serial Flash GD25Q16 AC CHARACTERISTICS (T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf) Symbol Parameter Min. Typ. Max. Unit. fC Serial Clock Frequency For: FAST_READ(0BH), Dual Output(3BH) DC. 120 MHz fC1 Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High Performance Mode) DC. 90 MHz fC2 Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH) (Dual I/O & Quad I/O Without High Performance Mode) DC. 50 MHz fR Serial Clock Frequency For: Read(03H) DC. 90 MHz tCLH Serial Clock High Time 3.5 ns tCLL Serial Clock Low Time 3.5 ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time（read/write） 20 ns tSHQZ Output Disable Time 16 ns tCLQX Output Hold Time 0 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 2 ns tHLCH Hold# Low Setup Time (relative to Clock) 5 ns tHHCH Hold# High Setup Time (relative to Clock) 5 ns tCHHL Hold# High Hold Time (relative to Clock) 5 ns tCHHH Hold# Low Hold Time (relative to Clock) 5 ns tHLQZ Hold# Low To High-Z Output 6 ns tHHQX Hold# Low To Low-Z Output 6 ns tCLQV Clock Low To Output Valid 6 ns tWHSL Write Protect Setup Time Before CS# Low 20 ns tSHWL Write Protect Hold Time After CS# High 100 ns tDP CS# High To Deep Power-Down Mode 0.1 μs tRES1 CS# High To Standby Mode Without Electronic Signature Read 0.1 μs tRES2 CS# High To Standby Mode With Electronic Signature Read 0.1 μs tHPM CS# High To High Performance mode 0.2 us

Dual and Quad Serial Flash GD25Q16 tSUS CS# High To Next Command After Suspend 2 us tW Write Status Register Cycle Time 2 15 ms tPP Page Programming Time 0.7 2.4 ms tSE Sector Erase Time 100 300 ms tCE Chip Erase Time(GD25Q16) 16 32 s Figure32. Serial Input Timing SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCHtCHSH tCHCLtCLCH tSHSL Figure33. Output Timing CS# SCLK SO SI Least significant address bit (LIB) in tCLQV tCLQX tCLQX tCLQV tCH tCL tSHQZ LSB tQHQL tQLQH Figure34. Hold Timing CS# SCLK SO HOLD# tCHHL tHLQZ tHLCH tCHHH tHHCH tHHQX SI do not care during HOLD operation.

Dual and Quad Serial Flash GD25Q16

ORDERING INFORMATION

NOTE: 1. Standard bulk shipment is in Tube. Any altern ation of packing method (for Tape, R eel and Tray etc.), please advise in advance. GD XX X XX X X X X Green Code P:Pb Free Only Green Package Temperature Range C:Commercial(0℃ to +70℃) I:Industrial(-40℃ to +85℃) Package Type S:SOP8 208mil P:DIP8 Density 80:8Mb 16:16Mb Series Q:3V, 4KB Uniform Sector, Quad I/O Product Family 25:Serial Flash 32:32Mb T:SOP8 150mil 64:64Mb Packing Type T:Tube Y:Tray R:Tape & Reel W: WSON (6*5mm) LQ:1.8V,4KB Uniform Sector G:Pb Free & Halogen Free Green Package

Dual and Quad Serial Flash GD25Q16

PACKAGE INFORMATION

D AA2 S e b L C θ Dimensions Symbol A A1 A2 b C D E E1 e L L1 S θ Unit mm Inch

Dual and Quad Serial Flash GD25Q16 1 4 E1 E D AA2 S e b L C θ Dimensions Symbol A A1 A2 b C D E E1 e L L1 S θ Unit mm Inch

Dual and Quad Serial Flash GD25Q16 1 4 D L S b e AA2 C eB E Dimensions Symbol A A1 A2 b b1 C D E E1 e eB SL S Unit mm Inch

Dual and Quad Serial Flash GD25Q16

REVISION HISTORY

Version No Description Date 1.0 Initial Release Sep.10,2009 1.1 Add Packing Type(Tray, Reel & Tape), Add 150Mil Package Feb.04,2010 1.2 Add tHPM Parameter May.14,2010 1.3 Update Datasheet Aug.04,2010