25PE20VP

M25PE20_07 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Data Output (Q)
• 2.2 Serial Data Input (D)
• 2.3 Serial Clock (C)
• 2.4 Chip Select (S)
• 2.5 Reset (Reset )
• 2.6 Top Sector Lock (TSL)
• 2.7 Write Protect (W) or Top Sector Lock (TSL)
• 2.8 V CC supply voltage
• 2.9 V SS ground
• 3 SPI modes
• 4 Operating features
• 4.1 Sharing the overhead of modifying data
• 4.2 An easy way to modify data
• 4.3 A fast way to modify data
• 4.4 Polling during a Write, Program or Erase cycle
• 4.5 Reset
• 4.6 Active Power, Standby Power and Deep Power-Down modes
• 4.7 Status Register
• 4.8 Protection modes
• 4.8.1 Protocol-related protections
• 4.8.2 Specific Hardware and Software protections
• 5 Memory organization
• 6 Instructions
• 6.1 Write Enable (WREN)
• 6.2 Write Disable (WRDI)

Features

■ 1 or 2 Mbit of Page-Erasable Flash memory ■ 2.7 V to 3.6 V single supply voltage ■ SPI bus compatible serial interface ■ 50 MHz clock rate (maximum) ■ Page size: 256 bytes – Page Write in 11 ms (typical) – Page Program in 0.8 ms (typical) – Page Erase in 10 ms (typical) ■ SubSector Erase (32 Kbits) ■ Sector Erase (512 Kbits) ■ Bulk Erase (1 Mbit for the M25PE10, 2 Mbits for the M25PE20) ■ Deep Power-down mode 1µA (typical) ■ Electronic Signature – JEDEC Standard Two-Byte Signature (8012h for M25PE20 8011h for M25PE10) ■ Software Write Protection on a 64 Kbyte sector basis ■ More than 100 000 Write cycles ■ More than 20 year data retention ■ Hardware Write Protection of the memory area selected using the BP0 and BP1 bits ■ Package – ECOPACK® (RoHS compliant) SO8N (MN) 150 mil width VFQFPN8 (MP) 6 × 5 mm

M25PE20, M25PE10 Contents

Table 2. Software protection truth table (Sectors 0 to 3 for M25PE20 or sectors 0 Table 25. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package Table 26. VFQFPN8 (MLP8), 8-lead Very thin Fine Pitch Quad Flat Package No lead,

Description M25PE20, M25PE10

1 Description

The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) Serial Paged Flash memories, respectively. They are accessed by a high speed SPI-compatible bus. The memories can be written or programmed 1 to 256 Bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle. The M25PE20 memory is organized as 4 sectors, each containing 256 pages. Each page is 256 Bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 Bytes. The M25PE10 memory is organized as 2 sectors, each containing 256 pages. Each page is 256 Bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131, 072 Bytes. The memories can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase instruction. The memory can be Write Protected by either Hardware or Software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64 Kbytes (sector granularity). In order to meet environmental requirements, ST offers the M25PE20 and M25PE10 in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Important note This datasheet details the functionality of the M25PE20 and M25PE10 devices, based on the previous T7X process or based on the current T9HX process. Delivery of parts in T9HX process starts from August 2007. What are the changes? The M25PE10/M25PE20 in T9HX process offers the following additional features:

• the whole memory array is partitioned into 4-Kbyte subsectors
• five new instructions: Write Status Register (WRSR), Write to Lock Register (WRLR), Read Lock Register (RDLR), 4-Kbyte SubSector Erase (SSE) and Bulk Erase (BE)
• Status Register: 3 bits can be written (BP0, BP1, SRWD)
• WP input (pin 3): Write protection limits are extended, depending on the value of the BP0, BP1, SRWD bits. The WP Write protection remains the same if bits (BP1, BP0) are set to (0, 1) or (1, 0)
• VFQFPN8 6 × 5 mm package added

Signal description M2 5PE20, M25PE10

2 Signal description

2.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

2.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S )

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

2.5 Reset (Reset )

The Reset (Reset) input provides a hardware reset for the memory. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost.

2.6 Top Sector Lock (TSL )

This input signal puts the device in the Hardware Protected mode, when Top Sector Lock (TSL ) is connected to VSS , causing the top 256 pages (upper addresses) of the memory to become read-only (protected from write, program and erase operations). When Top Sector Lock (TSL) is connected to VCC , the top 256 pages of memory behave like the other pages of memory.

M25PE20, M25PE10 Signal description

2.7 Write Protect (W ) or Top Sector Lock (TSL)

• The Write Protect function is available in the T9HX process only (see Important note on page 6). The Write Protect (W) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in theBP1 and BP0 bits of the Status Register. See Section 6.4: Read Status Register (RDSR) for a description of these bits).
• The Top Sector Lock function is available in the T7X process only (see Important note on page 6). The input signal sets the device in the Hardware Protected mode, when Top Sector Lock (TSL) is connected to VSS , causing the top 256 pages (upper addresses) of the memory to become read-only (protected from write, program and erase operations). When Top Sector Lock (TSL) is connected to VCC , the top 256 pages of memory behave like the other pages of memory.

2.8 V CC supply voltage

VCC is the supply voltage.

2.9 V SS ground

VSS is the reference for the VCC supply voltage.

3 SPI modes

• CPOL=0, CPHA=0
• CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Standby mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus master and memory devices on the SPI bus

1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.

and C do not become High at the same time, and so, that the tSHCH requirement is met).

Figure 5. SPI modes supported

Operating features M25PE20, M25PE10

4 Operating features

4.1 Sharing the overhead of modifying data

To write or program one (or more) data Bytes, two instructions are required: Write Enable (WREN), which is one Byte, and a Page Write (PW) or Page Program (PP) sequence, which consists of four Bytes plus data. This is followed by the internal cycle (of duration t PW or tPP ). To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to

256 Bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1)

at a time, provided that they lie in consecutive addresses on the same page of memory.

4.2 An easy way to modify data

The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous Bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The Page Write (PW) instruction is entered by driving Chip Select (S ) Low, and then transmitting the instruction Byte, three address Bytes (A23-A0) and at least one data Byte, and then driving Chip Select (S ) High. While Chip Select (S) is being held Low, the data Bytes are written to the data buffer, starting at the address given in the third address Byte (A7-A0). When Chip Select (S ) is driven High, the Write cycle starts. The remaining, unchanged, Bytes of the data buffer are automatically loaded with the values of the corresponding Bytes of the addressed memory page. The addressed memory page then automatically put into an Erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a Byte-by-Byte basis. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see Page Write (PW) and Table 22: AC characteristics (50 MHz operation, T9HX (0.11µm) process)).

M25PE20, M25PE10 Operating features

4.3 A fast way to modify data

The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous Bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be:

• when the designer is programming the device for the first time
• when the designer knows that the page has already been erased by an earlier Page Erase (PE), SubSector Erase (SSE), Sector Erase (SE) or Bulk Erase (BE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available
• when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Page Program (PP) and Table 22: AC characteristics (50 MHz operation, T9HX (0.11µm) process)).

4.4 Polling during a Write, Program or Erase cycle

A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW , tPP, tPE , tBE , tW or tSE ). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.

4.5 Reset

An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition protection is provided by driving Reset (Reset) Low during the Power-on process, and only driving it High when VCC has reached the correct voltage level, VCC (min).

4.6 Active Power, Standby Powe r and Deep Power-Down modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write). The device then goes in to the Standby Power mode. The device consumption drops to I CC1 . The Deep Power-down mode is entered when the specific instruction (the Deep Power- down (DP) instruction) is executed. The device consumption drops further to ICC2 . The device remains in this mode until the Release from Deep Power-down instruction is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.

Operating features M25PE20, M25PE10

4.7 Status Register

The Status Register contains two status bits that can be read by the Read Status Register (RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.

4.8 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PE10 and M25PE20 feature the following data protection mechanisms:

4.8.1 Protocol-rel ated protections

• Power On Reset and an internal timer (tPUW ) can provide protection against inadvertent changes while the power supply is outside the operating specification.
• Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
• All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Reset (RESET ) driven Low – Write Disable (WRDI) instruction completion – Page Write (PW) instruction completion – Page Program (PP) instruction completion – Write to Lock Register (WRLR) instruction completion – Page Erase (PE) instruction completion – SubSector Erase (SSE) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion
• The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For the specific cases of Program and Write cycles, the designer should refer to Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW), Section 6.10: Page Program (PP), Section 6.12: Page Erase (PE), Section 6.14: Sector Erase (SE), and Section 6.13: SubSector Erase (SSE), and to Table 14: Device status after a Reset Low pulse.
• In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions while the device is not in active use.

M25PE20, M25PE10 Operating features

4.8.2 Specific Hardware and Software protections

The M25PE20/M25PE20 features a Hardware Protected mode, HPM, and two Software Protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. They are described below: HPM

• HPM in T7X process (see Important note on page 6): The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven Low, causing the top 256 pages of memory to become read-only. When Top Sector Lock (TSL ) is driven High, the top 256 pages of memory behave like the other pages of memory and the protection depends on the Block Protect bits (see SPM2 below).
• HPM in T9HX process (see Important note on page 6): The Hardware Protected mode (HPM) is used to write-protect the non-volatile bits of the Status Register (that is, the Block Protect bits, BP1 and BP0, and the Status Register Write Disable bit, SRWD). HPM is entered by driving the Write Protect (W ) signal Low with the SRWD bit set to High. This additional protection allows the Status Register to be hardware-protected. (see also Section 6.4.4: SRWD bit) SPM1 and SPM2
• The first Software Protected mode (SPM1) is managed by specific Lock Registers assigned to each 64-Kbyte sector. The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock Bit and the Lock Down Bit. – Write Lock Bit: The Write Lock Bit determines whether the contents of the sector can be modified (using the Write, Program or Erase instructions). When the Write Lock Bit is set, ‘1’, the sector is write protected – any operations that attempt to change the data in the sector will fail. When the Write Lock Bit is reset to ‘0’, the sector is not write protected by the Lock Register, and may be modified. – Lock Down Bit: The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write Lock and Lock Down Bits cannot be performed. A reset, or power-up, is required before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write Lock and Lock Down Bits can be changed. The Write Lock Bit and the Lock Down Bit are volatile and their value is reset to ‘0’ after a Power-Down or a Reset.

• The second Software Protected mode (SPM2) uses the Block Protect (BP1, BP0, see Section 6.4.3)) bits to allow part of the memory to be configured as read-only.

00 Sector unprotected from Program/Erase/Write operations, Protection status

01 Sector protected from Program/Erase/Write operations, Protection status

10 Sector Unprotected from Program/Erase/Write operations,

Sector Protection Status cannot be changed except by a Reset or Power-up.

11 Sector Protected from Program/Erase/Write operations,

Sector Protection Status cannot be changed except by a Reset or Power-up. Table 3. Protected area sizes for M25PE20

1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect bits (BP1, BP0) are 0.

Table 4. Protected area sizes for M25PE10

1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect bits (BP1, BP0) are 0.

5 Memory organization

• 1024 pages (256 Bytes each).
• 262,144 Bytes (8 bits each)
• 64 subsectors (32 Kbits, 4096 bytes each)
• 4 sectors (512 Kbits, 65536 Bytes each) The M25PE10 memory is organized as:
• 512 pages (256 Bytes each).
• 131,074 Bytes (8 bits each)
• 32 subsectors (32 Kbits, 4096 bytes each)
• 2 sectors (512 Kbits, 65536 Bytes each) In the M25PE20 and M25PE10, each page can be individually:
• programmed (bits are programmed from 1 to 0)
• erased (bits are erased from 0 to 1)
• written (bits are changed to either 0 or 1) The device is Page or Sector Erasable (bits are erased from 0 to 1).

Table 5. M25PE20 memory organization

Table 6. M25PE10 memory organization

Figure 6. M25PE20 block diagram

1. These features (in gray) are only available in the T7X process.

256 Byte

256 Bytes (Page Size)

Figure 7. M25PE10 block diagram

1. These features (in gray) are only available in the T7X process.

M25PE20, M25PE10 Instructions

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-Byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 7. Every instruction sequence starts with a one-Byte instruction code. Depending on the instruction, this might be followed by address Bytes, or by data Bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Read to Lock Register (RDLR) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S ) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), SubSector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI), Write Status Register (WRSR), Write to Lock Register (WRLR), Deep Power-down (DP) or Release from Deep Power-down (RDP) instruction, Chip Select (S ) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S ) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle or Erase cycle continues unaffected.

Table 7. Instruction set

1. Instruction available only in the T9HX process (see Important note on page 6).

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. instruction code, and then driving Chip Select (S) High. Figure 8. Write Enable (WREN) instruction sequence

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. instruction code, and then driving Chip Select (S) High.

• Power-up
• Write Disable (WRDI) instruction completion
• Page Write (PW) instruction completion
• Page Program (PP) instruction completion
• Write Status Register (WRSR) instruction completion
• Write to Lock Register (WRLR) instruction completion
• Page Erase (PE) instruction completion
• SubSector Erase (SSE) instruction completion
• Sector Erase (SE) instruction completion
• Bulk Erase (BE) instruction completion

Figure 9. Write Disable (WRDI) instruction sequence

6.3 Read Identification (RDID)

not decoded, and has no effect on the cycle that is in progress. the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. any time during data output. Figure 10. Read Identification (RDID) instruction sequence and data-out sequence Table 8. Read Identification (RDID) data-out sequence

6.4 Read Status Register (RDSR)

the Status Register continuously, as shown in Figure 11.

6.4.1 WIP bit

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write, Program or Erase instruction is accepted.

6.4.3 BP1, BP0 bits

• all Block Protect (BP1, BP0) bits are 0
• the Lock Register protection bits are not all set (‘1’)

6.4.4 SRWD bit

Table 9. Status Register format(1) (2)

1. SRWD = Status Register Write Protect bit; BP0, BP1 = Block Protect Bits (only available with T9HX).
2. The BP bits and the SRWD bit exist only in the T9HX process.
3. WEL (Write Enable Latch) and WIP (Write In Progress) are volatile read-only bits (WEL is set and reset by

specific instructions; WIP is automatically set and reset by the internal logic of the device).

Figure 11. Read Status Register (RDSR) instruction sequence and data-out

6.5 Write Status Register (WRSR)

Important note on page 6 for more details. instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 12. Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. ) signal (see Section 6.4.4). and Table 24: Timings after a Reset Low pulse). Figure 12. Write Status Register (WRSR) instruction sequence

The protection features of the device are summarized in Table 10.

• If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
• If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM2) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
• by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low
• or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM2), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.

Table 10. Protection modes (T9HX process only, see Important note on page 6)

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.

6.6 Read Data Bytes (READ)

R , during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. to be continued indefinitely. any effects on the cycle that is in progress. Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

6.7 Read Data Bytes at Higher Speed (FAST_READ)

A0) and a dummy Byte, each bit being latched-in during the rising edge of Serial Clock (C). C, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. 000000h, allowing the read sequence to be continued indefinitely. Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

6.8 Read Lock Register (RDLR)

falling edge of Serial Clock (C). The instruction sequence is shown in Figure 15. any time during data output. progress, is rejected without having any effects on the cycle that is in progress. Figure 15. Read Lock Register (RDLR) instruction sequence and data-out Sequence Table 11. Lock Registers except by a Reset or power-up. new values to them. (Default value). executed. The memory contents will not be changed. and will modify the sector contents. (Default value).

M25PE20, M25PE10 Instructions

6.9 Page Write (PW)

The Page Write (PW) instruction allows Bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Write (PW) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address Bytes and at least one data Byte on Serial Data Input (D). The rest of the page remains unchanged if no power failure occurs during this write cycle. The Page Write (PW) instruction performs a page erase cycle even if only one Byte is updated. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be written correctly within the same page. If less than

256 Data Bytes are sent to device, they are correctly written at the requested addresses

without having any effects on the other Bytes of the same page. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see Table 22: AC characteristics (50 MHz operation, T9HX (0.11µm) process)). Chip Select (S ) must be driven High after the eighth bit of the last data Byte has been latched in, otherwise the Page Write (PW) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration is tPW ) is initiated. While the Page Write cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 16. Page Write (PW) instruction sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

M25PE20, M25PE10 Instructions

6.10 Page Program (PP)

The Page Program (PP) instruction allows Bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address Bytes and at least one data Byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Table 22: AC characteristics (50 MHz operation, T9HX (0.11µm) process)). Chip Select (S ) must be driven High after the eighth bit of the last data Byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP ) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is Hardware Protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Page Program (PP) instruction sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

6.11 Write to Lock Register (WRLR)

device sets the Write Enable Latch (WEL). Figure 18. Chip Select (S latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed. progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Write to Lock Register (WRLR) instruction sequence Table 12. Lock Register In

6.12 Page Erase (PE)

Low for the entire duration of the sequence. The instruction sequence is shown in Figure 19. ) is driven High, the self-timed Page Erase cycle (whose duration is tPE ) is initiated. cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed. rejected without having any effects on the cycle that is in progress. Figure 19. Page Erase (PE) instruction sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

24 Bit Address

6.13 SubSector Erase (SSE)

The SubSector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. the SubSector (see Table 5) is a valid address for the SubSector Erase (SE) instruction. ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 21. unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. Hardware or software Protected is not executed. progress, is rejected without having any effects on the cycle that is in progress. Section 11: DC and AC parameters. Figure 20. SubSector Erase (SSE) instruction sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

6.14 Sector Erase (SE)

can be accepted, a Write Enable (WREN) instruction must previously have been executed. ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 21. time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. rejected without having any effects on the cycle that is in progress. Figure 21. Sector Erase (SE) instruction sequence

1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the

6.15 Bulk Erase (BE)

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 22. completed, the Write Enable Latch (WEL) bit is reset. tRHSL is then required before the device can be re-selected by driving Chip Select (S) Low. Figure 22. Bulk Erase (BE) instruction sequence

6.16 Deep Power-down (DP)

device ignores all Write, Program and Erase instructions. ICC2 , as specified in Table 19). Powers-up in Standby Power mode. entire duration of the sequence. The instruction sequence is shown in Figure 23. to ICC2 and the Deep Power-down mode is entered. progress, is rejected without having any effects on the cycle that is in progress. Figure 23. Deep Power-down (DP) instruction sequence

6.17 Release from Deep Power-down (RDP)

takes the device out of the Deep Power-down mode. driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 24. Low, cause the instruction to be rejected, and not executed. device waits to be selected, so that it can receive, decode and execute instructions. cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 24. Release from Deep Power-down (RDP) instruction sequence

Power-up and power-down M25PE20, M25PE10

7 Power-up and power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC ) until VCC reaches the correct value:

• VCC (min) at Power-up, and then for a further delay of tVSL
• VSS at Power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold value, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program (PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC (min). No Write, Program or Erase instructions should be sent until the later of:
• tPUW after VCC passed the VWI threshold
• tVSL after VCC passed the VCC (min) level These values are specified in Table 13. If the delay, tVSL , has elapsed, after VCC has risen above VCC (min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration of the Power-up and Power-down phases. At Power-up, the device is in the following state:
• The device is in the Standby Power mode (not the Deep Power-down mode).
• The Write Enable Latch (WEL) bit is reset.
• The Write In Progress (WIP) bit is reset
• The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0) Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)

Figure 25. Power-up timing Table 13. Power-up timing and VWI threshold

1. These parameters are characterized only, over the temperature range –40°C to +85°C.

8 Reset

(write, program or erase cycle) and data may be lost. All the Lock bits are reset to 0 after a Reset Low pulse. Table 14 shows the status of the device after a Reset Low pulse. Table 14. Device status after a Reset Low pulse

1. S remains Low while Reset is Low.

9 Initial delivery state

contains FFh). All usable Status Register bits are 0.

10 Maximum rating

Program and other relevant quality documents. Table 15. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

11 DC and AC parameters

match the measurement conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 26. AC measurement I/O waveform Table 16. Operating conditions Table 17. AC measurement conditions Table 18. Capacitance(1)

1. Sampled only, not 100% tested, at TA=25°C and a frequency of 20MHz.

Table 19. DC characteristics

Table 20. AC characteristics (25 MHz operation)

1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one

Table 21. AC characteristics (33 MHz operation)

1. Details of how to find the date of marking are given in Application Note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC
3. Value guaranteed by characterization, not 100% tested in production.

0.1 V/ns

1. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one

Table 22. AC characteristics (50 MHz operation, T9HX (0.11µm) process(1))(2) (3)

1. See Important note on page 6.
2. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 13: Part numbering.
3. Value guaranteed by characterization, not 100% tested in production.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence

including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).

Figure 29. Output timing

Figure 30. Reset AC waveforms Table 23. Reset conditions

1. Value guaranteed by characterization, not 100% tested in production.

Table 24. Timings after a Reset Low pulse(1)(2)

1. All the values are guaranteed by characterization, and not 100% tested in production.
2. See Table 14 for a description of the device status after a Reset Low pulse.
3. S remains Low while Reset is Low.

Figure 31. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline

Figure 32. VFQFPN8 (MLP8), 8-lead Very thin Fine Pitch Quad Flat Package No lead,

13 Part numbering

contact your nearest ST Sales Office. soldering conditions are also marked on the inner box label. Table 27. Ordering information scheme

1. Package only available for products in the T9HX process.

Table 28. Document revision history 21-Dec-2004 0.2 Notes 1 and 2 removed from Table 27: Ordering information scheme. S08N silhouette corrected on page 1. Added <Blue>Table 21., AC characteristics (33 MHz operation). Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns. Document converted to the new ST template. Section 12: Package mechanical). Section 7: Power-up and power-down). VIO max changed in Table 15: Absolute maximum ratings. – Status Register BP1, BP0 bits and SRWD bit added.