25P10AV

M25P10-A NUMONYX | Alldatasheet

Document overview

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• PDF pages: 51

Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Serial Data output (Q)
• 2.2 Serial Data input (D)
• 2.3 Serial Clock (C)
• 2.4 Chip Select (S
• 2.5 Hold (HOLD )
• 2.6 Write Protect (W )
• 3 SPI modes
• 4 Operating features
• 4.1 Page Programming
• 4.2 Sector Erase and Bulk Erase
• 4.3 Polling during a Write, Program or Erase cycle
• 4.4 Active Power, Standby Power and Deep Power-down modes
• 4.5 Status Register
• 4.6 Protection modes
• 4.7 Hold condition
• 5 Memory organization
• 6 Instructions
• 6.1 Write Enable (WREN)
• 6.2 Write Disable (WRDI)
• 6.3 Read Identification (RDID)
• 6.4 Read Status Register (RDSR)
• 6.4.1 WIP bit
• 6.4.2 WEL bit
• 6.4.3 BP1, BP0 bits
• 6.4.4 SRWD bit
• 6.5 Write Status Register (WRSR)

Features

■ 1 Mbit of Flash memory ■ Page Program (up to 256 bytes) in 1.4 ms (typical) ■ Sector Erase (256 Kbit) in 0.65 s (typical) ■ Bulk Erase (1 Mbit) in 1.7 s (typical) ■ 2.3 to 3.6 V single supply voltage ■ SPI bus compatible serial interface ■ 50 MHz Clock rate (maximum) ■ Deep Power-down mode 1 µA (typical) ■ Electronic signatures – JEDEC standard two-byte signature (2011h) – RES instruction, one-byte signature (10h), for backward compatibility ■ More than 20 years’ data retention ■ Packages – ECOPACK® (RoHS compliant) SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) UFDFPN8 (MB) 2x3m m www.numonyx.com

6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 31

Table 21. SO8 narrow – 8-lead plastic small outline, 150 mils body width, Table 22. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,

1 Description

protection mechanisms, accessed by a high speed SPI-compatible bus. wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes. using the Sector Erase instruction. Figure 1. Logic diagram Table 1. Signal names

Figure 2. SO, VFQFPN and UFDFPN8 connections

1. There is an exposed die paddle on the underside of th e MLP8 packages. This is pulled, internally, to VSS,

and must not be allowed to be connected to any other voltage or signal line on the PCB.

1. See Package mechanical section for package dimensions, and how to identify pin-1.

Signal descriptions M25P10-A

2 Signal descriptions

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S )

When this input signal is High, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

2.5 Hold (HOLD )

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

2.6 Write Protect (W )

The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).

3 SPI modes

• CPOL=0, CPHA=0
• CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Standby mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus master and memory devices on the SPI bus

1. The Write Protect (W ) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 4. SPI modes supported

M25P10-A Operating features

4 Operating features

4.1 Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t PP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP) and Table 16: Instruction times (device grade 6)).

4.2 Sector Era se and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration t SE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.

4.3 Polling during a Write, Program or Erase cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.

4.4 Active Power, Standby Power and Deep Power-down modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to I CC1. The Deep Power-down mode is entered when the specific instruction (the Deep Power- down (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down and Read Electronic Signature (RES) instruction) is executed. While in the Deep Power-down mode, the device ignores all write, program and erase instructions (see Deep Power-down (DP)). This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions.

Operating features M25P10-A

4.5 Status Register

The Status Register contains a number of status and control bits, as shown in Table 6, that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 6.4: Read Status Register (RDSR).

4.6 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P10-A features the following data protection mechanisms:

• Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification.
• Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
• All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Page Program (PP) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion
• The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read- only. This is the Software Protected mode (SPM).
• The Write Protect (W) signal, in co-operation with the Status Register Write Disable (SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be write-protected. This is the Hardware Protected mode (HPM).
• In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection, as all write, program and erase instructions are ignored.

4.7 Hold condition

Write Status Register, Program or Erase cycle that is currently in progress. coincides with Serial Clock (C) being Low (as shown in Figure 5). coincides with Serial Clock (C) being Low. Low. (This is shown in Figure 5). input (D) and Serial Clock (C) are Don’t care. from the moment of entering the Hold condition. the device from going back to the Hold condition. Table 2. Protected area sizes

1. The device is ready to accept a Bulk Erase instructi on if, and only if, both Block Protect (BP1, BP0) bits are

Figure 5. Hold condition activation

5 Memory organization

• 131,072 bytes (8 bits each)
• 4 sectors (256 Kbits, 32768 bytes each)
• 512 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.

Figure 6. Block diagram Table 3. Memory organization

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (S ) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ), Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power- down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S ) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. instruction code, and then driving Chip Select (S) High. Figure 7. Write Enable (WREN) instruction sequence Table 4. Instruction set

1. The Read Identification (RDID) instruction is avail able in products with process technology code X and Y

(see application note AN1995).

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit. instruction code, and then driving Chip Select (S) High.

• Power-up
• Write Disable (WRDI) instruction completion
• Write Status Register (WRSR) instruction completion
• Page Program (PP) instruction completion
• Sector Erase (SE) instruction completion
• Bulk Erase (BE) instruction completion

Figure 8. Write Disable (WRDI) instruction sequence

6.3 Read Identification (RDID)

and the memory capacity of the device in the second byte (11h). not decoded, and has no effect on the cycle that is in progress. the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. any time during data output. Figure 9. Read Identification (RDID) instruction sequence and data-out sequence Table 5. Read identification (RDID) data-out sequence

6.4 Read Status Register (RDSR)

also possible to read the Status Register continuously, as shown in Figure 10.

6.4.1 WIP bit

‘0’ no such cycle is in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

6.4.3 BP1, BP0 bits

6.4.4 SRWD bit

Table 6. Status Register format

Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 10. Read Status Register (RDSR) instruction sequence and data-out

6.5 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code and the data byte on Serial Data input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select ) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read- only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected mode (HPM) is entered. The protection features of the device are summarized in Table 7. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W ) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two cases need to be considered, depending on the state of Write Protect (W):

• If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction
• If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.

• by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low
• or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.

Figure 11. Write Status Register (WRSR) instruction sequence Table 7. Protection modes

1. As defined by the values in the Block Protect ( BP1, BP0) bits of the Status Register, as shown in Table 2.

6.6 Read Data Bytes (READ)

R, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. to be continued indefinitely. any effects on the cycle that is in progress. Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence

1. Address bits A23 to A17 are Don’t care.

6.7 Read Data Bytes at Higher Speed (FAST_READ)

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). C, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. 000000h, allowing the read sequence to be continued indefinitely. Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

1. Address bits A23 to A17 are Don’t care.

6.8 Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Table 16: Instruction times (device grade 6)). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Figure 14. Page Program (PP) instruction sequence

1. Address bits A23 to A17 are Don’t care.

6.9 Sector Erase (SE)

can be accepted, a Write Enable (WREN) instruction must previously have been executed. must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. (BP1, BP0) bits (see Table 3 and Table 2) is not executed. Figure 15. Sector Erase (SE) instruction sequence

1. Address bits A23 to A17 are Don’t care.

6.10 Bulk Erase (BE)

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 16. completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 16. Bulk Erase (BE) instruction sequence

6.11 Deep Power-down (DP)

ignores all write, program and erase instructions. issued while the device is in Deep Power-down mode. be output on Serial Data output (Q). powers-up in the Standby mode. entire duration of the sequence. The instruction sequence is shown in Figure 17. to ICC2 and the Deep Power-down mode is entered. progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) instruction sequence

6.12 Release from Deep Power- down and Read Electronic

Signature (RES) To take the device out of Deep Power-down mode, the Release from Deep Power-down and Read Electronic Signature (RES) instruction must be issued. No other instruction must be issued while the device is in Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic signature, whose value for the M25P10-A is 10h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the Deep Power-down mode has not been entered. Any release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S ) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge of Serial Clock (C). Then, the 8-bit electronic signature, stored in the memory, is shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 18. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S ) High after the electronic signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the electronic signature to be output repeatedly. When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by t RES2, and Chip Select (S) must remain High for at least tRES2(max), as specified in Table 18. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Driving Chip Select (S ) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by t RES1, and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 18. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

M25P10-A Power-up and power-down

7 Power-up and power-down

At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

• VCC(min) at power-up, and then for a further delay of tVSL
• VSS at power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of t PUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of:
• tPUW after VCC passed the VWI threshold
• tVSL after VCC passed the VCC(min) level These values are specified in Table 8. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for read instructions even if the tPUW delay is not yet fully elapsed. At power-up, the device is in the following state:
• The device is in the Standby mode (not the Deep Power-down mode).
• The Write Enable Latch (WEL) bit is reset.
• The Write In Progress (WIP) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1 µF). At power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if a power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result).

Figure 20. Power-up timing Table 8. Power-up timing and V WI threshold

1. These parameters ar e characterized only.

8 Initial delivery state

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

9 Maximum rating

and other relevant quality documents. Table 9. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020C (for sm all body, Sn-Pb or Pb assembly), the Numonyx

10 DC and AC parameters

match the measurement conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC measurement I/O waveform Table 10. Operating conditions

1. Only in products with process technology code Y . In products with process technology code X, Vcc(min) is

Table 11. Data retention and endurance Table 12. AC measurement conditions

1. Sampled only, not 100% tested, at T A = 25 °C and a frequency of 25 MHz.

Table 13. Capacitance Table 14. DC characteristics (device grade 6)

Table 15. DC characteristics (device grade 3) (1)

1. Only for products with process technology code X.

Table 16. Instruction times (device grade 6)

1. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
2. t PP=2μs+8μs*[int(n-1)/2+1]+4μs*[int(n-1)/2]+2μs, in products with process technology code X and Y .

Table 17. Instruction times (device grade 3) (1)

1. Only for products with process technology code X.
2. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are

Table 18. AC characteristics (25 MHz operation, device grade 6 or 3)

1. t CH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterizati on, not 100% tested in production.
3. Expressed as a slew-rate.

0.1 V/ns

1. Only applicable as a constr aint for a WRSR instruction when SRWD is set to ‘1’.
2. It is 30 µs in devices produced with the ‘X’ and ‘Y’ process technology (grade 3 devices are only produced

in the application note AN1995.

Table 19. AC characteristics (40 MHz operation, device grade 6)

40 MHz available for products marked since week 20 of 2004, only(1)

1. Details of how to find the date of mark ing are given in application note, AN1995.
2. t CH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterizati on, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constr aint for a WRSR instruction when SRWD is set to ‘1’.
6. It is 30 µs in devices produced with the ‘X’ and ‘Y’ process technology codes. Details of how to find the

process letter on the device marking are given in the application note AN1995.

Table 20. AC characteristics (50 MHz operation, device grade 6)

50 MHz available only in products with process technology code Y(1)(2)

1. Details of how to find the process on the devi ce marking are given in application note AN1995.
2. 50 MHz operation is also available in products with process technology code X, but with a reduced supply

voltage range (2.7 to 3.6 V).

1. t CH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterizati on, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constr aint for a WRSR instruction when SRWD is set at ‘1’.

conditions are also marked on the inner box label. Figure 26. SO8 narrow – 8-lead plastic small outline, 150 mils body width, package outline1. Drawing is not to scale.

1. The ‘1’ that appears in the top view of the package shows the position of pin 1.

Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,

1. The circle in the top view of the package indicates the position of pin 1.

Figure 28. UFDFPN8 (MLP8) 8-lead ultra th in fine pitch dual flat package no lead,

1. Dimension b applies to plated terminal and is meas ured between 0.15 and 0.30 mm from the terminal tip.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

12 Part numbering

of this device, please contact your nearest Numonyx Sales Office. Table 24. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C. (1) = Device tested with high reliability certified flow(2).

1. Device grade 3 available in an SO 8 ECOPACK® (RoHS compliant) package.
2. Numonyx strongly recommends the use of the Au tomotive Grade devices for use in an automotive

environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest Numonyx Sales Office for a copy.

1. The process letter (/X) is specified in t he ordering information of grade 3 devices only.

device package (marking) and on the shipment box. Please contact your nearest Numonyx Sales Office. AN1995: Serial Flash memory device marking.

1. Only available for grade 6 devices.

Table 25. Document revision history 25-Feb-2001 1.0 Document written. terminating an instruction sequence or data-out sequence. Protection mode again immediately after. 21-Feb-2003 1.3 Erroneous address ranges corrected in memory organization table. SO8 narrow package specifications updated. Notes 1 and 2 removed from Table 24: Ordering information scheme. Program (PP) and Table 16: Instruction times (device grade 6). Table 10, Table 11, Table 15, Table 17, Table 18 and Table 24). Table 11: Data retention and endurance added. characteristics (device grade 6). Table 14: DC characteristics (device grade 6) shows preliminary data. grade 3 added to Table 8: Power-up timing and VWI threshold. /X Process added to Table 24: Ordering information scheme.

“X” process technology in Table 18 and Table 19. Changed the minimum value for supply voltage. memory devices on the SPI bus. Note 1 to Table 13: Capacitance changed. Note 2 below Table 16: Instruction times (device grade 6) added. Changed test condition for ICC3 in Table 14 and fR in Table 20. Removed “low voltage” from the title. Small text changes. Typical values for Sector Erase and Bulk Erase modified. UFDFPN8 package (MLP8) added. Added the reference to a new process technology (code “Y”). /Y process added to Table 24: Ordering information scheme. 18-Oct-2007 10 Code of the UFDFPN8 package modified. 10-Dec-2007 11 Applied Numonyx branding. Table 25. Document revision history (continued)