M25P05 STMICROELECTRONICS | Alldatasheet
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512 Kbit, Low Voltage, Serial Flash Memory
signs (as described in application note AN1511). Figure 1. Packages
Serial Data Output (Q).This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be pro- grammed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address- es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S ).When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Pro- gram, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S ) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD ).The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be se- lected, with Chip Select (S ) driven Low. Write Protect (W).The main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
To program one data byte, two instructions are re- quired: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which con- sists of four bytes plus data. This is followed by the internal Program cycle (of duration t PP ). To spread this overhead, the Page Program (PP) instruction allows up to 128 bytes to be pro- grammed at a time (changing bits from 1 to 0), pro- vided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (t W , tPP , tSE , or tBE ). The Write In Progress (WIP) bit is provided in the Status Regis- ter so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is com- plete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (S ) is Low, the device is en- abled, and in the Active Power mode. When Chip Select (S) is High, the device is dis- abled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to I CC1 . The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I CC2 . The device re- mains in this mode until another specific instruc- tion (the Release from Deep Power-down Mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertant Write, Program or Erase instructions. Status Register The Status Register contains a number of status and control bits, as shown in Table 5, that can be read or set (as appropriate) by specific instruc- tions. WIP bit.The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit.The Write Enable Latch (WEL) bit indi- cates the status of the internal Write Enable Latch. BP1, BP0 bits.The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
Table 2. Protected Area Sizes eight, before they are accepted for execution. is the Software Protected Mode (SPM). Figure 6. Hold Condition Activation
The Hold (HOLD) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S ) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Fig- ure 6). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts when Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends when Se- rial Clock (C) next goes Low. (This is shown in Fig- ure 6). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. Normally, the device is kept selected, with Chip Select (S ) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the mo- ment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart commu- nication with the device, it is necessary to drive Hold (HOLD ) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition.
■ 512 pages (128 bytes each). Table 3. Memory Organization Figure 7. Block Diagram
128 Byte
128 Bytes (Page Size)
and out of the device, most significant bit first. latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. tion sequence has been shifted in. Low is an exact multiple of eight. Table 4. Instruction Set
Figure 10. Read Status Register (RDSR) Sequence ister continuously, as shown in Figure 10. Table 5. Status Register Format Note: 1. SRWD, BP1 and BP0 are non-volatile read and write bits.
- WEL and WIP are volatile read-only bits (WEL is set and
and reset by the internal logic of the device). cates the status of the internal Write Enable Latch. Erase instruction is accepted. ware Protected mode has not been set.
Figure 11. Write Status Register (WRSR) Sequence the Write Enable Latch (WEL). The instruction sequence is shown in Figure 11. Register. b6, b5 and b4 are always read as 0. ed, the Write Enable Latch (WEL) is reset.
Table 6. Protection Modes Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2. been set by a Write Enable (WREN) instruction. been set by a Write Enable (WREN) instruction. the Status Register Write Disable (SRWD) bit. the Status Register, can be used.
Figure 12. Read Data Bytes (READ) Sequence Note: 1. Address bits A23 to A16 must be set to 00h. The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. with a single Read Data Bytes (READ) instruction. the cycle that is in progress.
Figure 13. Page Program (PP) Sequence Note: 1. Address bits A23 to A16 must be set to 00h. en Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. check the value of the Write In Progress (WIP) bit. Enable Latch (WEL) bit is reset. bits (see Table 2) is not executed.
Figure 14. Sector Erase (SE) Sequence Note: 1. Address bits A23 to A16 must be set to 00h. ed, the device sets the Write Enable Latch (WEL). Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. bits (see Table 2) is not executed.
24 Bit Address
Figure 15. Bulk Erase (BE) Sequence The instruction sequence is shown in Figure 15. check the value of the Write In Progress (WIP) bit.
Figure 16. Deep Power-down (DP) Sequence Program and Erase instructions. The instruction sequence is shown in Figure 16.
Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Sequence Electronic Signature (RES) instruction. during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 17. tronic Signature has been read at least once. Electronic Signature to be output repeatedly.
Figure 18. Release from Deep Power-down (RES) Sequence RES ) before the device is put in Standby mode. tRES (max), as specified in Table 14.
VCC (min), and a further tVSL delay has elapsed. and the device will not respond to any instruction. VCC has risen above the VCC (min) level. These values are specified in Table 7. – The Write Enable Latch (WEL) bit is reset. Figure 19. Power-up Timing Table 7. Power-Up Timing and VWI Threshold Note: 1. These parameters are characterized only.
Table 8. Initial Status Register Format
Table 9. Absolute Maximum Ratings
Table 10. Operating Conditions Table 11. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 20. AC Measurement I/O Waveform Table 12. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.
Table 13. DC Characteristics
Table 14. AC Characteristics
- Value guaranteed by characterization, not 100% tested in production.
Figure 23. Output Timing
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width Note: Drawing is not to scale. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width SO-a E N CP B e A D C LA1 α H h x 45˚ Symb. mm inches A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N8 8 CP 0.10 0.004
Table 15. Ordering Information Scheme
REVISION HISTORY
Table 16. Document Revision History
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