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P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E MX25L8006E DATASHEET
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E 8M-BIT [x 1 / x 2] CMOS SERIAL FLASH
FEATURES
- Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
- Serial Peripheral Interface compatible -- Mode 0 and Mode 3
- 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (Dual Output mode) structure
- 256 Equal Sectors with 4K byte each - Any Sector can be erased individually
- 16 Equal Blocks with 64K byte each - Any Block can be erased individually
- Program Capability - Byte base - Page base (256 bytes)
- Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE
- High Performance - Fast access time: 86MHz serial clock - Serial clock of Dual Output mode : 80MHz - Fast program time: 0.6ms(typ.) and 3ms(max.)/page - Byte program time: 9us (typical) - Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block
- Low Power Consumption - Low active read current: 12mA(max.) at 86MHz - Low active programming current: 15mA (typ.) - Low active Sector/Block erase current: 9mA (typ.) - Low standby current: 15uA (typ.) - Deep power-down mode 2uA (typ.)
- Typical 100,000 erase/program cycles
- 20 years of data retention SOFTWARE FEATURES
- Input Data Format - 1-byte Command code
- Advanced Security Features - Block lock protection The BP2-BP0 status bit defines the size of the area to be software protection against program and erase instruc - tions - Additional 512 bit secured OTP for unique identifier
- Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
- Status Register Feature
- Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E - REMS command for 1-byte manufacturer ID and 1-byte device ID
- Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES
- PACKAGE - 8-pin SOP (150mil) - 8-pin SOP (200mil) - 8-pin PDIP (300mil) - 8-land WSON (6x5mm) - 8-land USON (4x4mm) - All devices are RoHS Compliant and Halogen-free GENERAL DESCRIPTION The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output. The device provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E PIN CONFIGURATIONS SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for Dual Output mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Output (for Dual Output mode) SCLK Clock Input WP# Write protection HOLD# Hold, to pause the device without deselecting the device VCC + 3.3V Power Supply GND Ground PIN DESCRIPTION8-LAND WSON (6x5mm), USON (4x4mm) 8-PIN SOP (200mil, 150mil) CS# SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 CS# SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 CS# SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 8-PIN PDIP (300mil)
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y-Decoder X-Decoder Data Register SRAM Buffer SI/SIO0 SCLK Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer SO/SIO1 CS#, WP#, HOLD#
Table 1. Memory Organization
- Before a command is issued, status register should be checked to ensure device is ready for the intended op -
- When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
- When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge. The CS# rising time needs to follow tCLCH spec.
- Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown in Figure 1.
- For the following instructions:RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, DREAD, RES, and
be rejected and not executed.
- During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect -
ed and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power- up and power-down or from system noise.
- Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
- Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion
- Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig - nature command (RES).
- Advanced Security Features: there are some protection and security features which protect content from inad - vertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM): MX25L8006E: use (BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP2 bits. Please refer to table of "protected area sizes". - The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L8006E:BP2-BP0 bits and SRWD bit.
Table 2. Protected Area Sizes
- Security register bit 0 indicates whether the chip is locked by factory or not.
through normal program procedure, and then exiting 512 bit secured OTP mode by writing EXSO command. register bit definition and table of "512 bit secured OTP definition" for address range definition. cured OTP mode, array access is not allowed. Table 3. 512 bit Secured OTP Definition
operation of write status register, programming, or erasing in progress. Figure 2. Hold Condition Operation the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Table 4. COMMAND DEFINITION Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in - struction setting the WEL bit. The sequence is shown as Figure 11. (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence is shown as Figure 12. The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence is shown as Figure 13. The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. BP2, BP1, BP0 bits. The Block Protect (BP2-BP0) bits, non-volatile bits, indicate the protected area (as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP2-BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2-BP0) are read only. (4) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad - vance. The WRSR instruction can change the value of Block Protect (BP2-BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence is shown as Figure 14. The WRSR instruction has no effect on b6, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Status Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) 0 0 BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1=status register write disable 0 0 (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit 0 0 Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit note 1: see the table "Protected Area Size".
Table 5. Protection Modes
- As defined by the values in the Block Protect (BP2-BP0) bits of the Status Register, as shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). SRWD, BP2-BP0. The protected area, which is defined by BP2-BP0, is at software protected mode (SPM). been set. It is rejected to write the Status Register and not be executed. protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. software protected mode via BP2-BP0.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E (5) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence is shown as Figure 15. (6) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence is shown as Figure 16. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im - pact on the Program/Erase/Write Status Register current cycle. (7) Dual Output Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maxi - mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc - tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc - tion, the data out will perform as 2-bit instead of previous 1-bit. The sequence is shown as Figure 17. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. throughputs. (8) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit be - fore sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence is shown as Figure 18.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2-BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (9) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 19. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2-BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (10) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc - tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex - ecuted. The sequence is shown as Figure 20. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP2-BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2- BP0 all set to "0". (11) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruc- tion will be rejected and not executed. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence is shown as Figure 21.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2-BP0 bits, the Page Program (PP) instruction will not be executed. (12) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter - ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac - tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence is shown as Figure 22. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Se - lect (CS#) must remain High for at least tRES2(max), as specified in Table 9. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown in Figure 23 and Figure 24. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat - edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode.
Manufacturer ID and Device ID are listed as table of "ID Definitions". The sequence is shown as Figure 25. cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. JEDEC assigned manufacturer ID and the specific device ID. instruction is completed by driving CS# high. Table 6. ID DEFINITIONS Secured OTP data cannot be updated again once it is lock-down. curity OTP is lock down, only read related commands are valid. The EXSO instruction is for exiting the additional 512 bit secured OTP mode.
at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence is shown as Figure 27. not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. area cannot be update any more. While it is in 512 bit secured OTP mode, array access is not allowed. Table 7. SECURITY REGISTER DEFINITION cured OTP area cannot be updated any more. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 28.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E (20) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence 21 3456789 10 28 29 30 31 22 21 3210 High-Z
24 BIT ADDRESS
32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 01 DATA OUT 1 Dummy Cycle MSB 7 6543210 DATA OUT 2 MSB MSB 765432 01 SCLK SI CS# SO SCLK SI CS# SO 5Ah Command
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E Table a. Signature and Parameter Identification Data Values Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) SFDP Signature Fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 01h 06h 23:16 01h 01h Unused 07h 31:24 FFh FFh ID number (JEDEC) 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Parameter Table Minor Revision Number Start from 00h 09h 15:08 00h 00h Parameter Table Major Revision Number Start from 01h 0Ah 23:16 01h 01h Parameter Table Length (in double word) How many DWORDs in the Parameter table 0Bh 31:24 09h 09h Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h Unused 0Fh 31:24 FFh FFh ID number (Macronix manufacturer ID) it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Parameter Table Minor Revision Number Start from 00h 11h 15:08 00h 00h Parameter Table Major Revision Number Start from 01h 12h 23:16 01h 01h Parameter Table Length (in double word) How many DWORDs in the Parameter table 13h 31:24 04h 04h Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h Unused 17h 31:24 FFh FFh
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E Table b. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase 30h 01:00 01b E5h Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b Write Enable Instruction Requested for Writing to Volatile Status Registers 0: Nonvolatitle status bit 1: Volatitle status bit (BP status register bit) 03 0b Write Enable Opcode Select for Writing to Volatile Status Registers 0: use 50h opcode, 1: use 06h opcode Note: If target flash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b Unused Contains 111b and can never be changed 07:05 111b 4KB Erase Opcode 31h 15:08 20h 20h (1-1-2) Fast Read (Note2) 0=not support 1=support 32h 16 1b 81h Address Bytes Number used in addressing flash array 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 18:17 00b Double Transfer Rate (DTR) Clocking 0=not support 1=support 19 0b (1-2-2) Fast Read 0=not support 1=support 20 0b (1-4-4) Fast Read 0=not support 1=support 21 0b (1-1-4) Fast Read 0=not support 1=support 22 0b Unused 23 1b Unused 33h 31:24 FFh FFh Flash Memory Density 37h:34h 31:00 007FFFFFh (1-4-4) Fast Read Number of Wait states (Note3) 0 0000b: Wait states (Dummy Clocks) not support 38h 04:00 0 0000b 00h(1-4-4) Fast Read Number of Mode Bits (Note4) 000b: Mode Bits not support 07:05 000b (1-4-4) Fast Read Opcode 39h 15:08 FFh FFh (1-1-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Ah 20:16 0 0000b 00h(1-1-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (1-1-4) Fast Read Opcode 3Bh 31:24 FFh FFh
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) (1-1-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Ch 04:00 0 1000b 08h(1-1-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 07:05 000b (1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh (1-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Eh 20:16 0 0000b 00h(1-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (1-2-2) Fast Read Opcode 3Fh 31:24 FFh FFh (2-2-2) Fast Read 0=not support 1=support 40h 00 0b EEh Unused 03:01 111b (4-4-4) Fast Read 0=not support 1=support 04 0b Unused 07:05 111b Unused 43h:41h 31:08 0xFFh 0xFFh Unused 45h:44h 15:00 0xFFh 0xFFh (2-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 46h 20:16 0 000b 00h(2-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh Unused 49h:48h 15:00 0xFFh 0xFFh (4-4-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 4Ah 20:16 0 0000b 00h(4-4-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist 4Ch 07:00 0Ch 0Ch Sector Type 1 erase Opcode 4Dh 15:08 20h 20h Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 4Eh 23:16 10h 10h Sector Type 2 erase Opcode 4Fh 31:24 D8h D8h Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 50h 07:00 00h 00h Sector Type 3 erase Opcode 51h 15:08 FFh FFh Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h Sector Type 4 erase Opcode 53h 31:24 FFh FFh
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E Table c. Parameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 36h 00h 36h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 00h 27h 00h 27h HW Reset# pin 0=not support 1=support 65h:64h 00 0b 4FF6h HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 0b SW Reset Opcode Reset Enable (66h) should be issued before Reset command 11:04 1111 1111b (FFh) Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b Unused 14 1b Wrap-Around Read mode 0=not support 1=support 15 0b Wrap-Around Read mode Opcode 66h 23:16 FFh FFh Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B 67h 31:24 FFh FFh Individual block lock 0=not support 1=support 6Bh:68h 00 0b CFFEh Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 1b Individual block lock Opcode 09:02 1111 1111b Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect 10 1b Secured OTP 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 0xFFh 0xFFh Unused 6Fh:6Ch 31:00 0xFFh 0xFFh
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: 0xFFh means all data is blank ("1b").
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed.(generally around 0.1uF) INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
- Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
to absolute maximum rating conditions for extended period may affect reliability.
- Specifications contained within the following tables are subject to change.
- During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Fig -
Figure 3. Maximum Negative Overshoot Waveform Figure 4. Maximum Positive Overshoot Waveform
Table 8. DC CHARACTERISTICS
- Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
Table 9. AC CHARACTERISTICS
- Value guaranteed by characterization, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
- Test condition is shown as Figure 5 & 6.
- The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec.
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
Figure 17. Dual Output Read Mode Sequence (Command 3B)
8 Bit Instruction 24 BIT Address 8 dummy
Figure 18. Sector Erase (SE) Sequence (Command 20) Figure 19. Block Erase (BE) Sequence (Command 52 or D8) Note: SE command is 20(hex). Note: BE command is 52 or D8(hex).
Figure 24. Read Electronic Signature (RES) Sequence (Command AB)
3 Dummy Bytes
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB) Figure 22. Deep Power-down (DP) Sequence (Command B9)
(2) Instruction is either 90(hex). Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
2 Dummy Bytes
Figure 25. Read Identification (RDID) Sequence (Command 9F)
Figure 29. Power-up Timing Note: 1. The parameter is characterized only. Table 10. Power-Up Timing
and power-down. If the timing in the figures is ignored, the device will not operate correctly. lected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
- Sampled, not 100% tested.
- For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Figure 30. AC Timing at Device Power-Up
Figure 31. Power-Down Sequence During power down, CS# need to follow the voltage drop on VCC to avoid mis-operation.
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E ERASE AND PROGRAMMING PERFORMANCE Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com - mand. 4. Erase/Program cycles comply with JEDEC: JESD-47 & JESD22-A117 standard. Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. LATCH-UP CHARACTERISTICS Parameter Min. Typ. (1) Max. (2) Unit Write Status Register Time 5 40 ms Sector Erase Time 40 200 ms Block Erase Time 0.4 2 s Chip Erase Time 3.5 6 s Byte Program Time (via page program command) 9 50 us Page Program Time 0.6 3 ms Erase/Program Cycle 100,000 cycles DATA RETENTION Parameter Condition Min. Max. Unit Data retention 55˚C 20 years
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
ORDERING INFORMATION
PART NO. CLOCK (MHz) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (uA) Temperature Package Remark MX25L8006EM1I-12G 86 12 25 -40°C~85°C 8-SOP (150mil) RoHS Compliant MX25L8006EM2I-12G 86 12 25 -40°C~85°C 8-SOP (200mil) RoHS Compliant MX25L8006EPI-12G 86 12 25 -40°C~85°C 8-PDIP (300mil) RoHS Compliant MX25L8006EZNI-12G 86 12 25 -40°C~85°C 8-WSON (6x5mm) RoHS Compliant MX25L8006EZUI-12G 86 12 25 -40°C~85°C 8-USON (4x4mm) RoHS Compliant
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E PART NAME DESCRIPTION MX 25 L 12ZN I G OPTION: G: RoHS Compliant & Halogen-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: ZN: WSON (0.8mm package height) ZU: USON (0.6mm package height) M1: 150mil 8-SOP M2: 200mil 8-SOP P: 300mil 8-PDIP DENSITY & MODE: 8006E: 8Mb TYPE: L: 3V DEVICE: 25: Serial Flash 8006E
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
PACKAGE INFORMATION
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E
REVISION HISTORY
Revision No. Description Page Date 1.1 1. Added RDSCUR & WRSCUR diagram form P38 SEP/02/2011 2. Added CS# rising and falling time description P10,28 4. Modified description for RoHS compliance P6,43,44 1.2 1. Added Read SFDP (RDSFDP) Mode P6,10,15, FEB/10/2012 P24~29,34 1.3 1. Modified ABSOLUTE MAXIMUM RATINGS table P31 SEP/05/2013 2. Modified WRSCUR Figure P44 1.4 1. Updated parameters for DC/AC Characteristics P33,34 NOV/06/2013 2. Updated Erase and Programming Performance P5,48
P/N: PM1613 REV. 1.4, NOV. 06, 2013 MX25L8006E MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2009~2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com