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P/N: PM1907 REV. 1.1, NOV. 06, 2013 MX25L6473E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION
P/N: PM1907 REV. 1.1, NOV. 06, 2013 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY 1. FEATURES GENERAL
- Serial Peripheral Interface compatible -- Mode 0 and Mode 3
- 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O mode) structure
- 2048 Equal Sectors with 4K bytes each - Any Sector can be erased individually
- 256 Equal Blocks with 32K bytes each - Any Block can be erased individually
- 128 Equal Blocks with 64K bytes each - Any Block can be erased individually
- Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
- Latch-up protected to 100mA from -1V to Vcc +1V
- Permanent fixed QE bit, QE =1 and 4 I/O mode is enabled PERFORMANCE
- High Performance VCC = 2.7~3.6V - Normal read - 50MHz - Fast read - 1 I/O: 104MHz with 8 dummy cycles - 2 I/O: 86MHz with 4 dummy cycles for 2READ instruction - 4 I/O: Up to 104MHz - Configurable dummy cycle number for 4 I/O read operation - Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 12us (typical) - Continuous Program mode (automatically increase address under word program mode) - Fast erase time: 30ms (typ.)/sector (4K-byte per sector) ; 0.25s(typ.) /block (64K-byte per block); 20s(typ.) / chip
- Low Power Consumption - Low active read current: 19mA(max.) at 104MHz, 10mA(max.) at 33MHz - Low active programming current: 15mA (typ.) - Low active sector erase current: 10mA (typ.) - Low standby current: 15uA (typ.) - Deep power down current: 1uA (typ.)
- Typical 100,000 erase/program cycles
- 20 years data retention
P/N: PM1907 REV. 1.1, NOV. 06, 2013 SOFTWARE FEATURES
- Input Data Format - 1-byte Command code
- Advanced Security Features - BP0-BP3 block group protect - Flexible individual block protect when OTP WPSEL=1 - Additional 4K bits secured OTP for unique identifier
- Auto Erase and Auto Program Algorithms - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programmed should have page in the erased state first.)
- Status Register Feature
- Electronic Identification - JEDEC 1-byte Manufacturer ID and 2-byte Device ID - RES command for 1-byte Device ID - The REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID
- Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES
- SCLK Input - Serial clock input
- SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
- SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
- SIO2 - Serial data Input/Output for 4 x I/O mode
- SIO3 - Serial data Input/Output for 4 x I/O mode
- PACKAGE - 16-pin SOP (300mil) - 8-pin SOP (200mil) - 8-pin VSOP (200mil) - 8-WSON (6x5mm) - All devices are RoHS Compliant and Halogen-free
rial access to the device is enabled by CS# input. SIO3 pin for address/dummy bits input and data Input/Output. block (32K-byte/64K-byte), or whole chip basis. read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. 100,000 program and erase cycles. Table 1. Read Performance
P/N: PM1907 REV. 1.1, NOV. 06, 2013 3. PIN CONFIGURATION 8-WSON (6x5mm) CS# SO/SIO1 SIO2 GND VCC SIO3 SCLK SI/SIO0 4. PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1xI/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O mode) SO/SIO1 Serial Data Output (for 1xI/O)/Serial Data Input & Output (for 2xI/O or 4xI/O mode) SCLK Clock Input SIO2 Serial Data Input & Output (for 4xI/O mode) SIO3 Serial data Input/Output for 4 x I/O mode VCC + 3.0V Power Supply GND Ground NC No Connection CS# SO/SIO1 SIO2 GND VCC SIO3 SCLK SI/SIO0 8-PIN SOP (200mil) 16-PIN SOP (300mil) SIO3 VCC NC NC NC NC CS# SO/SIO1 SCLK SI/SIO0 NC NC NC NC GND SIO2 8-PIN VSOP (200mil) CS# SO/SIO1 SIO2 GND VCC SIO3 SCLK SI/SIO0
P/N: PM1907 REV. 1.1, NOV. 06, 2013 5. BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y -Decoder X-Decoder Data Register SRAM Buffer SI/SIO0 SCLK SO/SIO1 Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer CS# SIO2 SIO3
P/N: PM1907 REV. 1.1, NOV. 06, 2013 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power-up and power-down or from system noise.
- Valid command length checking: The command length will be checked whether it is at byte base and complet - ed on byte boundary.
- Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - W rite Disable (WRDI) command completion - W rite Status Register (WRSR) command completion - Page Program (PP , 4PP) command completion - Continuous Program mo de (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE, BE32K) command completion - Chip Erase (CE) comma nd completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
- Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES). I. Block lock protection - The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be pro - tected as read only. The protected area definition is shown as table of "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various areas by setting value of BP0-BP3 bits. - MX25L647 3E provides individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with GBLK instruction and unlock the whole chip with GBULK instruction.
Table 2. Protected Area Sizes
device unique serial number - Which may be set by factory or system maker.
- Security register bit 0 ind icates whether the chip is locked by factory or not.
OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition
Table 4. Memory Organization
- Before a command is issued, status register should be checked to ensure device is ready for the intended op-
- When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
- When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
- For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported (for Normal Serial mode)".
- For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD,
byte boundary; otherwise, the instruction will be rejected and not executed.
- During the progress of Write Status Register, Program, Erase operation, to access the memory array is ne -
glected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported (for Normal Serial mode)
Table 5. Command Sets Note: * Dummy cycle number will be different, depending on the bit7 (DC) setting of Configuration Register.
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Other Commands Command WREN (write enable) WRDI (write disable) RDSR (read status register) RDCR (read configuration register) WRSR (write status/ configuration register) 4PP (quad page program) SE (sector erase) 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 38 (hex) 20 (hex) 2nd byte Values AD1 AD1 3rd byte Values AD2 AD2 4th byte AD3 AD3 Action sets the (WEL) write enable latch bit resets the (WEL) write enable latch bit to read out the values of the status register to read out the values of the configuration register to write new values of the status register quad input to program the selected page to erase the selected sector Command BE 32K (block erase 32KB) BE (block erase 64KB) CE (chip erase) PP (page program) CP (continuous program) DP (Deep power down) RDP (Release from deep power down) 1st byte 52 (hex) D8 (hex) 60 or C7 (hex) 02 (hex) AD (hex) B9 (hex) AB (hex) 2nd byte AD1 AD1 AD1 AD1 3rd byte AD2 AD2 AD2 AD2 4th byte AD3 AD3 AD3 AD3 Action to erase the selected 32KB block to erase the selected 64KB block to erase whole chip to program the selected page continuously program whole chip, the address is automatically increase enters deep power down mode release from deep power down mode Command RDID (read identific- ation) RES (read electronic ID) REMS (read electronic manufacturer & device ID) REMS2 (read electronic manufacturer & device ID) REMS4 (read electronic manufacturer & device ID) ENSO (enter secured OTP) 1st byte 9F (hex) AB (hex) 90 (hex) EF (hex) DF (hex) B1 (hex) 2nd byte x x x x 3rd byte x x x x 4th byte x ADD (Note 2) ADD ADD Action outputs JEDEC ID: 1-byte Manufacturer ID & 2-byte Device ID to read out 1-byte Device ID output the Manufacturer ID & Device ID output the Manufacturer ID & Device ID output the Manufacturer ID & device ID to enter the 4K-bit secured OTP mode
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Command EXSO (exit secured OTP) RDSCUR (read security register) WRSCUR (write security register) SBLK (single block lock SBULK (single block unlock) RDBLOCK (block protect read) GBLK (gang block lock) 1st byte C1 (hex) 2B (hex) 2F (hex) 36 (hex) 39 (hex) 3C (hex) 7E (hex) 2nd byte AD1 AD1 AD1 3rd byte AD2 AD2 AD2 4th byte AD3 AD3 AD3 Action to exit the 4K- bit secured OTP mode to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) individual block (64K-byte) or sector (4K-byte) write protect individual block (64K-byte) or sector (4K-byte) unprotect read individual block or sector write protect status whole chip write protect Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled. COMMAND GBULK (gang block unlock) NOP (No Operation) RSTEN (Reset Enable) RST (Reset Memory) WPSEL (Write Protect Selection) ESRY (enable SO to output RY/BY#) DSRY (disable SO to output RY/BY#) 1st byte 98 (hex) 00 (hex) 66 (hex) 99 (hex) 68 (hex) 70 (hex) 80 (hex) 2nd byte 3rd byte 4th byte Action whole chip unprotect to enter and enable individal block protect mode to enable SO to output RY/ BY# during CP mode to disable SO to output RY/ BY# during CP mode COMMAND Release Read Enhanced 1st byte FF (hex) 2nd byte 3rd byte 4th byte 5th byte Action All these commands FFh, 00h, AAh or 55h will escape the performance mode
ed to change the device content, should be set every time after the WREN instruction setting the WEL bit. The SIO[3:1] are don't care in this mode. Figure 2. Write Enable (WREN) Sequence (Command 06)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. Figure 3. Write Disable (WRDI) Sequence (Command 04)
Figure 4. Read Identification (RDID) Sequence (Command 9F) The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. dividual Device ID of second-byte ID are listed as table of "Table 7. ID Definitions". out on SO→ to end RDID operation can use CS# to high at any time during data out.
The SIO[3:1] are don't care when during this mode. Figure 5. Read Status Register (RDSR) Sequence (Command 05)
P/N: PM1907 REV. 1.1, NOV. 06, 2013 The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/ write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/ write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write en - able latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protect - ed area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected. QE bit. The Quad Enable (QE) bit, a non-volatile bit which is permanently set to "1". The flash always performs Quad I/O mode. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". Status Register Note: See the "Table 2. Protected Area Sizes" . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) QE (Quad Enable) BP3 (level of protected block) BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1=status register write disable 0=status register write enable 1= Quad Enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Configuration Register The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is set. TB bit The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed. Configuration Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DC (Dummy Cycle) Reserved Reserved Reserved TB (top/bottom selected) Reserved Reserved Reserved (Note) x x x 0=Top area protect 1=Bottom area protect (Default=0) x x x Volatile bit x x x OTP x x x Note: See "Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration Registers. Dummy Cycle and Frequency Table DC Numbers of Dummy clock cycles Quad I/O Fast Read 1 8 104 0 (default) 6 86
ter data on SI→ CS# goes high. Figure 6. Write Status Register (WRSR) Sequence (Command 01)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. able Latch (WEL) bit is reset. in "Table 2. Protected Area Sizes". Table 6. Protection Modes
Figure 7. WRSR flow
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. Figure 8. Read Data Bytes (READ) Sequence (Command 03)
24 ADD Cycles
0 when the highest address has been reached. can use CS# to high at any time during data out. escape from performance enhance mode and return to normal operation. impact on the Program/Erase/Write Status Register current cycle. Figure 9. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (104MHz)
24 BIT ADDRESS
ing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. high at any time during data out. pact on the Program/Erase/Write Status Register current cycle. Figure 10. Dual Read Mode Sequence (Command 3B)
ing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. 2READ operation can use CS# to high at any time during data out. impact on the Program/Erase/Write Status Register current cycle. Figure 11. 2 x I/O Read Mode Sequence (Command BB)
ing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. use CS# to high at any time during data out. pact on the Program/Erase/Write Status Register current cycle. Figure 12. Quad Read Mode Sequence (Command 6B)
ing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. SIO0→ to end 4READ operation can use CS# to high at any time during data out. dummy cycles. The clock rate runs at 54MHz. Figure 13. 4 x I/O Read Mode Sequence (Command EB)
8 Bit Instruction 6 Address cycles
- Hi-impedance is inhibited for the two clock cycles.
- P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
- The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and Fre-
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending 4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles (default)→ data out still CS# goes high → CS# goes low (reduce 4 Read instruc - tion) → 24-bit random access address (Please refer to "Figure 14. 4 x I/O Read enhance performance Mode Se- quence (Command EB)"). In the performance-enhancing mode (Notes of "Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any im - pact on the Program/Erase/Write Status Register current cycle. 9-12. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note "Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)") Please be noticed that “EBh” and “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” command to exit enhance mode. 9-13. Performance Enhance Mode Reset (FFh) To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in 1I/O sequence. If the system controller is being Reset during operation, the flash device will return to the standard operation. Upon Reset of main chip, Instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read (0Bh) would be issued. The SIO[3:1] are don't care when during this mode.
Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)
6 Address cycles
- Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
- The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and Frequen-
Figure 15. Performance Enhance Mode Reset for Fast Read Quad I/O
eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. The SIO[3:1] are don't care when during this mode. the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. (no change) and the WEL bit still be reset. Figure 16. Sector Erase (SE) Sequence (Command 20)
est eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. The SIO[3:1] are don't care when during this mode. the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. change) and the WEL bit still be reset. Figure 17. Block Erase (BE) Sequence (Command D8)
The SIO[3:1] are don't care when during this mode. the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. change) and the WEL bit still be reset. Figure 18. Block Erase 32KB (BE32K) Sequence (Command 52)
must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. The SIO[3:1] are don't care when during this mode. chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset. Figure 19. Chip Erase (CE) Sequence (Command 60 or C7)
SI→ at least 1-byte on data on SI→ CS# goes high. protected (no change) and the WEL bit will still be reset. The SIO[3:1] are don't care when during this mode. Figure 20. Page Program (PP) Sequence (Command 02)
down to 104MHz below. The other function descriptions are as same as standard page program. SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. change) and the WEL bit will still be reset. Figure 21. 4 x I/O Page Program (4PP) Sequence (Command 38)
6 ADD cycles Data
Figure 22. Program/Erase Flow(1) with read array data
- * Issue RDSR to check BP[3:0].
- If WPSEL=1, issue RDBLOCK to check the block status.
Figure 23. Program/Erase Flow(2) without read array data
- Issue RDSR to check BP[3:0].
- If WPSEL=1, issue RDBLOCK to check the block status.
P/N: PM1907 REV. 1.1, NOV. 06, 2013 9-20. Continuous Program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher ad- dress after each byte data has been programmed. The Continuous Program (CP) instruction is for multiple bytes program to Flash. A write Enable (WREN) in - struction must execute to set the Write Enable Latch (WEL) bit before sending the Continuous Program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before enter - ing next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after com - pletion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY commands are not accepted unless the completion of CP mode. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be pro - tected (no change) and the WEL bit will still be reset.
command (05 hex), RDSCUR command (2B hex), RSTEN command (66 hex) and RST command (99hex). goes high will return the SO pin to tri-state. CP mode is ended. Please be noticed that Software reset and Hardware reset can end the CP mode. Figure 24. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. The SIO[3:1] are don't care when during this mode. Figure 25. Deep Power-down (DP) Sequence (Command B9)
the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7. program/erase/write cycles in progress. The SIO[3:1] are don't care when during this mode. The RDP instruction is for releasing from Deep Power-down Mode. Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command
3 Dummy Bytes
Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB)
Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
- A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 are don't care.
- Instruction is either 90(hex) or EF(hex) or DF(hex).
ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 7. ID Definitions update data. The Secured OTP data cannot be updated again once it is lock-down. The SIO[3:1] are don't care when during this mode. The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode. The SIO[3:1] are don't care when during this mode.
at any time (even in program/erase/write status register/write security register condition) and continuously. Register data out on SO→ CS# goes high. The SIO[3:1] are don't care when during this mode. Figure 29. Read Security Register (RDSCUR) Sequence (Command 2B) or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock. OTP area cannot be updated any more. While it is in 4K-bit Secured OTP mode, array access is not allowed. "0" indicates not in CP mode; "1" indicates in CP mode. successful program operation.
Table 8. Security Register Definition
The SIO[3:1] are don't care when during this mode. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. Figure 30. Write Security Register (WRSCUR) Sequence (Command 2F) mode, the BP mode is disabled. The SIO[3:1] are don't care when during this mode. ARRAY is protected by BP3~BP0, where SRWD is bit 7 of status register that can be set by WRSR command.
Figure 33. The individual block lock mode is effective after setting WPSEL=1
- Power-Up: All SRAM bits=1 (all blocks are default protected). All arrays cannot be programmed/erased
- SBLK/SBULK(36h/39h): - SBLK(36h) : Set SRAM bit=1 (protect) : array can not be programmed /erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed /erased - All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected SRAM bits individually by SBLK/SBULK command set.
- GBLK/ GBULK(7Eh/98h): - GBLK(7Eh):Set all SRAM bits=1,whole chip are protected and cannot be programmed / erased. - GBULK(98h):Set all SRAM bits=0,whole chip are unprotected and can be programmed / erased. - All sectors and blocks SRAM bits of whole chip can be protected and unprotected at one time by GBLK/GBULK command set.
- RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK /SBLK/GBULK/GBLK command set.
Figure 34. WPSEL Flow
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. → send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. The SIO[3:1] are don't care when during this mode. Figure 35. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
Figure 36. Block Lock Flow
Figure 37. Block Unlock Flow
block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The SIO[3:1] are don't care when during this mode. Figure 38. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The SIO[3:1] are don't care when during this mode. Figure 39. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
The ESRY instruction is for outputting the ready/busy status to SO during CP mode. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The SIO[3:1] are don't care when during this mode. command. It returns the device to standby mode. The SIO[3:1] are don't care when during this mode. under processing could be damaged or lost. program operation than from other operations. Figure 40. Software Reset Recovery
can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216. Figure 41. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
Table 9. Signature and Parameter Identification Data Values
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) (1-1-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Ch 04:00 0 1000b 08h(1-1-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 07:05 000b (1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh (1-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Eh 20:16 0 0100b 04h(1-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh (2-2-2) Fast Read 0=not support 1=support 40h 00 0b EEh Unused 03:01 111b (4-4-4) Fast Read 0=not support 1=support 04 0b Unused 07:05 111b Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh (2-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 46h 20:16 0 0000b 00h(2-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh Unused 49h:48h 15:00 FFh FFh (4-4-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 4Ah 20:16 0 0000b 00h(4-4-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist 4Ch 07:00 0Ch 0Ch Sector Type 1 erase Opcode 4Dh 15:08 20h 20h Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 4Eh 23:16 0Fh 0Fh Sector Type 2 erase Opcode 4Fh 31:24 52h 52h Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h Sector Type 3 erase Opcode 51h 15:08 D8h D8h Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h Sector Type 4 erase Opcode 53h 31:24 FFh FFh
Table 11. Parameter Table (1): Macronix Flash Parameter Tables
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Note 1: h/b is hexadecimal or binary . Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh.
P/N: PM1907 REV. 1.1, NOV. 06, 2013 10. POWER-ON STATE The device is at below states when power-up: - Standby mode (please n ote it is not Deep Power-down mode) - W rite Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below cor - rect level: - VCC minimum at power- up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed. (generally around 0.1uF)
Table 12. DC Characteristics
- T ypical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and
- T ypical value is calculated by simulation.
- The value guaranteed by characterization, not 100% tested in production.
Table 13. AC Characteristics
1 I/O 5 ns
2 I/O & 4 I/O 6 ns
1 I/O 6 ns
1 I/O 7 ns
2 I/O & 4 I/O 8
P/N: PM1907 REV. 1.1, NOV. 06, 2013 Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. 2. The value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a WRSR instruction when SR WD is set at 1. 4. For 4READ instruction, when dummy cycle=6, clock rate is 86MHz (default), and when dummy cycle=8, clock rate is 104MHz. Symbol Alt. Parameter Min. Typ. Max. Unit tW Write Status Register Cycle Time 40 ms tBP Byte-Program 12 50 us tPP Page Program Cycle Time 0.7 3 ms tSE Sector Erase Cycle Time (4KB) 30 200 ms tBE Block Erase Cycle Time (32KB) 0.14 1.6 s tBE Block Erase Cycle Time (64KB) 0.25 2 s tCE Chip Erase Cycle Time 20 80 s tWPS Write Protection Selection Time 1 ms tWSR Write Security Register Time 1 ms
Register contains 00h (all Status Register bits are 0). Note: The parameter is characterized only. Table 14. Power-Up Timing Figure 48. Power-Up Timing
- Sampled, not 100% tested .
- For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer
to "Table 13. AC Characteristics". ignored, the device will not operate correctly. selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 49. AC Timing at Device Power-Up
Figure 50. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
P/N: PM1907 REV. 1.1, NOV. 06, 2013 14. ERASE AND PROGRAMMING PERFORMANCE Notes: 1. T ypical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V . 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com- mand. 15. DATA RETENTION Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. Parameter Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 ms Sector Erase Time (4KB) 30 200 ms Block Erase Time (32KB) 0.14 1.6 s Block Erase Time (64KB) 0.25 2 s Chip Erase Time 20 80 s Byte Program Time (via page program command) 12 50 us Page Program Time 0.7 3 ms Erase/Program Cycle 100,000 cycles 16. LATCH-UP CHARACTERISTICS Parameter Condition Min. Max. Unit Data retention 55˚C 20 years
P/N: PM1907 REV. 1.1, NOV. 06, 2013 17. ORDERING INFORMATION PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark MX25L6473EMI-10G * 104 -40°C~85°C 16-SOP (300mil) MX25L6473EM2I-10G 104 -40°C~85°C 8-SOP (200mil) MX25L6473EMBI-10G 104 -40°C~85°C 8-VSOP (200mil) MX25L6473EZNI-10G 104 -40°C~85°C 8-WSON (6x5mm) * Advanced Information.
P/N: PM1907 REV. 1.1, NOV. 06, 2013 18. PART NAME DESCRIPTION MX 25 L M I TEMPERATURE RANGE: I: Industrial (-40° C to 85° C) PACKAGE: M: 300mil 16-SOP M2: 200mil 8-SOP MB: 200mil 8-VSOP ZN: 6x5mm 8-WSON DENSITY & MODE: 6473E: 64Mb standard type TYPE: L: 3V DEVICE: 25: Serial Flash 6473E 10 G OPTION: G: RoHS Compliant and Halogen-free SPEED: 10: 104MHz
P/N: PM1907 REV. 1.1, NOV. 06, 2013 19. PACKAGE INFORMATION
P/N: PM1907 REV. 1.1, NOV. 06, 2013
P/N: PM1907 REV. 1.1, NOV. 06, 2013
P/N: PM1907 REV. 1.1, NOV. 06, 2013
P/N: PM1907 REV. 1.1, NOV. 06, 2013 20. REVISION HISTORY Revision No. Description Page Date 0.00 1. Initial releas ed All NOV/02/2012 1.0 1. Removed Advanced Information state P4 DEC/25/2012 2. Kept MX25L6473EMI-10G as Advanced Information P79 1.1 1. Updated parameters for DC/AC Characteristics P4,71,73 NOV/06/2013 2. Updated Erase and Programming Performance P4,78 3. Modified VCC to Ground Potential & Capacitance table P69
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