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REV. 1.6, FEB. 17, 2009 P/N: PM1214 512K-BIT [x 1] CMOS SERIAL FLASH

FEATURES

  • Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
  • 524,288 x 1 bit structure
  • 16 Equal Sectors with 4K byte each - Any Sector can be erased individually
  • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
  • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE
  • High Performance - Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load) - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/chip(512Kb)
  • Low Power Consumption - Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz - Low active programming current: 15mA (max.) - Low active erase current: 15mA (max.) - Low standby current: 10uA (max.) - Deep power-down mode 1uA (typical)
  • Minimum 100,000 erase/program cycles SOFTWARE FEATURES
  • Input Data Format - 1-byte Command code
  • Block Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in - structions.
  • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
  • Status Register Feature
  • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID HARDWARE FEATURES
  • SCLK Input - Serial clock input MX25L512

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512

  • SI Input - Serial Data Input
  • SO Output - Serial Data Output
  • WP# pin - Hardware write protection
  • HOLD# pin - pause the chip without diselecting the chip
  • PACKAGE - 8-pin SOP (150mil) - 8-USON (2x3mm) - All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512 features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. MX25L512 provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the spec- ified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC cur - rent. The MX25L512 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 PIN CONFIGURATIONS SYMBOL DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without deselecting the device WP# Write Protection VCC + 3.3V Power Supply GND Ground PIN DESCRIPTION 8-PIN SOP (150mil) CS# SO WP# GND VCC HOLD# SCLK SI 8-LAND USON (2x3mm) CS# SO WP# GND VCC HOLD# SCLK SI

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y-Decoder X-Decoder Data Register SRAM Buffer SI SCLK Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer SO CS#

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 DATA PROTECTION MX25L512 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state ma - chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

  • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
  • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion
  • Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
  • Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change.
  • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig - nature command (RES).

Table 1. Protected Area Sizes operation of write status register, programming, or erasing in progress. Clock being low), see Figure 1. the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. Figure 1. Hold Condition Operation

Table 2. COMMAND DEFINITION (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) BE command may erase whole 512Kb chip. (3) It is not recommended to adopt any other code which is not in the above command definition table.

  1. Before a command is issued, status register should be checked to ensure device is ready for the intended op -
  2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode

until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

  1. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
  2. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.

The difference of SPI mode 0 and mode 3 is shown as Figure 2. Figure 2. SPI Modes Supported

  1. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction se -

byte boundary; otherwise, the instruction will be rejected and not executed.

  1. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect -

ed and not affect the current operation of Write Status Register, Program, Erase. Table 3. Memory Organization

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register data out on SO (see Figure. 14) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec - tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only. Note: 1. See the table "Protected Area Sizes". 2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) 0 0 0 BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1=status register write disable (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation

Protected Mode (HPM) is entered. The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. Table 4. Protection Modes

  1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.

As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard - ware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im - pact on the Program/Erase/Write Status Register current cycle. (8) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in - struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 19)

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (9) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in - struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 20) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (10) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc - tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex - ecuted. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see Figure 20) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0". (11) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig - nificant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7- A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 (12) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter - ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac - tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see Fig- ure 22) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 23,24. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat - edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. at least 1-byte on data on SI→ CS# goes high. (see Figure 18) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 (14) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi - ated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of ID Definitions on page 16. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: RDID Command manufacturer ID memory type memory density C2 20 10 RES Command electronic ID REMS Command manufacturer ID device ID C2 05

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed.(generally around 0.1uF)

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Expo - sure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. ABSOLUTE MAXIMUM RATINGS ELECTRICAL SPECIFICATIONS CAPACITANCE TA = 25°C, f = 1.0 MHz Figure 3.Maximum Negative Overshoot Waveform Figure 4. Maximum Positive Overshoot Waveform RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Commercial grade 0°C to 70°C Storage Temperature -55°C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS CIN Input Capacitance 6 pF VIN = 0V COUT Output Capacitance 8 pF VOUT = 0V -0.5V 20ns 4.6V 3.6V 20ns

Table 5. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, Temperature = 0°C to

  1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
  2. Typical value is calculated by simulation.
  1. tCH + tCL must be greater than or equal to 1/ fC
  2. Value guaranteed by characterization, not 100% tested in production.
  3. Expressed as a slew-rate.
  4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
  5. Test condition is shown as Figure 3.

Table 6. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, Temperature = 0°C to

Register contains 00h (all Status Register bits are 0). Table 7. Power-Up Timing Note: 1. The parameter is characterized only.

Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

24 BIT ADDRESS

Figure 18. Page Program (PP) Sequence (Command 02)

Figure 19. Sector Erase (SE) Sequence (Command 20) Note: SE command is 20(hex). Figure 20. Block Erase (BE) Sequence (Command 52 or D8) Note: BE command is 52 or D8(hex).

Figure 21. Chip Erase (CE) Sequence (Command 60 or C7) Figure 22. Deep Power-down (DP) Sequence (Command B9) Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) Note: CE command is 60(hex) or C7(hex).

3 Dummy Bytes

Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)

2 Dummy Bytes

Figure 26. Power-up Timing

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Figure A. AC Timing at Device Power-Up Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. Symbol Parameter Notes Min. Max. Unit tVR VCC Rise Time 1 0.5 500000 us/V SCLK SI CS# VCC MSB IN SO tDVCH High Impedance LSB IN tSLCH tCHDX tCHCL tCLCH tSHCH tSHSL tCHSHtCHSL tVR VCC(min) GND

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 ERASE AND PROGRAMMING PERFORMANCE PARAMETER Min. TYP. (1) Max. (2) UNIT Write Status Register Cycle Time 5 15 ms Sector erase Time 60 120 ms Block erase Time 1 2 s Chip Erase Time 1 2 s Page Program Time 1.4 5 ms Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com - mand. MIN. MAX. Input Voltage with respect to GND on ACC -1.0V 12.5V Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. LATCH-UP CHARACTERISTICS

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 PART NO. CLOCK (MHz) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (uA) Temperature PACKAGE Remark MX25L512MC-12G 85 12 10 0~70°C 8-SOP (150mil) Pb-free MX25L512MI-12G 85 12 10 -40~85°C 8-SOP (150mil) Pb-free MX25L512ZUI-12G 85 12 10 -40~85°C 8-USON (2x3mm) Pb-free

ORDERING INFORMATION

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512 PART NAME DESCRIPTION MX 25 L 12 M I G OPTION: G: Pb-free blank: normal SPEED: 12: 85MHz TEMPERATURE RANGE: I: Industrial (-40Ċ to 85Ċ) C: Commercial (0Ċ to 70Ċ) PACKAGE: M: 150mil 8-SOP ZU: 2x3mm 8-USON DENSITY & MODE: 512: 512Kb TYPE: L: 3V DEVICE: 25: Serial Flash 512

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512

PACKAGE INFORMATION

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512

P/N: PM1214 REV. 1.6, FEB. 17, 2009 MX25L512

REVISION HISTORY

Revision No. Description Page Date 1.0 1. Modified read current:6mA@85MHz/4mA@66MHz/2mA@33MHz P1,18,33 OCT/03/2005 → 12mA@85MHz/8mA@66MHz/4mA@33MHz 2. Modified tSE:90ms(typ)/270ms(max)→60ms(typ)/120ms(max) ; P1,19,32 tBE:3s(max)→2s(max); tCE:3s(max)→2s(max) 3. Added description about Pb-free device is RoHS compliant P1 4. Removed "Advanced Information" title P1 5. Added C-grade part number P33 1.1 1. Format change All JUN/08/2006 2. Supplemented the footnote for tW of protect/unprotect bits P9 1.2 1. Added statement P38 NOV/06/2006 1.3 1. Defined min. clock frequency of fSCLK & fRSCLK as 1KHz P20 NOV/30/2006 1.4 1. Removed 8-land SON package and order information P2,3,34,35 MAR/24/2008 1.5 1. Removed wrong Block Protect bit: BP2 P5,11 AUG/12/2008 2. Removed non Pb-free EPN P34,35 1.6 1. Modified Figure 13, 14, 16, 17, 23 (waveform) P24,25,26,29 FEB/17/2009 2. Added 8-USON package P3,34,37 3. Removed "Low Vcc write inhibit" function P1,5,16,21,31 4. Changed tCH/tCL spec from 7/7(ns) to 5.5/5.5(ns) P20

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