Memory

25L1605

Macronix International

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Manufacturer: Macronix International

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MX25L1605D MCNIX | Alldatasheet

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Technical content

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH 32M-BIT [x 1 / x 2] CMOS SERIAL FLASH 64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

FEATURES

Serial Peripheral Interface compatible -- Mode 0 and Mode 3
16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure 32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure 64M:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure 512 Equal Sectors with 4K byte each (16Mb)

1024 Equal Sectors with 4K byte each (32Mb)

2048 Equal Sectors with 4K byte each (64Mb)

Any Sector can be erased individually 32 Equal Blocks with 64K byte each (16Mb)

64 Equal Blocks with 64K byte each (32Mb)

128 Equal Blocks with 64K byte each (64Mb)

Any Block can be erased individually Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations Latch-up protected to 100mA from -1V to Vcc +1V Low Vcc write inhibit is from 1.5V to 2.5V PERFORMANCE High Performance - Fast access time: 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load) - Serial clock of two I/O read mode : 50MHz (15pF + TTL Load), which is equivalent to 100MHz - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously program mode (automatically increase address under word program mode) - Fast erase time: 60ms(typ.) /sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip for 16Mb, 25s(typ.) for 32Mb, and 50s(typ.) for 64Mb Low Power Consumption - Low active read current: 25mA(max.) at 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 20uA (max.) - Deep power-down mode 1uA (typical) Typical 100,000 erase/program cycles SOFTWARE FEATURES Input Data Format - 1-byte Command code Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 512-bit secured OTP for unique identifier Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1290 REV. 1.4, OCT. 01, 2008 MX25L1605D MX25L3205D MX25L6405D

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Status Register Feature Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES SCLK Input - Serial clock input SI Input - Serial Data Input SO Output - Serial Data Output WP#/ACC pin - Hardware write protection and program/erase acceleration HOLD# pin - pause the chip without diselecting the chip PACKAGE - 16-pin SOP (300mil) - 8-land WSON (8x6mm or 6x5mm) - 8-pin SOP (200mil, 150mil) - 8-pin PDIP (300mil) - 8-land USON (4x4mm) - All Pb-free devices are RoHS Compliant ALTERNATIVE Security Serial Flash (MX25L1615D/MX25L3215D/MX25L6415D) may provides additional protection features for op- tion. The datasheet is provided under NDA. GENERAL DESCRIPTION The MX25L1605D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in two I/O read mode, the structure becomes 8,388,608 bits x 2. The MX25L3205D are 33,554,432 bit serial Flash memory, which is configured as 4,194,304 x 8 internally. When it is in two I/O read mode, the structure becomes 16,772,216 bits x 2. The MX25L6405D are 67,108,864 bit serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two I/O read mode, the structure becomes 33,554,432 bits x 2. (please refer to the "Two I/O Read mode" section). The MX25L1605D/3205D/6405D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. The MX25L1605D/3205D/6405D provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis.

Table 1. Additional Feature Comparison command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current. after typical 100,000 program and erase cycles.

2 I/O Read

P/N: PM1290 REV. 1.4, OCT. 01, 2008 PIN CONFIGURATIONS SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O read mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O read mode) SCLK Clock Input WP#/ACC W rite protection: connect to GND ; 9.5~10.5V for program/erase acceleration: connect to 9.5~10.5V HOLD# Hold, to pause the device without deselecting the device VCC + 3.3V Power Supply GND Ground PIN DESCRIPTION 16-PIN SOP (300mil) 8-LAND WSON (8x6mm, 6x5mm), USON (4x4mm) 8-PIN SOP (200mil, 150mil) PACKAGE OPTIONS 16M 32M 64M 150mil 8-SOP V 200mil 8-SOP V V 300mil 16-SOP V V V 300mil 8-PDIP V V 6x5mm WSON V V 8x6mm WSON V 4x4mm USON V V HOLD# VCC NC NC NC NC CS# SO/SIO1 SCLK SI/SIO0 NC NC NC NC GND WP#/ACC CS# SO/SIO1 WP#/ACC GND VCC HOLD# SCLK SI/SIO0 CS# SO/SIO1 WP#/ACC GND VCC HOLD# SCLK SI/SIO0 CS# SO/SIO1 WP#/ACC GND VCC HOLD# SCLK SI/SIO0 8-PIN PDIP (300mil)

P/N: PM1290 REV. 1.4, OCT. 01, 2008 BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y -Decoder X-Decoder Data Register SRAM Buffer SI/SIO0 SCLK Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer SO/SIO1 CS#, WP#/ACC, HOLD#

P/N: PM1290 REV. 1.4, OCT. 01, 2008 DATA PROTECTION The MX25L1605D/3205D/6405D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and tPUW (internal timer) may protect the Flash. Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion - Write Read-lock Bit (WRLB) instruction completion Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). Advanced Security Features: there are some protection and securuity features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Proteced Mode (HPM) use WP#/ACC to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.

Security register bit 0 indicates whether the chip is locked by factory or not.

normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command. definition and table of "512-bit secured OTP definition" for address range definition. mode, array access is not allowed. Table 3. 512-bit Secured OTP Definition Table 2. Protected Area Sizes

Table 4. COMMAND DEFINITION

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Table 5-1. Memory Organization (16Mb) Block 511 496 1FF000h 1F0000h 1FFFFFh 1F0FFFh Sector Address Range 495 480 1EF000h 1E0000h 1EFFFFh 1E0FFFh 479 464 1DF000h 1D0000h 1DFFFFh 1D0FFFh 463 448 1CF000h 1C0000h 1CFFFFh 1C0FFFh 447 432 1BF000h 1B0000h 1BFFFFh 1B0FFFh 431 416 1AF000h 1A0000h 1AFFFFh 1A0FFFh 415 400 19F000h 190000h 19FFFFh 190FFFh 399 384 18F000h 180000h 18FFFFh 180FFFh 383 368 17F000h 170000h 17FFFFh 170FFFh 367 352 16F000h 160000h 16FFFFh 160FFFh 351 336 15F000h 150000h 15FFFFh 150FFFh 335 320 14F000h 140000h 14FFFFh 140FFFh 319 304 13F000h 130000h 13FFFFh 130FFFh 303 288 12F000h 120000h 12FFFFh 120FFFh 287 272 11F000h 110000h 11FFFFh 110FFFh 271 256 10F000h 100000h 10FFFFh 100FFFh Block 255 240 0FF000h 0F0000h 0FFFFFh 0F0FFFh Sector Address Range 239 224 0EF000h 0E0000h 0EFFFFh 0E0FFFh 223 208 0DF000h 0D0000h 0DFFFFh 0D0FFFh 207 192 0CF000h 0C0000h 0CFFFFh 0C0FFFh 191 176 0BF000h 0B0000h 0BFFFFh 0B0FFFh 175 160 0AF000h 0A0000h 0AFFFFh 0A0FFFh 159 144 09F000h 090000h 09FFFFh 090FFFh 143 128 08F000h 080000h 08FFFFh 080FFFh 127 112 07F000h 070000h 07FFFFh 070FFFh 111 06F000h 060000h 06FFFFh 060FFFh 05F000h 050000h 05FFFFh 050FFFh 04F000h 040000h 04FFFFh 040FFFh 03F000h 030000h 03FFFFh 030FFFh 02F000h 020000h 02FFFFh 020FFFh 01F000h 010000h 01FFFFh 010FFFh 00F000h 004000h 00FFFFh 004FFFh 3 003000h 003FFFh 2 002000h 002FFFh 1 001000h 001FFFh 0 000000h 000FFFh

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Table 5-2. Memory Organization (32Mb) Block 1023 1008 3FF000h 3F0000h 3FFFFFh 3F0FFFh Sector Address Range 1007 992 3EF000h 3E0000h 3EFFFFh 3E0FFFh 991 976 3DF000h 3D0000h 3DFFFFh 3D0FFFh 975 960 3CF000h 3C0000h 3CFFFFh 3C0FFFh 959 944 3BF000h 3B0000h 3BFFFFh 3B0FFFh 943 928 3AF000h 3A0000h 3AFFFFh 3A0FFFh 927 912 39F000h 390000h 39FFFFh 390FFFh 911 896 38F000h 380000h 38FFFFh 380FFFh 895 880 37F000h 370000h 37FFFFh 370FFFh 879 864 36F000h 360000h 36FFFFh 360FFFh 863 848 35F000h 350000h 35FFFFh 350FFFh 847 832 34F000h 340000h 34FFFFh 340FFFh 831 816 33F000h 330000h 33FFFFh 330FFFh 815 800 32F000h 320000h 32FFFFh 320FFFh 799 784 31F000h 310000h 31FFFFh 310FFFh 783 768 30F000h 300000h 30FFFFh 300FFFh Block 767 752 2FF000h 2F0000h 2FFFFFh 2F0FFFh Sector Address Range 751 736 2EF000h 2E0000h 2EFFFFh 2E0FFFh 735 720 2DF000h 2D0000h 2DFFFFh 2D0FFFh 719 704 2CF000h 2C0000h 2CFFFFh 2C0FFFh 703 688 2BF000h 2B0000h 2BFFFFh 2B0FFFh 687 672 2AF000h 2A0000h 2AFFFFh 2A0FFFh 671 656 29F000h 290000h 29FFFFh 290FFFh 655 640 28F000h 280000h 28FFFFh 280FFFh 639 624 27F000h 270000h 27FFFFh 270FFFh 623 608 26F000h 260000h 26FFFFh 260FFFh 607 592 25F000h 250000h 25FFFFh 250FFFh 591 576 24F000h 240000h 24FFFFh 240FFFh 575 560 23F000h 230000h 23FFFFh 230FFFh 559 544 22F000h 220000h 22FFFFh 220FFFh 543 528 21F000h 210000h 21FFFFh 210FFFh 527 512 20F000h 200000h 20FFFFh 200FFFh

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Block 511 496 1FF000h 1F0000h 1FFFFFh 1F0FFFh Sector Address Range 495 480 1EF000h 1E0000h 1EFFFFh 1E0FFFh 479 464 1DF000h 1D0000h 1DFFFFh 1D0FFFh 463 448 1CF000h 1C0000h 1CFFFFh 1C0FFFh 447 432 1BF000h 1B0000h 1BFFFFh 1B0FFFh 431 416 1AF000h 1A0000h 1AFFFFh 1A0FFFh 415 400 19F000h 190000h 19FFFFh 190FFFh 399 384 18F000h 180000h 18FFFFh 180FFFh 383 368 17F000h 170000h 17FFFFh 170FFFh 367 352 16F000h 160000h 16FFFFh 160FFFh 351 336 15F000h 150000h 15FFFFh 150FFFh 335 320 14F000h 140000h 14FFFFh 140FFFh 319 304 13F000h 130000h 13FFFFh 130FFFh 303 288 12F000h 120000h 12FFFFh 120FFFh 287 272 11F000h 110000h 11FFFFh 110FFFh 271 256 10F000h 100000h 10FFFFh 100FFFh Block 255 240 0FF000h 0F0000h 0FFFFFh 0F0FFFh Sector Address Range 239 224 0EF000h 0E0000h 0EFFFFh 0E0FFFh 223 208 0DF000h 0D0000h 0DFFFFh 0D0FFFh 207 192 0CF000h 0C0000h 0CFFFFh 0C0FFFh 191 176 0BF000h 0B0000h 0BFFFFh 0B0FFFh 175 160 0AF000h 0A0000h 0AFFFFh 0A0FFFh 159 144 09F000h 090000h 09FFFFh 090FFFh 143 128 08F000h 080000h 08FFFFh 080FFFh 127 112 07F000h 070000h 07FFFFh 070FFFh 111 06F000h 060000h 06FFFFh 060FFFh 05F000h 050000h 05FFFFh 050FFFh 04F000h 040000h 04FFFFh 040FFFh 03F000h 030000h 03FFFFh 030FFFh 02F000h 020000h 02FFFFh 020FFFh 01F000h 010000h 01FFFFh 010FFFh 00F000h 004000h 00FFFFh 004FFFh 3 003000h 003FFFh 2 002000h 002FFFh 1 001000h 001FFFh 0 000000h 000FFFh

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Table 5-3. Memory Organization (64Mb) Block 127 2047 2032 7FF000h 7F0000h 7FFFFFh 7F0FFFh Sector Address Range 126 2031 2016 7EF000h 7E0000h 7EFFFFh 7E0FFFh 125 2015 2000 7DF000h 7D0000h 7DFFFFh 7D0FFFh 124 1999 1984 7CF000h 7C0000h 7CFFFFh 7C0FFFh 123 1983 1968 7BF000h 7B0000h 7BFFFFh 7B0FFFh 122 1967 1952 7AF000h 7A0000h 7AFFFFh 7A0FFFh 121 1951 1936 79F000h 790000h 79FFFFh 790FFFh 120 1935 1920 78F000h 780000h 78FFFFh 780FFFh 119 1919 1904 77F000h 770000h 77FFFFh 770FFFh 118 1903 1888 76F000h 760000h 76FFFFh 760FFFh 117 1887 1872 75F000h 750000h 75FFFFh 750FFFh 116 1871 1856 74F000h 740000h 74FFFFh 740FFFh 115 1855 1840 73F000h 730000h 73FFFFh 730FFFh 114 1839 1824 72F000h 720000h 72FFFFh 720FFFh 113 1823 1808 71F000h 710000h 71FFFFh 710FFFh 112 1807 1792 70F000h 700000h 70FFFFh 700FFFh Block 111 1791 1776 6FF000h 6F0000h 6FFFFFh 6F0FFFh Sector Address Range 110 1775 1760 6EF000h 6E0000h 6EFFFFh 6E0FFFh 109 1759 1744 6DF000h 6D0000h 6DFFFFh 6D0FFFh 108 1743 1728 6CF000h 6C0000h 6CFFFFh 6C0FFFh 107 1727 1712 6BF000h 6B0000h 6BFFFFh 6B0FFFh 106 1711 1696 6AF000h 6A0000h 6AFFFFh 6A0FFFh 105 1695 1680 69F000h 690000h 69FFFFh 690FFFh 104 1679 1664 68F000h 680000h 68FFFFh 680FFFh 103 1663 1648 67F000h 670000h 67FFFFh 670FFFh 102 1647 1632 66F000h 660000h 66FFFFh 660FFFh 101 1631 1616 65F000h 650000h 65FFFFh 650FFFh 100 1615 1600 64F000h 640000h 64FFFFh 640FFFh 1599 1584 63F000h 630000h 63FFFFh 630FFFh 1583 1568 62F000h 620000h 62FFFFh 620FFFh 1567 1552 61F000h 610000h 61FFFFh 610FFFh 1551 1536 60F000h 600000h 60FFFFh 600FFFh

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Block 1535 1520 5FF000h 5F0000h 5FFFFFh 5F0FFFh Sector Address Range 1519 1504 5EF000h 5E0000h 5EFFFFh 5E0FFFh 1503 1488 5DF000h 5D0000h 5DFFFFh 5D0FFFh 1487 1472 5CF000h 5C0000h 5CFFFFh 5C0FFFh 1471 1456 5BF000h 5B0000h 5BFFFFh 5B0FFFh 1455 1440 5AF000h 5A0000h 5AFFFFh 5A0FFFh 1439 1424 59F000h 590000h 59FFFFh 590FFFh 1423 1408 58F000h 580000h 58FFFFh 580FFFh 1407 1392 57F000h 570000h 57FFFFh 570FFFh 1391 1376 56F000h 560000h 56FFFFh 560FFFh 1375 1360 55F000h 550000h 55FFFFh 550FFFh 1359 1344 54F000h 540000h 54FFFFh 540FFFh 1343 1328 53F000h 530000h 53FFFFh 530FFFh 1327 1312 52F000h 520000h 52FFFFh 520FFFh 1311 1296 51F000h 510000h 51FFFFh 510FFFh 1295 1280 50F000h 500000h 50FFFFh 500FFFh Block 1279 1264 4FF000h 4F0000h 4FFFFFh 4F0FFFh Sector Address Range 1263 1248 4EF000h 4E0000h 4EFFFFh 4E0FFFh 1247 1232 4DF000h 4D0000h 4DFFFFh 4D0FFFh 1231 1216 4CF000h 4C0000h 4CFFFFh 4C0FFFh 1215 1200 4BF000h 4B0000h 4BFFFFh 4B0FFFh 1119 1184 4AF000h 4A0000h 4AFFFFh 4A0FFFh 1183 1168 49F000h 490000h 49FFFFh 490FFFh 1167 1152 48F000h 480000h 48FFFFh 480FFFh 1151 1136 47F000h 470000h 47FFFFh 470FFFh 1135 1120 46F000h 460000h 46FFFFh 460FFFh 1119 1104 45F000h 450000h 45FFFFh 450FFFh 1103 1088 44F000h 440000h 44FFFFh 440FFFh 1087 1072 43F000h 430000h 43FFFFh 430FFFh 1071 1056 42F000h 420000h 42FFFFh 420FFFh 1055 1040 41F000h 410000h 41FFFFh 410FFFh 1039 1024 40F000h 400000h 40FFFFh 400FFFh

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Block 1023 1008 3FF000h 3F0000h 3FFFFFh 3F0FFFh Sector Address Range 1007 992 3EF000h 3E0000h 3EFFFFh 3E0FFFh 991 976 3DF000h 3D0000h 3DFFFFh 3D0FFFh 975 960 3CF000h 3C0000h 3CFFFFh 3C0FFFh 959 944 3BF000h 3B0000h 3BFFFFh 3B0FFFh 943 928 3AF000h 3A0000h 3AFFFFh 3A0FFFh 927 912 39F000h 390000h 39FFFFh 390FFFh 911 896 38F000h 380000h 38FFFFh 380FFFh 895 880 37F000h 370000h 37FFFFh 370FFFh 879 864 36F000h 360000h 36FFFFh 360FFFh 863 848 35F000h 350000h 35FFFFh 350FFFh 847 832 34F000h 340000h 34FFFFh 340FFFh 831 816 33F000h 330000h 33FFFFh 330FFFh 815 800 32F000h 320000h 32FFFFh 320FFFh 799 784 31F000h 310000h 31FFFFh 310FFFh 783 768 30F000h 300000h 30FFFFh 300FFFh Block 767 752 2FF000h 2F0000h 2FFFFFh 2F0FFFh Sector Address Range 751 736 2EF000h 2E0000h 2EFFFFh 2E0FFFh 735 720 2DF000h 2D0000h 2DFFFFh 2D0FFFh 719 704 2CF000h 2C0000h 2CFFFFh 2C0FFFh 703 688 2BF000h 2B0000h 2BFFFFh 2B0FFFh 687 672 2AF000h 2A0000h 2AFFFFh 2A0FFFh 671 656 29F000h 290000h 29FFFFh 290FFFh 655 640 28F000h 280000h 28FFFFh 280FFFh 639 624 27F000h 270000h 27FFFFh 270FFFh 623 608 26F000h 260000h 26FFFFh 260FFFh 607 592 25F000h 250000h 25FFFFh 250FFFh 591 576 24F000h 240000h 24FFFFh 240FFFh 575 560 23F000h 230000h 23FFFFh 230FFFh 559 544 22F000h 220000h 22FFFFh 220FFFh 543 528 21F000h 210000h 21FFFFh 210FFFh 527 512 20F000h 200000h 20FFFFh 200FFFh

Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next
Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of Serial mode 0 and mode 3 is shown as Figure 3. Figure 3. Serial Modes Supported

For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, RES, REMS and REMS2 the
During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and

not affect the current operation of Write Status Register, Program, Erase.

P/N: PM1290 REV. 1.4, OCT. 01, 2008 COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 12) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure 13) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion - Continuously program mode (CP) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> to end RDID operation can use CS# to high at any time during data out. (see Figure. 14) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

P/N: PM1290 REV. 1.4, OCT. 01, 2008 (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out on SO (see Figure. 15) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/ ACC) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/ACC pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) Continuously program mode (CP mode) BP3 (level of protected block) BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1= status register write disable 0 = normal program mode 1 = CP mode(default 0) (note1) (note1) (note1) (note1) 1= write enable 0= not write enable 1= write operation 0= not in write operation Non- volatile bit volatile bit Non- volatile bit Non- volatile bit Non- volatile bit Non- volatile bit volatile bit volatile bit note1: see the table "Protected Area Sizes"

The WRSR instruction has no effect on b6, b1, b0 of the status register. and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 6. Protection Modes

As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Note: If SRWD bit=1 but WP#/ACC is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/ACC is low (or WP#/ACC is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/ACC to against data modification. Note: to exit the hardware protected mode requires WP#/ACC driving high once the hardware protected mode is entered. If the WP#/ACC pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI -> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 17) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 18) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/ data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 8-bit dummy interleave on SIO1 & SIO0 → data out interleave on SIO1 & SIO0 → to end 2READ operation can use CS# to high at any time during data out (see Figure of 2 x I/O Read Mode Timing Waveform)

P/N: PM1290 REV. 1.4, OCT. 01, 2008 While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. throughputs. (9) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 22) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (10) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K- byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (11) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure 24)

P/N: PM1290 REV. 1.4, OCT. 01, 2008 The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". (12) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 20) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (13) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), RDPR command (A1 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# high to low-> sending CP instruction code-> 3-byte address on SI-> Data (WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see Figure of CP mode timing waveform) Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.

P/N: PM1290 REV. 1.4, OCT. 01, 2008 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode. (14) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/ Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure 25) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (15) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power- down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 26,27. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power- down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode.

Table 7. ID Definitions both the JEDEC assigned manufacturer ID and the specific device ID. instruction is completed by driving CS# high. data cannot be updated again once it is lock-down. OTP is lock down, only read related commands are valid. The EXSO instruction is for exiting the additional 512-bit secured OTP mode.

time (even in program/erase/write status register/write security register condition) and continuously. Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. be update any more. While it is in 512-bit secured OTP mode, array access is not allowed. Table 8. Security Register Definition area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

P/N: PM1290 REV. 1.4, OCT. 01, 2008 POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device is fully accessible for commands like write enable(WREN), page program (PP), Continuously Program (CP), sector erase(SE), chip erase(CE), WRSCUR and write status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tPUW after VCC reached VWI level - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW has not passed. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

P/N: PM1290 REV. 1.4, OCT. 01, 2008 NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 4, 5. RATING VALUE Ambient Operating Temperature -40 ° C to 85° C for Industrial grade Storage Temperature -55 ° C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V ABSOLUTE MAXIMUM RATINGS ELECTRICAL SPECIFICATIONS CAPACITANCE TA = 25°°°°° C, f = 1.0 MHz SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS CIN Input Capacitance 6 pF VIN = 0V COUT Output Capacitance 8 pF VOUT = 0V Figure 4.Maximum Negative Overshoot Waveform Figure 5. Maximum Positive Overshoot Waveform Vss Vss - 2.0V 20ns 20ns 20ns Vcc + 2.0V Vcc 20ns 20ns 20ns

Table 9. DC CHARACTERISTICS

Table 10. AC CHARACTERISTICS

P/N: PM1290 REV. 1.4, OCT. 01, 2008 Symbol Alt. Parameter Min. Typ. Max. Unit tW Write Status Register Cycle Time 40 100 ms tBP Byte-Program 9 300 us tPP Page Program Cycle Time 1.4 5 ms tSE Sector Erase Cycle Time 60 300 ms tBE Block Erase Cycle Time 0.7 2 s tCE Chip Erase Cycle Time 64Mb 50 80 s 32Mb 25 50 s 16Mb 14 30 s Notes: 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 6.

contains 00h (all Status Register bits are 0). Note: 1. These parameters are characterized only. Table 11. Power-Up Timing and VWI Threshold

Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

24 BIT ADDRESS

Figure 22. Sector Erase (SE) Sequence (Command 20) Figure 23. Block Erase (BE) Sequence (Command D8) Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) (05 hex), RDPR command (A1 hex), and RDSCUR command (2B hex). high will return the SO pin to tri-state. Note: SE command is 20(hex). Note: BE command is D8(hex).

Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) Figure 25. Deep Power-down (DP) Sequence (Command B9) Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence Note: CE command is 60(hex) or C7(hex).

3 Dummy Bytes

(2) Instruction is either 90(hex) or EF(hex). Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF)

2 Dummy Bytes

Figure 29. Power-up Timing

P/N: PM1290 REV. 1.4, OCT. 01, 2008 RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Figure A. AC Timing at Device Power-Up Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. Symbol Parameter Notes Min. Max. Unit tVR VCC Rise Time 1 20 500000 us/V SCLK SI CS# VCC MSB IN SO tDVCH High Impedance LSB IN tSLCH tCHDX tCHCL tCLCH tSHCH tSHSL tCHSHtCHSL tVR VCC(min) GND

P/N: PM1290 REV. 1.4, OCT. 01, 2008 ERASE AND PROGRAMMING PERFORMANCE PARAMETER Min. TYP. (1) Max. (2) UNIT Write Status Register Cycle Time 40 100 ms Sector Erase Time 60 300 ms Block Erase Time 0.7 2 s 64Mb 50 80 s Chip Erase Time 32Mb 25 50 s 16Mb 14 30 s 64Mb 30 48 s Chip Erase Time (at ACC mode) 32Mb 15 30 s 16Mb 8 18 s Byte Program Time (via page program command) 9 300 us Page Program Time 1.4 5 ms Page Program Time (at ACC mode) 1.4 5 ms Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25° C, 3.3V, and checker board pattern. 2. Under worst conditions of 85° C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard. MIN. MAX. Input Voltage with respect to GND on ACC -1.0V 10.5V Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. LATCH-UP CHARACTERISTICS

P/N: PM1290 REV. 1.4, OCT. 01, 2008

ORDERING INFORMATION

PART NO. CLOCK OPERATING STANDBY Temperature PACKAGE Remark (MHz) CURRENT MAX. CURRENT MAX. (mA) (uA) MX25L1605DM2I-12G 86 25 20 -40 °C~85°C 8-SOP Pb-free (200mil) MX25L1605DMI-12G 86 25 20 -40 °C~85°C 16-SOP Pb-free MX25L1605DM1I-12G 86 25 20 -40 °C~85°C 8-SOP Pb-free (150mil) MX25L1605DPI-12G 86 25 20 -40 °C~85°C 8-PDIP Pb-free (300mil) MX25L1605DZNI-12G 86 25 20 -40 °C~85°C 8-WSON Pb-free (6x5mm) MX25L1605DZUI-12G 86 25 20 -40 °C~85°C 8-USON Pb-free (4x4mm) MX25L3205DZNI-12G 86 25 20 -40 °C~85°C 8-WSON Pb-free (6x5mm) MX25L3205DM2I-12G 86 25 20 -40 °C~85°C 8-SOP Pb-free (200mil) MX25L3205DMI-12G 86 25 20 -40 °C~85°C 16-SOP Pb-free MX25L3205DPI-12G 86 25 20 -40 °C~85°C 8-PDIP Pb-free (300mil) MX25L3205DZUI-12G 86 25 20 -40 °C~85°C 8-USON Pb-free (4x4mm) MX25L6405DZNI-12G 86 25 20 -40 °C~85°C 8-WSON Pb-free (8x6mm) MX25L6405DMI-12G 86 25 20 -40 °C~85°C 16-SOP Pb-free

P/N: PM1290 REV. 1.4, OCT. 01, 2008 PART NAME DESCRIPTION MX 25 L 12ZN I G OPTION: G: Pb-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40˚C to 85˚C) PACKAGE: ZN: WSON (0.8mm package height) ZU: USON (0.6mm package height) M: 300mil 16-SOP M1: 150mil 8-SOP M2: 200mil 8-SOP P: 300mil 8-PDIP DENSITY & MODE: 1605D: 16Mb 3205D: 32Mb 6405D: 64Mb TYPE: L: 3V DEVICE: 25: Serial Flash 1605D

P/N: PM1290 REV. 1.4, OCT. 01, 2008

PACKAGE INFORMATION

P/N: PM1290 REV. 1.4, OCT. 01, 2008

REVISION HISTORY

Revision No. Description Page Date 1.0 1. Removed "Preliminary" P1 MAR/07/2008 1.1 1. Dual I/O Pre-released P1,3,21,31 MAY/12/2008 1.2 1. Added 8-land USON package information P2,4,46,47,50JUL/08/2008 1.3 1. Modified figure 4 & 5 waveform P28 AUG/15/2008 9.5V(min.)~10.5V(max.) 1.4 1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.) P32,45 OCT/01/2008 2. Removed "Advanced Information" for MX25L3205DZUI-12G P46

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Product Information

25L1605 specifications and overview.

Summary

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Description

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Source title 25L1605 Datasheet(PDF) - Macronix International

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