25C320I/ST14

25AA320 MICROCHIP | Alldatasheet

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Technical content

 2004 Microchip Technology Inc. DS21227E-page 1 25AA320/25LC320/25C320 Device Selection Table Features:

• Low-power CMOS technology: - Write current: 3 mA maximum - Read current: 500µA typical - Standby current: 500 nA typical  4096 x 8 bit organization  32 byte page  Write cycle time: 5 ms maximum  Self-timed erase and write cycles  Block write protection: - Protect none, 1/4, 1/2 or all of array  Built-in write protection: - Power on/off data protection circuitry - Write enable latch - Write-protect pin  Sequential read  High reliability: - Endurance: 1M E/W cycles - Data retention: > 200 years - ESD protection: > 4000V  8-pin PDIP , SOIC and TSSOP packages  14-lead TSSOP package  Temperature ranges supported: Description: The Microchip Technology Inc. 25AA320/25LC320/ 25C320 (25XX320 *) are 32 Kbit serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS ) input. Communication to the device can be paused via the hold pin (HOLD ). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. Block Diagram Package Types Part Number VCC Range Max. Clock Frequency Temp. Ranges 25AA320 1.8-5.5V 1 MHz I 25LC320 2.5-5.5V 2 MHz I,E 25C320 4.5-5.5V 3 MHz I,E - Industrial (I): -40°Ct o + 8 5°C - Automotive (E): -40°C to +125°C SI SO SCK CS HOLD WP Status Register I/O Control Memory Control Logic HV Generator EEPROM Array Page Y Decoder Sense Amp. R/W Control Logic VCC VSS Latches XDEC TSSOPPDIP, SOIC TSSOP CS SO WP VSS VCC HOLD SCK SI 25XX320 HOLD VCC CS SO SCK SI VSS WP 25XX320 NC CS SO NC WP VSS NC NC VCC HOLD NC SCK SI NC 25XX320 51 0 32K SPI™ Bus Serial EEPROM *25XX320 is used in this document as a generic part number for the 25AA320/25LC320/25C320 devices.

DS21227E-page 2  2004 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†) TABLE 1-1: DC CHARACTERISTICS † NOTICE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E):TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. No. Sym. Characteristics Min. Max. Units Conditions D1 V IH1 High-level input voltage 2.0 V CC +1 V V CC ≥ 2.7V (Note) D2 V IH2 0.7 VCC VCC +1 V V CC < 2.7V (Note) D3 V IL1 Low-level input voltage -0.3 0.8 V V CC ≥ 2.7V (Note) D4 V IL2 -0.3 0.3 V CC VV CC < 2.7V (Note) D5 V OL Low-level output voltage —0 . 2 V I OL = 1.0 mA, VCC < 2.5V D6 V OH High-level output voltage VCC -0.5 — V I OH = -400µA D7 I LI Input leakage current — ±1 µAC S = VCC , VIN = VSS TO VCC D8 I LO Output leakage current —± 1 µAC S = VCC , VOUT = VSS TO VCC D9 C INT Internal Capacitance (all inputs and outputs) —7 p F T A = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) D10 I CC Read Operating Current — 500 mA µA VCC = 5.5V; FCLK = 3.0 MHz; SO = Open V CC = 2.5V; FCLK = 2.0 MHz; SO = Open D11 I CC Write — mA mA VCC = 5.5V VCC = 2.5V D12 I CCS Standby Current — µA µA CS = VCC = 5.5V, Inputs tied to VCC or VSS CS = VCC = 2.5V, Inputs tied to VCC or VSS Note: This parameter is periodically sampled and not 100% tested.

 2004 Microchip Technology Inc. DS21227E-page 3 25AA320/25LC320/25C320 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C V CC = 1.8V to 5.5V Automotive (E): TA = -40°C to +125°C V CC = 2.5V to 5.5V Param. No. Sym. Characteristic Min. Max. Units Conditions 1F CLK Clock Frequency — MHz MHz MHz V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 2T CSS CS Setup Time 100 250 500 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 3T CSH CS Hold Time 150 250 475 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 4T CSD CS Disable Time 500 — ns — 5T SU Data Setup Time 30 ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 6T HD Data Hold Time 50 100 100 ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 7T R CLK Rise Time — 2 µs (Note 1) 8T F CLK Fall Time — 2 µs (Note 1) 9T HI Clock High Time 150 230 475 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V

10 T LO Clock Low Time 150

V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V

11 T CLD Clock Delay Time 50 — ns —

12 T CLE Clock Enable Time 50 — ns —

13 T V Output Valid from

VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V

14 T HO Output Hold Time 0 — ns (Note 1)

15 T DIS Output Disable Time —

V CC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 5.5V (Note 1) VCC = 1.8V to 5.5V

16 T HS HOLD Setup Time 100

V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V

17 T HH HOLD Hold Time 100

V CC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V

18 T HZ HOLD Low to Output

V CC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 5.5V (Note 1) VCC = 1.8V to 5.5V

19 T HV HOLD High to Output

VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V

20 T WC Internal Write Cycle

—5 m s — 21 — Endurance 1M — E/W Cycles (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.

 2004 Microchip Technology Inc. DS21227E-page 5 25AA320/25LC320/25C320 TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) Timing Measurement Reference Level Input 0.5 V CC Output 0.5 V CC Note 1: For VCC ≤ 4.0V 2: For VCC > 4.0V VCC SO 100 pF1.8 KΩ 2.25 KΩ

DS21227E-page 6  2004 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE

2.1 Chip Select (CS )

A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power- up, a low level on CS is required prior to any sequence being initiated.

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX320. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.

2.3 Write-Protect (WP )

This pin is used in conjunction with the WPEN bit in the Status register to prohibit writes to the nonvolatile bits in the Status register. When WP is low and WPEN is high, writing to the nonvolatile bits in the Status register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the Status register operate normally. If the WPEN bit is set, WP low during a Status register write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the Status register is low. This allows the user to install the 25XX320 in a system with WP pin grounded and still be able to write to the Status register. The WP pin functions will be enabled when the WPEN bit is set high.

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication between a master and the 25XX320. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD )

The HOLD pin is used to suspend transmission to the 25XX320 while in the middle of a serial sequence with- out having to re-transmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to- low transition. The 25XX320 must remain selected dur- ing this sequence. The SI, SCK, and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. Name PDIP SOIC 8-pin TSSOP 14-lead TSSOP Description CS 1 1 3 1 Chip Select Input SO 2 2 4 2 Serial Data Output NC — — — 3,4,5 Not Connected WP 3 3 5 6 Write-Protect Pin Vss 4 4 6 7 Ground SI 5 5 7 8 Serial Data Input SCK 6 6 8 9 Serial Clock Input NC — — — 10,11,12 Not Connected HOLD 7 7 1 13 Hold Input Vcc 8 8 2 14 Supply Voltage

 2004 Microchip Technology Inc. DS21227E-page 7 25AA320/25LC320/25C320

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles Of Operation

The 25XX320 are 4096 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25XX320 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX320 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.

3.2 Read Sequence

The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX320 fol- lowed by the 16-bit address, with the four MSBs of the address being don’t care bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to pro- vide clock pulses. The internal address pointer is auto- matically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (0FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1).

3.3 Write Sequence

Prior to any attempt to write data to the 25XX320, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX320. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the four MSBs of the address being don’t care bits, and then the data to be written. Up to 32 bytes of data can be sent to the 25XX320 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with xxxx xxxx xxx0 0000 and ends with xxxx xxxx xxx1 1111. If the internal address counter reaches xxxx xxxx xxx1 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the least significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP , WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. TABLE 3-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011Read data from memory array beginning at selected address WRITE 0000 0010Write data to memory array beginning at selected address WRDI 0000 0100Reset the write enable latch (disable write operations) WREN 0000 0110Set the write enable latch (enable write operations) RDSR 0000 0101Read Status register WRSR 0000 0001Write Status register

 2004 Microchip Technology Inc. DS21227E-page 9 25AA320/25LC320/25C320

3.4 Write Enable (WREN) and Write

Disable (WRDI) The 25XX320 contains a write enable latch. See Table 3-3 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. The following is a list of conditions under which the write enable latch will be reset:  Power-up  WRDI instruction successfully executed  WRSR instruction successfully executed  WRITE instruction successfully executed FIGURE 3-4: WRITE ENABLE SEQUENCE FIGURE 3-5: WRITE DISABLE SEQUENCE SCK 0 2345671 SI High-impedance SO CS 01 0000 0 1 SCK 0 2345671 SI High-impedance SO CS 010000 0 10

DS21227E-page 10  2004 Microchip Technology Inc.

3.5 Read Status Register Instruction

(RDSR) The Read Status Register instruction (RDSR) provides access to the Status register. The Status register may be read at any time, even during a write cycle. The Status register is formatted as follows: The Write-In-Process (WIP) bit indicates whether the 25XX320 is busy with a write operation. When set to a 1’, a write is in progress; when set to a ‘0’, no write is in progress. This bit is read-only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the Status register. This bit is read-only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile. See Figure 3-6 for the RDSR timing sequence. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE 76 5 4 3 2 1 0 WPEN X X X BP1 BP0 WEL WIP SO SI CS 91 01 1 1 21 31 41 5 11000000 765 4 2 1 0 instruction data from Status registerHigh-impedance SCK 0 2345671 8

 2004 Microchip Technology Inc. DS21227E-page 11 25AA320/25LC320/25C320

3.6 Write Status Register Instruction

(WRSR) The Write Status Register instruction (WRSR) allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the Status register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as shown in Table 3-2. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the Status register control the program- mable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the Status register are disabled. See Table 3-3 for a matrix of functionality on the WPEN bit. See Figure 3-7 for the WRSR timing sequence. TABLE 3-2: ARRAY PROTECTION FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE BP1 BP0 Array Addresses Write-Protected 00 none 01 upper 1/4 (0C00h - 0FFFh) 10 upper 1/2 (0800h - 0FFFh) 11 all (0000h - 0FFFh) SO SI CS 91 01 1 1 21 31 41 5 01000000 765 4 21 0 instruction data to Status register High-impedance SCK 0 2345671 8

DS21227E-page 12  2004 Microchip Technology Inc.

3.7 Data Protection

The following protection has been implemented to prevent inadvertent writes to the array:  The write enable latch is reset on power-up A WRITE ENABLE instruction must be issued to set the write enable latch  After a byte write, page write or Status register write, the write enable latch is reset C S must be set high after the proper number of clock cycles to start an internal write cycle  Access to the array during an internal write cycle is ignored and programming is continued

3.8 Power-On State

The 25XX320 powers on in the following state:  The device is in low-power Standby mode (CS = 1)  The write enable latch is reset  SO is in high-impedance state  A low level on CS is required to enter active state TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX WPEN WP WEL Protected Blocks Unprotected Blocks Status Register xx0 Protected Protected Protected 0x1 Protected Writable Writable

1 Low 1 Protected Writable Protected

x High 1 Protected Writable Writable

 2004 Microchip Technology Inc. DS21227E-page 13 25AA320/25LC320/25C320

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

8-Lead PDIP (300 mil) Example: 14-Lead TSSOP Example: 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN XXXXXXXX NNN 25LC320 /PNNN YYWW 25LC320 I/SNYYWW NNN 25L32 YYWW NNN 8-Lead TSSOP Example: XXXX XYWW NNN 5LBX IYWW NNN YYWW Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, and traceability code. For device markings beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

DS21227E-page 14  2004 Microchip Technology Inc. 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) B A L p α E eB β c n D Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 88 Pitch p .100 2.54 Base to Seating Plane A1 .015 0.38 Mold Draft Angle Top α 51 01 5 51 01 5 Mold Draft Angle Bottom β 51 01 5 51 01 5 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed JEDEC Equivalent: MS-001 Drawing No. C04-018 .010” (0.254mm) per side. § Significant Characteristic

 2004 Microchip Technology Inc. DS21227E-page 15 25AA320/25LC320/25C320 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Foot Angle φ 048048 1512015120βMold Draft Angle Bottom 1512015120αMold Draft Angle Top 1.27.050pPitch 88nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D n p B E h Lβ c 45° φ α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 § Significant Characteristic

DS21227E-page 16  2004 Microchip Technology Inc. 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) 10501050βMold Draft Angle Bottom 10501050αMold Draft Angle Top 1.10.043AOverall Height 0.65.026pPitch 88nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits α A L c β φ D n p B E Foot Angle φ 048048 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 § Significant Characteristic

 2004 Microchip Technology Inc. DS21227E-page 17 25AA320/25LC320/25C320 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) 840840φFoot Angle 10501050βMold Draft Angle Bottom 10501050αMold Draft Angle Top 1.10.043AOverall Height 0.65.026pPitch 1414nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits Lβ c φ D n B p E α A2A1 A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 § Significant Characteristic

DS21227E-page 18  2004 Microchip Technology Inc. APPENDIX A: REVISION HISTORY Revision D Corrections to Section 1.0, Electrical Characteristics. Revision E Revise Endurance from 100K to 1M.

 2004 Microchip Technology Inc. DS21227E-page 19 25AA320/25LC320/25C320 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape ® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is:  Latest Microchip Press Releases  Technical Support Section with Frequently Asked Questions  Design Tips  Device Errata  Job Postings  Microchip Consultant Program Member Listing  Links to other useful web sites related to Microchip Products  Conferences for products, Development Systems, technical information and more  Listing of seminars and events SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003

DS21227E-page 20  2004 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS21227E25AA320/25LC320/25C320 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document?

 2004 Microchip Technology Inc. DS21227E-page 21 25AA320/25LC320/25C320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. PART NO. X /XX PackageTemperature Range Device Examples: a) 25LC320-I/SN: Industrial Temp., SOIC package b) 25LC320T-I/SN: Tape and Reel, Industrial Temp., SOIC package c) 25LC320-E/SN: Extended Temp., SOIC package d) 25C320-I/SN: Industrial Temp., SOIC package e) 25C320T-I/SN: Tape and Reel, Industrial Temp., SOIC package f) 25C320-I/ST: Industrial Temp., TSSOP package g) 25C320-E/SN: Extended Temp., SOIC package Device: 25AA320: 32 Kbit 1.8V SPI Serial EEPROM 25AA320T: 32 Kbit 1.8V SPI Serial EEPROM (Tape and Reel) 25AA320X 32-bit 1.8V SPI Serial EEPROM in alternate pinout (ST only) 25AA320XT 32-bit 1.8V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25LC320: 32 Kbit 2.5V SPI Serial EEPROM 25LC320T: 32 Kbit 2.5V SPI Serial EEPROM (Tape and Reel) 25LC320X 32-bit 2.5V SPI Serial EEPROM in alternate pinout (ST only) 25LC320XT 32-bit 2.5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25C320: 32 Kbit 5V SPI Serial EEPROM 25C320T: 32 Kbit 5V SPI Serial EEPROM (Tape and Reel) 25C320X 32-bit 5V SPI Serial EEPROM in alternate pinout (ST only) 25C320XT 32-bit 5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) Temperature Range: I= - 4 0 °C to +85°C E= - 4 0 °C to +125°C Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (150 mil body), 8-lead ST = Plastic TSSOP (4.4 mm body), 8-lead ST14 = Plastic TSSOP (4.4 mm body), 14-lead

DS21227E-page 22  2004 Microchip Technology Inc. NOTES:

 2004 Microchip Technology Inc. DS21227E-page 23 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEE LOQ , microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:  Microchip products meet the specification contained in their particular Microchip Data Sheet.  Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.  There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  Microchip is willing to work with the customer who is concerned about the integrity of their code.  Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEE LOQ ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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