HA-2520_06 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

  • Gain Bandwidth (A
  • Compensation Pin for Unity Gain Capability
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Data Acquisition Systems
  • R F A m p l i f i e r s
  • Video Amplifiers
  • Signal Generators Pinouts HA-2520, HA-2525 (8 LD CERDIP, 8 LD PDIP, CERDIP , SOIC) TOP VIEW HA-2520, HA-2522, HA-2525 (8 LD METAL CAN) TOP VIEW

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. HA2-2520-2 HA2-2520-2 -55 to +125 8 Ld Metal Can T8.C HA7-2520-2 HA7-2520-2 -55 to +125 8 Ld CerDIP F8.3A HA2-2522-2 HA2-2522-2 -55 to +125 8 Ld Metal Can T8.C HA2-2525-5 HA2-2525-5 0 to +75 8 Ld Metal Can T8.C HA3-2525-5 HA3-2525-5 0 to +75 8 Ld PDIP E8.3 HA3-2525-5Z (Note) HA3-2525-5Z 0 to +75 8 Ld PDIP* (Pb-free) E8.3 HA7-2525-5 HA7-2525-5 0 to +75 8 Ld CerDIP F8.3A HA9P2525-5 25255 0 to +75 8 Ld SOIC M8.15 HA9P2525-5Z (Note) 2525-5Z 0 to +75 8 Ld SOIC (Pb-free) M8.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. BAL -IN +IN COMP OUT BAL COMP OUTIN- BAL IN+ BAL Data Sheet November 15, 2006 FN2894.8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2894.8 November 15, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15V PARAMETER TEMP (°C) HA-2520-2 HA-2522-2 HA-2525-5 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX INPUT CHARACTERISTICS Offset Voltage 25 - 4 8 - 5 10 - 5 10 mV Full - - 11 - - 14 - - 14 mV Offset Voltage Drift Full - 20 - - 25 - - 30 - mV/ °C Bias Current 25 - 100 200 - 125 250 - 125 250 nA Full - - 400 - - 500 - - 500 nA Offset Current 25 - 10 25 - 20 50 - 20 50 nA Full - - 50 - - 100 - - 100 nA Input Resistance (Note 2) 25 50 100 - 40 100 - 40 100 - MW Common Mode Range Full ±10.0 - - ±10.0 - - ±10.0 - - V TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Notes 3, 6) 25 10 15 - 7.5 15 - 7.5 15 - kV/V Common Mode Rejection Ratio (Note 4) Full 80 90 - 74 90 - 74 90 - dB Gain Bandwidth (Notes 2, 5) 25 10 20 - 10 20 - 10 20 - MHz Minimum Stable Gain 25 3 - - 3 - - 3 - - V/V OUTPUT CHARACTERISTICS Output Current (Note 6) 25 ±10 ±20 - ±10 ±20 - ±10 ±20 - mA Full Power Bandwidth (Notes 6, 11) TRANSIENT RESPONSE (A V = +3) Rise Time (Notes 3, 7, 8, 10) 25 - 25 50 - 25 50 - 25 50 ns Overshoot (Notes 3, 7, 8, 10) 25 - 25 40 - 25 50 - 25 50 % Slew Rate (Notes 3, 7, 10, 12) 25 ±100 ±120 - ±80 ±120 - ±80 ±120 - V/ μs Settling Time (Notes 3, 7, 10, 12) 25 - 0.20 - - 0.20 - - 0.20 - μs HA-2520, HA-2522, HA-2525

NOTE: Tested offset adjustment range is |VOS + 1mV| minimum referred to output. Typical ranges are ±20mV with RT = 20kΩ. FIGURE 5. SUGGESTED V OS ADJUSTMENT AND COMPENSATION HOOK-UP

FIGURE 12. OUTPUT CURRENT vs SUPPLY VOLTAGE FIG URE 13. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 15. FREQUENCY RESPONSE FIGURE 16. OPEN LOOP FREQUENCY RESPONSE FOR FIGURE 17. INPUT NOISE CHARACTERISTICS

100 GAIN (dB)

FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY F IGURE 19. NORMALIZED AC PARAMETERS vs SUPPLY

8 FN2894.8 November 15, 2006 Metal Can Packages (Can) NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. a is the basic spacing from the centerline of the tab to terminal 1 and b is the basic spacing of eac h lead or lead position (N -1 places) from a, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. Øb ØD2 Øe k1 k βØb1 BASE AND SEATING PLANE F Q ØD ØD1 REFERENCE PLANE L A α Øb2Øb1 BASE METAL LEAD FINISH SECTION A-A A A N CL T8.C MIL-STD-1835 MACY1-X8 (A1)

8 LEAD METAL CAN PACKAGE

A 0.165 0.185 4.19 4.70 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 - 0.050 - 1.27 1 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - a 45° BSC 45° BSC 3 b 45° BSC 45° BSC 3 N8 8 4 Rev. 0 5/18/94 HA-2520, HA-2522, HA-2525

9 FN2894.8 November 15, 2006 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)

8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90° 105° 90° 105° - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N8 8 8 Rev. 0 4/94 HA-2520, HA-2522, HA-2525

10 FN2894.8 November 15, 2006 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93 HA-2520, HA-2522, HA-2525

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2894.8 November 15, 2006 HA-2520, HA-2522, HA-2525 Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05