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Technical content

Features

  • 8-pin SOIC package
  • Four addressable registers
  • Input crystal frequency of 5 to 27 MHz
  • Clock input frequency of 3 to 150 MHz
  • Output clock frequencies up to 200 MHz
  • Configurable Spread Spectrum Modulation
  • Operating voltage of 3.3 V
  • Replaces multiple crystals and oscillators
  • Controllable output drive levels
  • Advanced, low-power CMOS process
  • Available in RoHS compliant packaging Block Diagram Crystal Oscillator PLL Clock Synthesis, Spread Spectrum and Control Circuitry CLK PDTS (output and PLL) OTP ROM with PLL Divider Values S1:0 VDD GND Crystal or clock input External capacitors are required with a crystal input. X1/ICLK

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2 REVISION E 05/19/14 ICS251 DATASHEET Pin Assignment 8-pin (150 mil) SOIC Output Clock Selection Table Pin Descriptions External Components The ICS251 requires a minimum number of external components for proper operation. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS251 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (C L -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. X1/ICLK VDD GND CLKX2 PDTS S1 S0 CLK (MHz) Spread Percentage 0 0 User Configurable User Configurable

01 User

10 User

11 User

1 S0 Input Select pin 0 for frequency selection on CLK. Internal pull-up resistor. 2 VDD Power Connect to +3.3 V. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. 4 X2 XO Connect this pin to a crystal, or float for clock input. 5 CLK Output Clock output. Weak internal pull-down when tri-state. 6 S1 Input Select pin 1 for frequency selection on CLK. Internal pull-up resistor. 7 GND Power Connect this to Ground. 8P D T S Input Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up resistor. The pin must be tied either directly or through the external resistor to VDD or GND. External resistor value must be less than 15kOhm.

REVISION E 05/19/14 3 FIELD PR OGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS251 DATASHEET PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS251. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. ICS251 Configuration Capabilities The architecture of the ICS251 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS251 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: Output Drive Control The ICS251 has two output drive settings. Low drive should be selected when outputs are less than 100 MHz. High drive should be selected when outputs are greater than 100 MHz. (Consult the AC Electrical Characteristics for output rise and fall times for each drive option.) IDT VersaClock Software IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. Spread Spectrum Modulation The ICS251 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system’s electro-magnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. Spread Spectrum Modulation can be applied as either “center spread” or “down spread”. During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The ICS251 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between +/- 0.125% to +/-2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of “down-circuit” PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. OutputFreq REFFreq N-----=

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 4 REVISION E 05/19/14 ICS251 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS251. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Parameter Condition Min. Typ. Max. Units Supply Voltage, VDD Referenced to GND -0.5 4.6 V Inputs Referenced to GND -0.5 VDD+ 0.5 V Clock Outputs Referenced to GND -0.5 VDD+ 0.5 V Storage Temperature -65 150 C Soldering Temperature Max 10 seconds 260 C Junction Temperature 125 C Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS251M) 0 +70 C Ambient Operating Temperature (ICS251MI) -40 +85 C Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V Power Supply Ramp Time 4 ms

REVISION E 05/19/14 5 FIELD PR OGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS251 DATASHEET Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85C Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 3.3 3.45 V Operating Supply Current Input High Voltage IDD Configuration Dependent - See VersaClockTM mA

33.3333 MHz output, PDTS

= 1, no load Note 1 14 mA PDTS = 0 500 A Input High Voltage V IH S1:S0 VDD/2+1 V Input Low Voltage V IL S1:S0 0.4 V Input High Voltage, PDTS VIH VDD-0.5 V Input Low Voltage, PDTS VIL 0.4 V Input High Voltage V IH ICLK VDD/2+1 V Input Low Voltage V IL ICLK VDD/2-1 V Output High Voltage (CMOS High) VOH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -8 mA (Low Drive); IOH = -12 mA (High Drive) 2.4 VDD-0.4 V Output Low Voltage V OL IOL = 8 mA (Low Drive); IOL = 12 mA (High Drive) 0.4 V Short Circuit Current I OS ±70 mA Nominal Output Impedance Z O 20  Internal pull-up resistor R PUP S1:S0, PDTS 190 k  Internal pull-down resistor R PD CLK output 120 k  Input Capacitance C IN inputs 4 pF

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6 REVISION E 05/19/14 ICS251 DATASHEET Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85C Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency F IN Fundamental Crystal 5 27 MHz Input Clock 3 150 MHz Output Frequency 0.314 200 MHz Output Rise Time t OR 20% to 80%, Note 1 1 ns Output Fall Time t OF 80% to 20%, Note 1 1 ns Duty Cycle Note 2 40 49-51 60 % Power-up time PLL lock time from power-up 41 0 m s PDTS goes high until stable CLK output, Spread Spectrum Off .6 2 ms PDTS goes high until stable CLK output, Spread Spectrum On 47 m s PDTS goes high until spread spectrum is stable, Spread Spectrum On 10 50 ms One Sigma Clock Period Jitter Configuration Dependent 50 ps Maximum Absolute Jitter t ja Deviation from Mean. Configuration Dependent +200 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W Thermal Resistance Junction to Case JC 40 C/W

REVISION E 05/19/14 7 FIELD PR OGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS251 DATASHEET Marking Diagram Marking Diagram (Pb free) Notes: 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “I” denotes industrial temp. range (if applicable). 4. “L” denotes RoHS compliant package. 5. Bottom marking: country of origin. 251PM YYWW 251PMI YYWW 251PML YYWW 251PMIL YYWW

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 8 REVISION E 05/19/14 ICS251 DATASHEET Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. The 251M-XX, 251M-XXLF, 251MI-XX, and 251MI-XXLF are factory programmed versions of the ICS251PM, ICS251PMLF, ICS251PMI, and ICS251PMILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. Part / Order Number Marking Shipping Packaging Package Temperature 251PM See Page 7 Above Tubes 8-pin SOIC 0 to +70  C 251PMI Tubes 8-pin SOIC -40 to +85  C 251PMLF Tubes 8-pin SOIC 0 to +70  C 251PMILF Tubes 8-pin SOIC -40 to +85  C 251M-XX 251M-XX Tubes 8-pin SOIC 0 to +70  C 251MI-XX 251MIXX Tubes 8-pin SOIC -40 to +85  C 251M-XXLF 251MXXL Tubes 8-pin SOIC 0 to +70  C 251MI-XXLF 251MIXXL Tubes 8-pin SOIC -40 to +85  C 251M-XXT 251M-XX Tape and Reel 8-pin SOIC 0 to +70  C 251MI-XXT 251MIXX Tape and Reel 8-pin SOIC -40 to +85  C 251M-XXLFT 251MXXL Tape and Reel 8-pin SOIC 0 to +70  C 251MI-XXLFT 251MIXXL Tape and Reel 8-pin SOIC -40 to +85  C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0

REVISION E 05/19/14 9 FIELD PR OGRAMMABLE SS VERSACLOCK SYNTHESIZER ICS251 DATASHEET

Revision History

Rev. Date Originator Description of Change E 05/19/14 J. Chao 1. Updated Supply Voltage max rating from 7V to 4.6V 2. Updated datasheet with latest version of template.

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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