24C64RP

M24128_07 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Clock (SCL)
• 2.2 Serial Data (SDA)
• 2.3 Chip Enable (E0, E1, E2)
• 2.4 Write Control (WC
• 2.5 V SS ground
• 2.6 Supply voltage (V CC)
• 2.6.1 Operating supply voltage V CC
• 2.6.2 Power-up conditions
• 2.6.3 Device reset
• 2.6.4 Power-down conditions
• 3 Memory organization
• 4 Device operation
• 4.1 Start condition
• 4.2 Stop condition
• 4.3 Acknowledge bit (ACK)
• 4.4 Data Input
• 4.5 Memory addressing
• 4.6 Write operations
• 4.7 Byte Write
• 4.8 Page Write
• 4.9 ECC (error correction code) and Write cycli ng
• 4.10 Minimizing system delays by polling on ACK
• 4.11 Read operations
• 4.12 Random Address Read
• 4.13 Current Address Read
• 4.14 Sequential Read
• 4.15 Acknowledge in Read mode

Features

■ Two-wire I2C serial interface supports 400 kHz protocol ■ Single supply voltages (see Table 1 for root part numbers): – 2.5 V to 5.5 V – 1.8 V to 5.5 V – 1.7 V to 5.5 V ■ Write Control input ■ Byte and Page Write ■ Random and Sequential Read modes ■ Self-timed programming cycle ■ Automatic address incrementing ■ Enhanced ESD/latch-up protection ■ More than 1 Million write cycles ■ More than 40-year data retention ■ Packages – ECOPACK® (RoHS compliant) Table 1. Device summary

M24128, M24C64, M24C32 Contents

Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width, Table 22. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

1 Description

and 16384 × 8 bits, respectively. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram 2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. bit (RW) (as described in Table 3), terminated by an acknowledge bit. terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 2. DIP, SO, TSSOP and UFDFPN connections

1. See Package mechanical section for package dimensions, and how to identify pin-1.

Table 2. Signal names

2 Signal description

2.1 Serial Clock (SCL)

2.2 Serial Data (SDA)

the value of the pull-up resistor can be calculated).

2.3 Chip Enable (E0, E1, E2)

floating), these inputs are read as low (0,0,0). Figure 3. Device select code

2.4 Write Control (WC )

Write operations are allowed. acknowledged, Data bytes are not acknowledged.

M24128, M24C64, M24C32 Signal description

2.5 V SS ground

VSS is the reference for the VCC supply voltage.

2.6 Supply voltage (V CC)

2.6.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W).

2.6.2 Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs.

2.6.3 Device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of V CC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 9 and Table 10). Until VCC passes over the POR threshold, the device is reset and in Standby Power mode. In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below the POR threshold voltage, the device is reset and stops responding to any instruction sent to it.

2.6.4 Power-down conditions

During power-down (continuous decay of VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal Write cycle in progress).

Table 3. Device select code

1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respec tive external pins on the memory device.

Table 4. Address most significant byte Table 5. Address least significant byte

3 Memory organization

The memory is organized as shown in Figure 6. Figure 6. Block diagram

1 Page

M24128, M24C64, M24C32 Device operation

4 Device operation

The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24C32, M24C64 and M24128 devices are always slaves in all communications.

4.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

4.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle.

4.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

4.4 Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

4.5 Memory addressing

in Table 3 (on Serial Data (SDA), most significant bit first). the Chip Enable (E0, E1, E2) inputs. th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus, and goes into Standby mode. Table 6. Operating modes

1 X reStart, device select, RW = 1

Figure 7. Write mode sequences with WC = 1 (data write inhibited)

Device operation M24128, M24C64, M24C32

4.6 Write operations

Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data Byte. Writing to the memory may be inhibited if Write Control (WC ) is driven high. Any Write instruction with Write Control (WC) driven high (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 7. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least Significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay t W, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

4.7 Byte Write

After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC ) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8.

4.8 Page Write

The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for the M24128) to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b13-b6 for M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes of data (for the M24128), each of which is acknowledged by the device if Write Control (WC is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition.

Figure 8. Write mode sequences with WC = 0 (data write enabled)

4.9 ECC (error correction code) and Write cycling

improved by the use of this feature. benefit from the larger amount of write cycles. using a cycling routine that writes to the device by multiples of 4-byte words.

Figure 9. Write cycle polling flowchart using ACK

4.10 Minimizing system delays by polling on ACK

sequence can be used by the bus master.

1. Initial condition: a Write cycle is in progress.
2. Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

1. Step 2: if the device is busy with the in ternal Write cycle, no Ack will be returned and

part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 10. Read mode sequences

1. The seven most significant bits of the dev ice select code of a Random Read (in the 1st and 4th bytes) must

Device operation M24128, M24C64, M24C32

4.11 Read operations

Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address.

4.12 Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.

4.13 Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the Byte.

4.14 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.

4.15 Acknowledge in Read mode

For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode.

5 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

6 Maximum rating

Table 7. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD- 020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
2. T LEAD max must not be applied for more than 10 s.

7 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. Figure 11. AC test measurement I/O waveform Table 8. Operating conditions (M24xxx-W) Table 9. Operating conditions (M24xxx-R) Table 10. Operating conditions (M24xxx-F) Table 11. AC test measurement conditions

Table 12. Input parameters Table 13. DC characteristics (M24xxx-W, device grade 6)

1. Characterized value, not tested in production.

Table 14. DC characteristics (M24xxx-W, device grade 3)

1. Characterized value, not tested in production.

Table 15. DC characteristics (M24xxx-R - device grade 6)

1. Characterized value, not tested in production.

Table 16. DC characteristics (M24xxx-F) (1)

1. Characterized value, not tested in production.

Table 17. AC characteristics (M24xxx-W6, M24xxW3, M24xxR6)

1. Values recommended by the I²C- bus Fast-Mode specification.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
3. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

× Cbus time constant is less than 500 ns (as specified in Figure 4).

1. For a reStart condition, or following a Write cycle.
2. For production lots assembled fr om 1st July 2007 (data code 727: week27, year 2007), the M24xxx-R

(1.8 V to 5.5 V range) memories are specified with tW = 5 ms (instead of 10ms).

Table 18. AC characteristics (M24xxx-F)

1. Values recommended by the I²C- bus Fast-Mode specification.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
3. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

× Cbus time constant is less than 500 ns (as specified in Figure 4).

1. For a reStart condition, or following a Write cycle.
2. For temperature range 6: t W(max) = 5 ms.

For temperature range 5: tW(max) = 10 ms.

Figure 12. AC waveforms

8 Package mechanical

Figure 13. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline Table 19. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

1. Values in inches are converted from mm and rounded to 4 decimal digits.

9 Part numbering

of this device, please contact your nearest ST sales office. soldering conditions are also marked on the inner box label. Table 23. Ordering information scheme

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

nearest ST sales office for a copy.

Table 24. Available M24C32 products (package, voltage range, temperature grade) Table 25. Available M24C64 products (package, voltage range, temperature grade) Table 26. Available M24128 products (package, voltage range, temperature grade)

Table 27. Document revision history Document reformatted using new template. TSSOP8 (3x3mm² body size) package (MSOP8) added. Operations, Read Operations. VIL(min) improved to -0.45V. Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. pins of the device. ZWCL changed. 05-Jan-2005 6.0 UFDFPN8 package added. Small text changes.

Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Power On Reset: VCC Lock-Out Write Protect section. Table 7: Absolute maximum ratings. SO8N package specifications updated (see Figure 14 and Table 20). Ordering information scheme. Small text changes. and M24128-BR part numbers added. Generic part number corrected in Features on page 1. ICC0 corrected in Table 14 and Table 13. Packages are ECOPACK® compliant. Table 24, Table 25 and Table 26. Notes modified below Table 12: Input parameters. C process code added to Table 23: Ordering information scheme. Table 27. Document revision history (continued)

(error correction code) and Write cycling added. to 4 decimal digits (see Section 8: Package mechanical). M24xxR6), and Table 18: AC characteristics (M24xxx-F). Updated Figure 12: AC waveforms. voltage range, temperature grade). Process B removed fromTable 23: Ordering information scheme.