24C640-EP

25AA640 MICROCHIP | Alldatasheet

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Technical content

ª 1997 Microchip Technology Inc. Preliminary DS21223A-page 1 M 25AA640/25LC640/25C640 DEVICE SELECTION TABLE

FEATURES

• Low power CMOS technology - Write current: 3 mA typical - Read current: 500 m A typical - Standby current: 500 nA typical
• 8192 x 8 bit organization
• 32 byte page
• Write cycle time: 5ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection - Protect none, 1/4, 1/2, or all of array
• Built-in write protection - Power on/off data protection circuitry - Write enable latch - Write protect pin
• Sequential read
• High reliability - Endurance: 1M cycles (guaranteed) - Data retention: > 200 years - ESD protection: > 4000 V
• 8-pin PDIP , SOIC, and TSSOP packages
• Temperature ranges supported:

DESCRIPTION

The Microchip Technology Inc. 25AA640/25LC640/ 25C640 (25xx640 ) is a 64K bit serial Electrically Eras- able PROM. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS ) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. PACKAGE TYPES BLOCK DIAGRAM Part Number V CC Range Max Clock Frequency Temp Ranges 25AA640 1.8-5.5V 1 MHz C,I 25LC640 2.5-5.5V 2 MHz C,I 25C640 4.5-5.5V 3 MHz C,I,E - Commercial: (C) 0 C to +70 C - Industrial: (I) -40 C to +85 C - Automotive: (E) (25C640) -40 C to +125 C 25xx640 TSSOP SCK SI V SS WP HOLD VCC CS SO 25xx640 PDIP/SOIC V CC HOLD SCK SI CS SO WP VSS SI SO SCK CS HOLD WP Status Register I/O Control Memory Control Logic X Dec HV Generator EEPROM Array Page Latches Y Decoder Sense Amp. R/W Control Logic VCC VSS 64K SPI Bus Serial EEPROM *25xx640 is used in this document as a generic part number for the 25AA640/25LC640/25C640 devices. SPI is a trademark of Motorola.

ª 1997 Microchip Technology Inc.

1.0 ELECTRICAL

1.1 Maxim um Ratings*

*Notice: Stresses above those listed under ‘Maximum ratings’ ma y cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability TABLE 1-1: PIN FUNCTION TABLE FIGURE 1-1: AC TEST CIR CUIT

1.2 AC Test Conditions

V SS Ground V CC Supply Voltage HOLD Hold Input AC W aveform: V LO = 0.2V V H I = V CC - 0.2V (Note 1) V H I = 4.0V (Note 2) Timing Measurement Reference Level Input 0.5 V CC Output 0.5 V CC Note 1: For V CC 4.0V For V CC > 4.0V VCC SO 100 pF1.8 K 2.25 K TABLE 1-2: DC C HARACTERISTICS All parameters apply over the specified operating ranges unless otherwise noted. Commercial (C): Tamb = 0 C to +70 C V CC = 1.8V to 5.5V Industrial (I): Tamb = -40 C to +85 C V CC = 1.8V to 5.5V Automotive (E): Tamb = -40 C to +125 C V CC = 4.5V to 5.5V (25C640 only) Parameter Symbol Min Max Units Test Conditions High level input voltage V IH 1 2.0 V CC +1 V V CC 2.7V (Note) V IH 2 0.7 V CC V CC +1 V V CC < 2.7V (Note) Low level input voltage V IL 1 -0.3 0.8 V V CC 2.7V (Note) V IL 2 -0.3 0.3 V CC V V CC < 2.7V (Note) Low level output voltage V OL — 0.4 V I OL = 2.1 mA V OL — 0.2 V I OL = 1.0 mA, V CC < 2.5V High level output voltage V OH V CC -0.5 — V I OH =-400 m A Input leakage current I LI -10 10 m A CS = V CC , V IN = V SS TO V CC Output leakage current I LO -10 10 m A CS = V CC , V OUT = V SS TO V CC Internal Capacitance (all inputs and outputs) C INT — 7 pF T AMB = 25˚C, CLK = 1.0 MHz, V CC = 5.0V (Note) Operating Current I CC Read — 500 mA m A V CC = 5.5V; F CLK =3.0 MHz; SO = Open V CC = 2.5V; F CLK =2.0 MHz; SO = Open I CC Wr ite — mA mA V CC = 5.5V V CC = 2.5V Standby Current I CCS m A m A CS = Vcc = 5.5V, Inputs tied to V CC or V SS CS = Vcc = 2.5V, Inputs tied to V CC or V SS Note: This parameter is periodically sampled and not 100% tested.

ª 1997 Microchip Technology Inc. Preliminary DS21223A -page 3 TABLE 1-3: AC C HARACTERISTICS All parameters apply over the specified operating ranges unless otherwise noted. Commercial (C): Tamb = 0 C to +70 C V CC = 1.8V to 5.5V Industrial (I): Tamb = -40 C to +85 C V CC = 1.8V to 5.5V Automotive (E): Tamb = -40 C to +125°C VCC = 4.5V to 5.5V (25C640 only) Parameter Symbol Min Max Units Test Conditions Clock Frequency FCLK — MHz MHz MHz V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V CS Setup Time TCSS 100 250 500 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V CS Hold Time TCSH 150 250 475 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V CS Disable Time TCSD 500 — ns Data Setup Time TSU 30 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Data Hold Time THD 50 100 100 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V CLK Rise Time TR — 2 ms (Note 1) CLK Fall Time TF — 2 ms (Note 1) Clock High Time THI 150 250 475 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Clock Low Time TLO 150 250 475 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Clock Delay Time TCLD 50 — ns Clock Enable Time TCLE 50 — ns Output Valid from Clock Low TV — 150 250 475 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Output Hold Time THO 0 — ns (Note 1) Output Disable Time TDIS — 200 250 500 ns ns ns V CC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) HOLD Setup Time THS 100 100 200 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V HOLD Hold Time THH 100 100 200 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V HOLD Low to Output High-Z THZ 100 150 200 ns ns ns V CC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) HOLD High to Output Valid THV 100 150 200 ns ns ns V CC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Internal Wr ite Cycle Time TWC — 5 ms Endurance — 1M — E/W Cycles (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

ª 1997 Microchip Technology Inc. Preliminary DS21223A -page 5

2.0 PIN DESCRIPTIONS

2.1 Chip Select (CS )

A low level on this pin selects the device. A high level deselects the device and forces it into standby mode. Ho w ever, a programming cycle which is already initi- ated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go in standby mode as soon as the programming cycle is complete. As soon as the device is deselected, SO goes to the high impedance state, allowing multiple parts to share the same SPI bus. A low to high transition on CS after a valid write sequence initiates an internal write cycle. After pow er- up, a high to low transition on CS is required prior to any sequence being initiated.

2.2 Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock.

2.3 Serial Output (SO)

The SO pin is used to transfer data out of the 25xx640. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.

2.4 Serial Clock (SCK)

The SCK is used to synchronize the communication between a master and the 25xx640. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

2.5 Write Protect (WP )

This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile bits in the status register. When WP is low and WPEN is high, writing to the non-volatile bits in the status regis- ter is disabled. All other operations function normally. When WP is high, all functions, including writes to the non-volatile bits in the status register operate normally. If the WPEN bit is set, WP low during a status register write sequence will disable writing to the status regis- ter. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the status register is low. This allows the user to install the 25AA640/25LC640/25C640 in a system with WP pin grounded and still be able to write to the status reg- ister. The WP pin functions will be enabled when the WPEN bit is set high.

2.6 Hold (HOLD )

The HOLD pin is used to suspend transmission to the 25xx640 while in the middle of a serial sequence with- out having to re-transmit the entire sequence over at a later time. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication with- out resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high to low transition. The 25xx640 must remain selected dur- ing this sequence. The SI, SCK, and SO pins are in a high impedance state during the time the part is paused and transitions on these pins will be ignored. To resume serial communication, HOLD m ust be brought high while the SCK pin is low, otherwise serial comm unication will not resume. Low ering the HOLD line at any time will tri-state the SO line.

DS21223A -page 6 Preliminary ª 1997 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

3.1 PRINCIPLES OF OPERA TION

The 25xx640 is a 8192 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X micro- controllers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25xx640 contains an 8-bit instruction register. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire opera- tion. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25xx640 in ‘HOLD’ mode . After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25xx640 follow ed by the 16-bit address with the three MSB’s of the address being don’t care bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incre- mented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1).

3.3 Write Sequence

Prior to any attempt to write data to the 25xx640 array or status register, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25xx640. After all eight bits of the instruction are transmitted, the CS m ust be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may pro- ceed by setting the CS low, issuing a write instruction, follow ed by the address, and then the data to be writ- ten. Up to 32 bytes of data can be sent to the 25xx640 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with XXX0 0000 and ends with XXX1 1111. If the internal address counter reaches XXX1 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS m ust be brought high after the least significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the status register may be read to check the status of the WPEN, WIP, WEL, BP1, and BP0 bits (Figure 3-6). A read attempt of a memor y array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. TABLE 3-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Wr ite data to memory array beginning at selected address WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read status register WRSR 0000 0001 Wr ite status register

DS21223A -page 8 Preliminary ª 1997 Microchip Technology Inc.

3.4 Write Enable (WREN) and Write

Disable (WRDI) The 25xx640 contains a write enable latch. S e e Table 3-3 for the Wr ite Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. The following is a list of conditions under which the write enable latch will be reset:

• Pow er-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed FIGURE 3-4: WRITE E N AB LE SEQUENCE FIGURE 3-5: WRITE DISAB LE SEQUENCE SCK 0 2 3 4 5 6 71 SI high impedance SO CS 0 10 0 0 0 01 SCK 0 2 3 4 5 6 71 SI high impedance SO CS 0 10 0 0 0 010

ª 1997 Microchip Technology Inc. Preliminary DS21223A -page 9

3.5 R ead Status Register (RDSR)

The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is format- ted as follows: The Write-In-Process (WIP) bit indicates whether the 25xx640 is busy with a write operation. When set to a ‘1’ a write is in progress, when set to a ‘0’ no write is in progress. This bit is read only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’ the latch allows writes to the array and status register, when set to a ‘0’ the latch prohibits writes to the array and status register. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the status register. This bit is read only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write protected. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile. See Figure 3-6 for RDSR timing sequence

3.6 Write Status Register(WRSR)

The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. The array is divided up into four segments. The user has the ability to write protect none, one, two, or all four of the seg- ments of the array. The partitioning is controlled as illustrated in Table 3-2. The Write Protect Enable (WPEN) bit is a non-volatile bit that is available as an enable bit for the WP pin. The Wr ite Protect (WP ) pin and the Wr ite Protect Enable (WPEN) bit in the status register control the programmab le hardware write protect feature. Hard- w are write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write protected, only writes to non-volatile bits in the status register are disabled. See Table 3-3 for a matrix of functionality on the WPEN bit. See Figure 3-7 for WRSR timing sequence TABLE 3-2: ARRA Y PROTECTION FIGURE 3-6: READ STATUS REGISTER SEQUENCE FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE 7 6 5 4 3 2 1 0 WPEN X X X BP1 BP0 WEL WIP BP1 BP0 Array Addresses Write Protected 0 0 none 0 1 upper 1/4 (1800h - 1FFFh) 1 0 upper 1/2 (1000h - 1FFFh) 1 1 all (0000h - 1FFFh) SO SI CS 9 10 11 12 13 14 15 1 100000 0 7 6 5 4 2 1 0 instruction data from status registerhigh impedance SCK 0 2 3 4 5 6 71 8 SO SI CS 9 10 11 12 13 14 15 0 100000 0 7 6 5 4 2 1 0 instruction data to status register high impedance SCK 0 2 3 4 5 6 71 8

DS21223A -page 10 Preliminary ª 1997 Microchip Technology Inc.

3.7 Data Protection

The following protection has been implemented to pre- vent inadvertent writes to the array:

• The write enable latch is reset on pow er-up.
• A write enable instruction must be issued to set the write enable latch.
• After a byte write, page write, or status register write, the write enable latch is reset.
• CS must be set high after the proper number of clock cycles to start an internal write cycle.
• Access to the array during an internal write cycle is ignored and programming is continued.

3.8 Power On State

The 25xx640 pow ers on in the following state:

• The device is in low pow er standby mode (CS = 1).
• The write enable latch is reset.
• SO is in high impedance state.
• A high to low transition on CS is required to enter the active state. TABLE 3-3: WRITE PR OTECT FUNCTIONALITY MATRIX WPEN WP WEL Protected Blocks Unprotected Blocks Status Register X X 0 Protected Protected Protected

0 X 1 Protected Wr itable Wr itable

1 Low 1 Protected Wr itable Protected

X High 1 Protected Wr itable Wr itable

ª 1997 Microchip Technology Inc. Preliminary DS21223A -page 11 25AA640/25LC640/25C640 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Package: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead ST = TSSOP , 8-lead Temperature Rang e: Blank = 0°C to +70°C I = –40°C to +85°C E = –40°C to +125°C De vices: 25AA640 64K bit 1.8V SPI Serial EEPROM 25AA640 T 64K bit 1.8V SPI Serial EEPROM Tape and Reel 25AA640 X 64K bit 1.8V SPI Serial EEPROM in alternate pinout (ST only) 25AA640 XT 64K bit 1.8V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25LC640 64K bit 2.5V SPI Serial EEPROM 25LC640 T 64K bit 2.5V SPI Serial EEPROM Tape and Reel 25LC640 X 64K bit 2.5V SPI Serial EEPROM in alternate pinout (ST only) 25LC640 XT 64K bit 2.5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25C640 64K bit 5.0V SPI Serial EEPROM 25C640 T 64K bit 5.0V SPI Serial EEPROM Tape and Reel 25C640 X 64K bit 5.0V SPI Serial EEPROM in alternate pinout (ST only) 25C640 XT 64K bit 5.0V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25xx640 — /P Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended w orkarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks DS21223A-page 12 ª 1997 Microchip Technology Inc. M All rights reserved. © 1997, Microchip Technology Incorporated, USA. 9/97 Printed on recycled paper. AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc.

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