2471AQ

TLV247X-Q1_16 TI1 | Alldatasheet

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/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Qualified for Automotive Applications /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068CMOS Rail-To-Rail Input/Output /C0068Input Bias Current...2.5 pA /C0068Low Supply Current. . . 600 µA/Channel /C0068Gain-Bandwidth Product. . . 2.8 MHz /C0068High Output Drive Capability − ±10 mA at 180 mV − ±35 mA at 500 mV /C0068Input Offset Voltage. . . 250 µV (typ) /C0068Supply Voltage Range. . . 2.7 V to 6 V

description

The TLV247x is a family of CMOS rail-to-rail input/output operational amplifiers that establishes a new performance point for supply current versus ac performance. These devices consume just 600 µA/channel while offering 2.8 MHz of gain-bandwidth product. Along with increased ac performance, the amplifier provides high output drive capability, solving a major shortcoming of older micropower operational amplifiers. The TLV247x can swing to within 180 mV of each supply rail while driving a 10-mA load. For non-RRO applications, the TLV247x can supply ±35 mA at 500 mV off the rail. Both the inputs and outputs swing rail-to-rail for increased dynamic range in low-voltage applications. This performance makes the TLV247x family ideal for sensor interface, portable medical equipment, and other data acquisition circuits. The family is fully specified at 3 V and 5 V across the automotive temperature range (−40°C to 125°C). FAMILY TABLE DEVICE NUMBER OF UNIVERSAL EVMDEVICE NUMBER OF CHANNELS UNIVERSAL EVM BOARD TLV2471 1 See the EVM TLV2472 2 See the EVM selection guide (SLOU060)TLV2474 4 selection guide (SLOU060) A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS ‡ DEVICE VDD (V) VIO (µV) BW (MHz) SLEW RATE (V/µs) IDD (per channel) (µA) OUTPUT DRIVE RAIL-TO-RAIL TLV247X 2.7 − 6 250 2.8 1.5 600 ±35 mA I/O TLV245X 2.7 − 6 20 0.22 0.11 23 ±10 mA I/O TLV246X 2.7 − 6 150 6.4 1.6 550 ±90 mA I/O TLV277X 2.5 − 6 360 5.1 10.5 1000 ±10 mA O ‡ All specifications measured at 5 V. Copyright  2008 Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NC IN− IN+ GND NC VDD OUT NC TLV2471 D PACKAGE (TOP VIEW)

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ORDERING INFORMATION † TA PACKAGE /C0125 ORDERABLE PART NUMBER TOP-SIDE MARKING SOP − D Tape and reel TLV2471QDRQ1 2471Q1 −40°C to 125°C SOP − D Tape and reel TLV2471AQDRQ1 2471AQ−40 C to 125C SOT23 − DBV Tape and reel TLV2471QDBVRQ1 471Q SOP − D Tape and reel TLV2472QDRQ1 2472Q1 −40°C to 125°C SOP − D Tape and reel TLV2472AQDRQ1 2472AQ−40 C to 125C MSOP − DGN Tape and reel TLV2472QDGNRQ1 § SOP − D Tape and reel TLV2474QDRQ1 2474Q1 −40°C to 125°C SOP − D Tape and reel TLV2474AQDRQ1 2474AQ1 −40°C to 125°C TSSOP − PWP Tape and reel TLV2474QPWPRQ1 2474Q1 TSSOP − PWP Tape and reel TLV2474APWPRQ1 2474AQ1 † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. § Product Preview. TLV247x PACKAGE PINOUTS 1OUT 1IN− 1IN+ GND VDD 2OUT 2IN− 2IN+ TLV2472 D OR DGN PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT (TOP VIEW) TLV2474 D OR PWP PACKAGE NC − No internal connection TLV2471 DBV PACKAGE (TOP VIEW) 1OUT GND IN+ VDD IN−

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltage values, except differential voltages, are with respect to GND. DISSIPATION RATING TABLE PACKAGE θJC (°C/W) θJA (°C/W) TA ≤ 25°C POWER RATING D (8) 38.3 176 710 mW D (14) 26.9 122.3 1022 mW DBV (3) 55 324.1 385 mW DGN (8) 4.7 52.7 2370 mW PWP (14) 2.07 30.7 4070 mW recommended operating conditions MIN MAX UNIT Supply voltage, VDD Single supply 2.7 6 VSupply voltage, VDD Split supply ±1.35 ±3 V Common-mode input voltage range, VICR 0 VDD V Operating free-air temperature, TA −40 125 °C † Relative to GND

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT V = V /2, TLV247x 25°C 250 2200 VIO Input offset voltage VIC = VDD /2, VO = VDD /2, TLV247x Full range 2400 VVIO Input offset voltage IC DD VO = VDD /2, R S = 50 Ω TLV247xA 25°C 250 1600 µV R S = 50 Ω TLV247xA Full range 1800 VIO Temperature coefficient of inputVIC = VDD /2, VO = VDD /2, 0.4 V/°CαVIO Temperature coefficient of input offset voltage IC DD VO = VDD /2, R S = 50 Ω 0.4 µV/°C IIO Input offset current VIC = VDD /2, VO = VDD /2, 25°C 1.5 50 IIO Input offset current IC DD VO = VDD /2, R S = 50 Ω Full range 300 pA IIB Input bias current VIC = VDD /2, VO = VDD /2, 25°C 2 50 pA IIB Input bias current IC DD VO = VDD /2, R S = 50 Ω Full range 300 IOH = −2.5 mA 25°C 2.85 2.94 VOH High-level output voltage VIC = VDD /2 IOH = −2.5 mA Full range 2.8 VVOH High-level output voltage V IC = VDD /2 IOH = −10 mA 25°C 2.6 2.74 V IOH = −10 mA Full range 2.5 IOL = 2.5 mA 25°C 0.07 0.15 VOL Low-level output voltage VIC = VDD /2 IOL = 2.5 mA Full range 0.2 VVOL Low-level output voltage V IC = VDD /2 IOL = 10 mA 25°C 0.2 0.35 V IOL = 10 mA Full range 0.5 Sourcing 25°C 30 IOS Short-circuit output current Sourcing Full range 20 mAIOS Short-circuit output current Sinking 25°C 30 mA Sinking Full range 20 IO Output current VO = 0.5 V from rail 25°C ±22 mA AVD Large-signal differential voltage VO(PP) = 1 V, R L = 10 kΩ 25°C 90 116 dBAVD Large-signal differential voltage amplification VO(PP) = 1 V, R L = 10 kΩ Full range 88 dB ri(d) Differential input resistance 25°C 1012 Ω C IC Common-mode input capacitance f = 10 kHz 25°C 19.3 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 2 Ω CMRR Common-mode rejection ratio VIC = 0 to 3 V, 25°C 58 78 dBCMRR Common-mode rejection ratio VIC = 0 to 3 V, R S = 50Ω Full range 56 dB VDD = 2.7 V to 6 V,VIC = VDD /2, 25°C 68 90 kSVR Supply voltage rejection ratio VDD = 2.7 V to 6 V, No load VIC = VDD /2, Full range 60 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 3 V to 5 V, VIC = VDD /2, 25°C 70 92 dB( VDD /VIO) VDD = 3 V to 5 V, No load VIC = VDD /2, Full range 60 IDD Supply current (per channel) VO = 1.5 V, No load 25°C 550 750 µAIDD Supply current (per channel) VO = 1.5 V, No load Full range 800 µA † Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT SR Slew rate at unity gain VO(PP) = 0.8 V, C L = 150 pF, 25°C 1.1 1.4 V/ sSR Slew rate at unity gain VO(PP) = 0.8 V, R L = 10 kΩ C L = 150 pF, Full range 0.6 V/µs Vn Equivalent input noise voltage f = 100 Hz 25°C 28 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 15 nV/√Hz In Equivalent input noise current f = 1 kHz 25°C 0.405 pA/√Hz VO(PP) = 2 V, AV = 1 0.02% THD + N Total harmonic distortion plus noise VO(PP) = 2 V, R L = 10 kΩ, f = 1 kHz AV = 10 25°C 0.1%THD + N Total harmonic distortion plus noiseR L = 10 kΩ, f = 1 kHz AV = 100 25 C 0.5% Gain-bandwidth product f = 10 kHz, R L = 600 Ω 25°C 2.8 MHz V(STEP)PP = 2 V, AV = −1, 0.1% 1.5 ts Settling time AV = −1, C L = 10 pF, R L = 10 kΩ 0.01% 25°C 3.9 sts Settling time V(STEP)PP = 2 V, AV = −1, 0.1% 25°C 1.6 µs AV = −1, C L = 56 pF, R L = 10 kΩ 0.01% 4 φm Phase margin R L = 10 kΩ, C L = 1000 pF 25°C 61° Gain margin R L = 10 kΩ, C L = 1000 pF 25°C 15 dB † Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C. ‡ Depending on package dissipation rating

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT V = V /2, TLV247x 25°C 250 2200 VIO Input offset voltage VIC = VDD /2, VO = VDD /2, TLV247x Full range 2400 VVIO Input offset voltage IC DD VO = VDD /2, R S = 50 Ω TLV247xA 25°C 250 1600 µV R S = 50 Ω TLV247xA Full range 2000 VIO Temperature coefficient of inputVIC = VDD /2, VO = VDD /2, 0.4 V/°CαVIO Temperature coefficient of input offset voltage IC DD VO = VDD /2, R S = 50 Ω 0.4 µV/°C IIO Input offset current VIC = VDD /2, VO = VDD /2, 25°C 1.7 50 IIO Input offset current IC DD VO = VDD /2, R S = 50 Ω Full range 300 pA IIB Input bias current VIC = VDD /2, VO = VDD /2, 25°C 2.5 50 pA IIB Input bias current IC DD VO = VDD /2, R S = 50 Ω Full range 300 IOH = −2.5 mA 25°C 4.85 4.96 VOH High-level output voltage VIC = VDD /2 IOH = −2.5 mA Full range 4.8 VVOH High-level output voltage V IC = VDD /2 IOH = −10 mA 25°C 4.72 4.82 V IOH = −10 mA Full range 4.65 IOL = 2.5 mA 25°C 0.07 0.15 VOL Low-level output voltage VIC = VDD /2 IOL = 2.5 mA Full range 0.2 VVOL Low-level output voltage V IC = VDD /2 IOL = 10 mA 25°C 0.178 0.28 V IOL = 10 mA Full range 0.35 Sourcing 25°C 110 IOS Short-circuit output current Sourcing Full range 60 mAIOS Short-circuit output current Sinking 25°C 90 mA Sinking Full range 60 IO Output current VO = 0.5 V from rail 25°C ±35 mA AVD Large-signal differential voltage VO(PP) = 3 V, R L = 10 kΩ 25°C 92 120 dBAVD Large-signal differential voltage amplification VO(PP) = 3 V, R L = 10 kΩ Full range 91 dB ri(d) Differential input resistance 25°C 1012 Ω C IC Common-mode input capacitance f = 10 kHz 25°C 18.9 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 1.8 Ω CMRR Common-mode rejection ratio VIC = 0 to 5 V, 25°C 62 84 dBCMRR Common-mode rejection ratio VIC = 0 to 5 V, R S = 50Ω Full range 58 dB VDD = 2.7 V to 6 V,VIC = VDD /2, 25°C 68 90 kSVR Supply voltage rejection ratio VDD = 2.7 V to 6 V, No load VIC = VDD /2, Full range 60 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 3 V to 5 V, VIC = VDD /2, 25°C 70 92 dB( VDD /VIO) VDD = 3 V to 5 V, No load VIC = VDD /2, Full range 60 IDD Supply current (per channel) VO = 2.5 V, No load 25°C 600 900 µAIDD Supply current (per channel) VO = 2.5 V, No load Full range 1000 µA † Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT SR Slew rate at unity gain VO(PP) = 2 V, C L = 150 pF, 25°C 1.1 1.5 V/ sSR Slew rate at unity gain VO(PP) = 2 V, R L = 10 kΩ C L = 150 pF, Full range 0.7 V/µs Vn Equivalent input noise voltage f = 100 Hz 25°C 28 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 15 nV/√Hz In Equivalent input noise current f = 1 kHz 25°C 0.39 pA/√Hz VO(PP) = 4 V, AV = 1 0.01% THD + N Total harmonic distortion plus noise VO(PP) = 4 V, R L = 10 kΩ, f = 1 kHz AV = 10 25°C 0.05%THD + N Total harmonic distortion plus noiseR L = 10 kΩ, f = 1 kHz AV = 100 25 C 0.3% Gain-bandwidth product f = 10 kHz, R L = 600 Ω 25°C 2.8 MHz V(STEP)PP = 2 V, AV = −1, 0.1% 1.8 ts Settling time AV = −1, C L = 10 pF, R L = 10 kΩ 0.01% 25°C 3.3 sts Settling time V(STEP)PP = 2 V, AV = −1, 0.1% 25°C 1.7 µs AV = −1, C L = 56 pF, R L = 10 kΩ 0.01% 3 φm Phase margin R L = 10 kΩ, C L = 1000 pF 25°C 68° Gain margin R L = 10 kΩ, C L = 1000 pF 25°C 23 dB † Full range is −40°C to 125°C for Q suffix. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIO Input offset voltage vs Common-mode input voltage 1, 2 IIB Input bias current vs Free-air temperature 3, 4IIO Input offset current vs Free-air temperature 3, 4 VOH High-level output voltage vs High-level output current 5, 7 VOL Low-level output voltage vs Low-level output current 6, 8 Zo Output impedance vs Frequency 9 IDD Supply current vs Supply voltage 10 PSRR Power supply rejection ratio vs Frequency 11 CMRR Common-mode rejection ratio vs Frequency 12 Vn Equivalent input noise voltage vs Frequency 13 VO(PP) Maximum peak-to-peak output voltage vs Frequency 14, 15 AVD Differential voltage gain and phase vs Frequency 16, 17 φm Phase margin vs Load capacitance 18, 19 Gain margin vs Load capacitance 20, 21 Gain-bandwidth product vs Supply voltage 22 SR Slew rate vs Supply voltage 23 SR Slew rate vs Free-air temperature 24, 25 Crosstalk vs Frequency 26 THD+N Total harmonic distortion + noise vs Frequency 27, 28 VO Large and small signal follower vs Time 29 − 32

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VDD − Supply Voltage − V IDD − Supply Current − mA AV= 1 SHDN = VDD Per Channel SUPPLY CURRENT vs SUPPLY VOLTAGE TA=125°C TA=85°C TA=25°C TA=−40°C 100 POWER SUPPLY REJECTION RATIO vs FREQUENCY f − Frequency − Hz − Power Supply Rejection Ratio − dBPSRR 10 100 1k 10k 100k 1M 10M VDD =3 & 5 V R F=5 kΩ R I=50 Ω TA=25°C PSRR+ PSRR− Figure 11 Figure 12 100 110 120 130 COMMON-MODE REJECTION RATIO vs FREQUENCY f − Frequency − Hz 100 1k 10k 100k 1M 10M CMRR − Common-Mode Rejection Ratio − dB VDD =5 V VIC=2.5 V VDD =3 V VIC=1.5 V Figure 13 EQUIVALENT NOISE VOLTAGE vs FREQUENCY f − Frequency − Hz 1k 10k 100k10 100 nV/ Hz− Equivalent Input Noise Voltage −V n VDD =3 & 5 V AV= 10 VIN= VDD /2 TA=25°C Figure 14 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY f − Frequency − Hz 1M10k 100k V O(PP) − Maximum Peak-To-Peak Output Voltage − V VO(PP)=5 V VO(PP)=3 V THD+N ≤ 2.0% R L=10 kΩ TA=25°C Figure 15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY f − Frequency − Hz 1M10k 100k VO(PP)=3 V VO(PP)=5 V THD+N ≤ 2.0% R L=600 Ω TA=25°C V O(PP) − Maximum Peak-To-Peak Output Voltage − V Figure 16 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY Frequency − Hz 100 1k 10k 100k − Differential Voltage Gain − dB −40 −20 100 −135 −180 −270 −225 −45 −90 Phase − ° 1M 10M 100M VDD =±3 R L=600 Ω C L=0 TA=25°C AVD Figure 17 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY Frequency − Hz 100 1k 10k 100k −40 −20 100 −135 −180 −270 −225 −45 −90 Phase − ° 1M 10M 100M VDD =±5 R L=600 Ω C L=0 TA=25°C − Differential Voltage Gain − dBAVD

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f − Frequency − Hz 10 100 10 k 100 k Crosstalk − dB−100 −120 −140 −60 −80 −40 −160 1 k −20 VDD = 3V & 5V A V = 1 R L= 600Ω VI(PP)=2V All Channels Figure 27 10 1k 10k100 0.001 0.01 0.1 100k TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY THD+N−Total Harmonic Distortion + Noise f − Frequency − Hz A V = 10 A V = 1 VDD = 3 V R L = 10 kΩ V0 = 2 VPP TA = 25°C A V = 100 Figure 28 10 1k 10k100 0.001 0.01 0.1 100k VDD = 5 V R L = 10 kΩ V0 = 4 VPP TA = 25°C TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY THD+N−Total Harmonic Distortion + Noise f − Frequency − Hz AV = 100 AV = 10 AV = 1 Figure 29 0 1 2 3456789 1 0 t − Time − µs − Output Voltage LARGE SIGNAL FOLLOWER PULSE RESPONSE vs TIME V O VDD = 3 V R L = 10 kΩ C L = 8 pF f = 85 kHz TA = 25°C VI (2 V/DIV) VO (1 V/DIV) Figure 30 t − Time − µs LARGE SIGNAL FOLLOWER PULSE RESPONSE vs TIME 0 12 3 45 67891 0 VDD = 5 V R L = 10 kΩ C L = 8 pF f = 85 kHz TA = 25°C VI (2 V/DIV) VO (1 V/DIV) − Output Voltage V O Figure 31 t − Time − µs SMALL SIGNAL FOLLOWER PULSE RESPONSE vs TIME 0 100 200 300 400 500 VDD = 3 V R L = 10 kΩ C L = 8 pF f = 1 MHz TA = 25°C VI (50 mV/DIV) VO (50 mV/DIV) − Output Voltage V O Figure 32 t − Time − µs SMALL SIGNAL FOLLOWER PULSE RESPONSE vs TIME 0 100 200 300 400 500 VDD = 5 V R L = 10 kΩ C L = 8 pF f = 1 MHz TA = 25°C VI (50 mV/DIV) VO (50 mV/DIV) − Output Voltage V O

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 36). VI VO R G R F f–3dB /C00431 2/C0112R1C1 V O V I /C0043/C04661 /C0041 R F R G /C0467/C04661 1 /C0041sR1C1 /C0467 Figure 36. Single-Pole Low-Pass Filter task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. Figure 37. 2-Pole Low-Pass Sallen-Key Filter

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 circuit layout considerations To achieve the levels of high performance of the TLV247x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. /C0068Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. /C0068Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. /C0068Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. /C0068Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier. /C0068Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible.

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

general PowerPAD design considerations The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 38(a) and Figure 38(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 38(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) End View (b) Bottom View (c) DIE Thermal Pad NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 38. Views of Thermally Enhanced DGN Package Figure 39. PowerPAD PCB Etch and Via Pattern PowerPAD is a trademark of Texas Instruments Incorporated.

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 general PowerPAD design considerations (continued) 1. Prepare the PCB with a top side etch pattern as shown in Figure 39. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θ JA, the maximum power dissipation is shown in Figure 40 and is calculated by the following formula: P D /C0043/C0466 TMAX –TA /C0113JA /C0467 Where: PD = Maximum power dissipation of TLV247x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W)

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

general PowerPAD design considerations (continued) TJ = 150°C −55 −40 −10 20 35 Maximum Power Dissipation − W MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 65 95 125 TA − Free-Air Temperature − °C Low-K Test PCB θJA = 52.3°C/W Low-K Test PCB θJA = 324°C/W −25 5 50 80 110 Low-K Test PCB θJA = 29.7°C/W Low-K Test PCB θJA = 176°C/W NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 40. The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 41 to Figure 46 show this effect, along with the quiescent heat, with an ambient air temperature of 70°C and 125°C. When using V DD = 3 V, there is generally not a heat problem with an ambient air temperature of 70°C. But, when using VDD = 5 V, the packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ JA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package.

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

general PowerPAD design considerations (continued) Figure 45 100 0 0.25 0.5 0.75 − Maximum RMS Output Current − mA 140 180 1 1.25 160 120 | VO | − RMS Output Voltage − V IO|| Maximum Output Current Limit Line TLV2474† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 1.5 Safe Operating Area VDD = ±3 V TJ = 150°C TA = 125°C Packages With θJA ≤ 88°C/W at TA = 70°CC D Figure 46 100 0 0.5 1 1.5 − Maximum RMS Output Current − mA 140 180 2 2.5 160 120 | VO | − RMS Output Voltage − V IO|| Maximum Output Current Limit Line TLV2474† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS Safe Operating Area VDD = ± 5 V TJ = 150°C TA = 125°C Packages With θJA ≤ 52°C/W at TA = 70°C D C † A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14)

/C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0262/C0081/C0049/C0044 /C0084/C0076/C0086/C0050/C0052/C0055/C0120/C0065/C0262/C0081/C0049 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0054/C0048/C0048/C0262µ/C0065/C0047/C0067/C0104 /C0050/C0046/C0056/C0262/C0077/C0072/C0122 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0072/C0073/C0071/C0072/C0262/C0068/C0082/C0073/C0086/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SGLS180B − AUGUST 2003 − REVISED APRIL 2008 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Macromodel information provided was derived using MicrosimParts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 47 are generated using the TLV247x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068Maximum positive output voltage swing /C0068Maximum negative output voltage swing /C0068Slew rate /C0068Quiescent power dissipation /C0068Input bias current /C0068Open-loop voltage amplification /C0068Unity-gain frequency /C0068Common-mode rejection ratio /C0068Phase margin /C0068DC output resistance /C0068AC output resistance /C0068Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). * TLV247x operational amplifier ”macromodel” subcircuit * created using Parts release 8.0 on 4/27/99 at 14:31 * Parts is a MicroSim product. * connections: non−inverting input * | inverting input * | | positive power supply * | | | negative power supply .subckt TLV247x 1 2 3 4 5 c1 11 12 1.1094E−12 c2 6 7 5.5000E−12 css 10 99 556.53E−15 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx fb 7 99 poly(5) vb vc ve vlp vln 0 + 39.614E6 −1E3 1E3 40E6 −40E6 ga 6 0 11 12 79.828E−6 gcm 0 6 10 99 32.483E−9 iss 10 4 dc 10.714E−6 hlim 90 0 vlim 1K ioff 0 6 dc 75E−9 j1 11 2 10 jx1 j2 12 1 10 jx2 r2 6 9 100.00E3 rd1 3 11 12.527E3 rd2 3 12 12.527E3 ro1 8 5 10 ro2 7 99 10 rp 3 4 3.8023E3 rss 10 99 18.667E6 vb 9 0 dc 0 vc 3 53 dc .842 ve 54 4 dc .842 vlim 7 8 dc 0 vlp 91 0 dc 110 vln 0 92 dc 110 .model dx D(Is=800.00E−18) .model dy D(Is=800.00E−18 Rs=1m Cjo=10p) .model jx1 NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1) .model jx2 NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1) .ends IN− G D S D S G rp IN+ rd1 rd2 rss egnd fb ro2 ro1 vlim OUT ga ioffgcm vb dciss dp GND VDD css ve de dlp dln vlnhlimvlp 11 12 91 90 92 vc − + Figure 47. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation.

www.ti.com 25-Mar-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV2471AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2471AQ TLV2471AQDRQ1 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2471QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 471Q TLV2471QDRQ1 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2472AQDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2472AQ TLV2472AQDRQ1 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLV2472QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2472Q1 TLV2472QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2472Q1 TLV2474APWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2474AQ1 TLV2474AQDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2474AQ1 TLV2474AQDRQ1 OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 125 TLV2474QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2474Q1 TLV2474QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2474Q1 TLV2474QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2474Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.

www.ti.com 25-Mar-2015 Addendum-Page 2 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2471-Q1, TLV2471A-Q1, TLV2472-Q1, TLV2472A-Q1, TLV2474-Q1, TLV2474A-Q1 :

• Catalog: TLV2471 , TLV2471A , TLV2472 , TLV2472A , TLV2474 , TLV2474A NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2471QDBVRQ1 SOT-23 DBV 5 3000 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 Pack Materials-Page 2

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