HM-6514 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • TTL Compatible Input/Output
  • Common Data Input/Output
  • Three-State Output
  • Standard JEDEC Pinout
  • 18 Pin Package for High Density
  • On-Chip Address Register
  • Gated Inputs - No Pull Up or Pull Down Resistors Required

Description

The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also elimi- nate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaran- teed over temperature.

Ordering Information

120ns 200ns 300ns TEMPERATURE RANGE PACKAGE PKG. NO. HM3-6514S-9 HM3-6514B-9 HM3-6514-9 -40 oC to +85oC PDIP E18.3 HM1-6514S-9 HM1-6514B-9 HM1-6514-9 -40 oC to +85oC CERDIP F18.3 24502BVA - - - JAN# F18.3 8102402VA 8102404VA 8102406VA - SMD# F18.3 --- - 4 0 oC to +85oC CLCC J18.B - - HM4-6514-B -55 oC to +125oC J18.B Pinouts HM-6514 (PDIP, CERDIP) TOP VIEW HM-6514 (CLCC) TOP VIEW

1 VCC

W E GND PIN DESCRIPTION A Address Input E Chip Enable W Write Enable D Data Input Q Data Output 8 9 10 11 21 1 7 GND DQ3 W E DQ0 DQ1 DQ2 VCC File Number 2995.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

A L G A 64 x 64 MATRIX G E W LATCHED ADDRESS REGISTER A A L 16 16 16 16

1 OF 4

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Ranges: oC to +85oC Thermal Resistance (Typical) θJA θJC Maximum Junction Temperature Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX ICCSB Standby Supply Current HM-6514-9 - 25 µA IO = 0mA, E = VCC -0.3V, VCC = 5.5V HM-6514-8 - 50 µA ICCOP Operating Supply Current (Note 1) - 7 mA E = 1MHz, IO = 0mA, VI = GND, VCC = 5.5V ICCDR Data Retention Supply Current HM-6514-9 - 15 µA IO = 0mA, V CC = 2.0V,E = VCC HM-6514-8 - 25 µA VCCDR Data Retention Supply Voltage 2.0 - V II Input Leakage Current -1.0 +1.0 µA VI = V CC or GND, VCC = 5.5V IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = V CC or GND, VCC = 5.5V VIL Input Low Voltage -0.3 0.8 V V CC = 4.5V VIH Input High Voltage V CC -2.0 V CC +0.3 V V CC = 5.5V VOL Output Low Voltage - 0.4 V IO = 2.0mA, V CC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -1.0mA, V CC = 4.5V VOH2 Output High Voltage (Note 2) V CC -0.4 - V IO = -100 µA, VCC = 4.5V Capacitance TA = +25oC SYMBOL PARAMETER MAX UNITS TEST CONDITIONS CI Input Capacitance (Note 2) 8 pF f = 1MHz, All measurements are referenced to device GND CIO Input/Output Capacitance (Note 2) 10 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP . 2. Tested at initial design and after major design changes. HM-6514

TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONS HM-6514S-9 HM-6514B-9 HM-6514-9 MIN MAX MIN MAX MIN MAX (1) TELQV Chip Enable Access Time - 120 - 220 - 300 ns (Notes 1, 3) (2) TAVQV Address Access Time - 120 - 220 - 320 ns (Notes 1, 3, 4) (3) TELQX Chip Enable Output Enable Time 5 - 5 - 5 - ns (Notes 2, 3) (4) TEHQZ Chip Enable Output Disable Time - 50 - 80 - 100 ns (Notes 2, 3) (5) TELEH Chip Enable Pulse Negative Width 120 - 200 - 300 - ns (Notes 1, 3) (6) TEHEL Chip Enable Pulse Positive Width 50 - 90 - 120 - ns (Notes 1, 3) (7) TAVEL Address Setup Time 0 - 20 - 20 - ns (Notes 1, 3) (8) TELAX Address Hold Time 40 - 50 - 50 - ns (Notes 1, 3) (9) TWLWH Write Enable Pulse Width 120 - 200 - 300 - ns (Notes 1, 3) (10)TWLEH Chip Enable Write Pulse Setup Time 120 - 200 - 300 - ns (Notes 1, 3) (11)TELWH Chip Enable Write Pulse Hold Time 120 - 200 - 300 - ns (Notes 1, 3) (12)TDVWH Data Setup Time 50 - 120 - 200 - ns (Notes 1, 3) (13)TWHDX Data Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (14)TWLDV Write Data Delay Time 70 - 80 - 100 - ns (Notes 1, 3) (15)TWLEL Early Output High-Z Time 0 - 0 - 0 - ns (Notes 1, 3) (16)TEHWH Late Output High-Z Time 0 - 0 - 0 - ns (Notes 1, 3) (17)TELEL Read or Write Cycle Time 170 - 290 - 420 - - (Notes 1, 3) NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF , access time is derated by 0.15ns per pF . 2. Tested at initial design and after major design changes. 3. V CC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL. HM-6514

enabled, but data is not valid until during time (T = 2). the next memory cycle (T = 4). FIGURE 1. READ CYCLE

0 H V Z Cycle Begins, Addresses are Latched

1 L H X X Output Enabled

2 L H X V Output Valid

3 H X V Read Accomplished

4 H X X Z Prepare for Next Cycle (Same as -1)

5 H V Z Cycle Ends, Next Cycle Begins (Same as 0)

the control of the common data-in/data-out bus. write cycle TWLEL and TEHWH may be ignored. ten (an extension of Case 2). FIGURE 2. WRITE CYCLE

0 X V Z Cycle Begins, Addresses are Latched

1 L L X Z Write Period Begins

2 L X V Data In is Written

3 H X Z Write Completed

5 X V Z Cycle Ends, Next Cycle Begins (Same as 0)

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Test Load Circuit NOTE: 1. Test head capacitance. DUT 1.5V IOLIOH +- (NOTE 1) CL EQUIVALENT CIRCUIT HM-6514