23LCV512-I/P

23LCV512_V01 MICROCHIP | Alldatasheet

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Technical content

 2012-2021 Microchip Technology Inc. DS20005157B-page 1 23LCV512 Device Selection Table Features:

• SPI-Compatible Bus Interface: - 20 MHz Clock rate - SPI/SDI mode
• Low-Power CMOS Technology: - Read Current: 3 mA at 5.5V, 20 MHz - Standby Current: 4 A at +85°C
• Unlimited Read and Write Cycles
• External Battery Backup support
• Zero Write Time
• 64K x 8-bit Organization: - 32-byte page
• Byte, Page and Sequential mode for Reads and Writes
• High Reliability
• Temperature Range Supported:
• Pb-Free and RoHS Compliant, Halogen Free.
• 8-Lead SOIC, TSSOP and PDIP Packages Pin Function Table Description: The Microchip Technology Inc. 23LCV512 is a 512-Kbit Serial SRAM device. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS ) input. Additionally, SDI (Serial Dual Inter- face) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array, and supports data backup via exter- nal battery/coin cell connected to V BAT (pin 7). The 23LCV512 is available in standard packages including 8-lead SOIC, PDIP and advanced 8-lead TSSOP . Package Types (not to scale) Part Number VCC Range Dual I/O (SDI) Battery Backup Max. Clock Frequency Packages 23LCV512 2.5-5.5V Yes Yes 20 MHz SN, ST, P - Industrial (I): -40 Ct o + 8 5 C Name Function CS Chip Select Input SO/SIO1 Serial Output/SDI pin Vss Ground SI/SIO0 Serial Input/SDI pin SCK Serial Clock V BAT External Backup Supply Input Vcc Power Supply CS SO/SIO1 NC Vss Vcc VBAT SCK SI/SIO0 SOIC/TSSOP/PDIP 512-Kbit SPI Serial SRAM with Battery Backup and SDI Interface

DS20005157B-page 2  2012-2021 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†) TABLE 1-1: DC CHARACTERISTICS † NOTICE: Stresses above those listed under “Absolute Maximu m Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. DC CHARACTERISTICS Industrial (I): T A = -40°C to +85°C Param. D001 V CC Supply voltage 2.5 — 5.5 V 23LCV512 D002 V IH High-level input voltage 0.7 x VCC —V CC + 0.3 V D003 V IL Low-level input voltage -0.3 — 0.10 x VCC V 23LCV512 D004 V OL Low-level output voltage ——0 . 2V I OL = 1 mA D005 V OH High-level output voltage VCC - 0.5 — — V I OH = -400 A D006 I LI Input leakage current —— ± 1 AC S = VCC, VIN = VSS OR VCC D007 I LO Output leakage current —— ± 1 AC S = VCC, VOUT = VSS OR VCC D008 I CC Read Operating current — 3 10 mA F CLK = 20 MHz; SO = O, 5.5V D009 I CCS Standby current — 4 10 AC S = VCC = 5.5V, Inputs tied to VCC or VSS D010 C INT Input capacitance — — 7 pF V CC = 0V, f = 1 MHz, Ta = 25°C (Note 1) D011 V DR RAM data retention voltage —1 . 0 — V (Note 2) D012 V TRIP VBAT Change Over 1.6 1.8 2.0 V Typical at Ta = 25°C (Note 1) D013 V BAT VBAT Voltage Range 1.4 — 3.6 V (Note 1) D014 IBAT V BAT Current — 1 — A Typical at 2.5V, Ta = 25°C (Note 1) Note 1: This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature (25°C). 2: This is the limit to which VDD can be lowered without losing RAM data. This parameter is periodically sampled and not 100% tested.

 2012-2021 Microchip Technology Inc. DS20005157B-page 3 23LCV512 TABLE 1-3: AC TEST CONDITIONS TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): T A = -40°C to +85°C Param. No. Sym. Characteristic Min. Max. Units Test Conditions 1F CLK Clock frequency — 20 MHz 2T CSS CS setup time 25 — ns 3T CSH CS hold time 50 — ns 4T CSD CS disable time 25 — ns

5 Tsu Data setup time 10 — ns

6T HD Data hold time 10 — ns 7T R CLK rise time — 20 ns Note 1 8T F CLK fall time — 20 ns Note 1 9T HI Clock high time 25 — ns

10 T LO Clock low time 25 — ns

11 T CLD Clock delay time 25 — ns

12 T V Output valid from clock low —2 5 n s

13 T HO Output hold time 0 — ns Note 1

14 T DIS Output disable time —2 0 n s

Note 1: This parameter is periodically sampled and not 100% tested. AC Waveform: Input pulse level 0.1 x V CC to 0.9 x VCC Input rise/fall time 5 ns Operating temperature -40°C to +85°C C L = 30 pF — Timing Measurement Reference Level: Input 0.5 x V CC Output 0.5 x V CC

 2012-2021 Microchip Technology Inc. DS20005157B-page 5 23LCV512

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 23LCV512 is an 512 Kbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC ® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines pro- grammed properly in firmware to match the SPI proto- col. In addition, the 23LCV512 is also capable of operating in SDI (or dual SPI) mode. The 23LCV512 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSb first, LSb last.

2.2 Modes of Operation

The 23LCV512 has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Burst. Byte Operation – is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/ write operations are limited to only one byte. The command followed by the 16-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks (Figure 2-1, Figure 2-2). Page Operation – is selected when bits 7 and 6 in the MODE register are set to 10. The 23LCV512 has 2048 pages of 32 bytes. In this mode, the read and write oper- ations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure 2-3, Figure 2-4). Sequential Operation – is selected when bits 7 and 6 in the MODE register are set to 01. Sequential opera- tion allows the entire arra y to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x0000 (Figure 2-5, Figure 2-6).

2.3 Read Sequence

The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23LCV512 followed by the 16-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automati cally incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (FFFFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin.

2.4 Write Sequence

Prior to any attempt to write data to the 23LCV512, the device must be selected by bringing CS low. Once the device is select ed, the Write command can be started by issuing a WRITE instruction, followed by the 16-bit address and then the data to be written. A write is terminated by the CS being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. The internal Ad dress Pointer is automati- cally incremented. When the Address Pointer reaches the highest address (FFFFh), the address counter rolls over to (0000h). This allows the operation to continue indefinitely, however, previous data will be overwritten.

DS20005157B-page 8  2012-2021 Microchip Technology Inc. FIGURE 2-5: SEQUENTIAL RE AD SEQUENCE (SPI MODE) SI CS 9 1 01 1 2 12 22 32 42 52 62 72 82 93 0 31 15 14 13 12 210 76543210 Instruction 16-bit Address Page X, Word Y SCK 0 2345671 8 SO CS 76543210 Page X+1, Word 1 SCK 76543210 Page X+1, Word 0 76543210 Page X, Word 31 SO CS 76543210 Page X+n, Word 31 SCK 765432 1 0 Page X+n, Word 1 76543210 Page X+1, Word 31 SO SI SI 01000001

 2012-2021 Microchip Technology Inc. DS20005157B-page 9 23LCV512 FIGURE 2-6: SEQUENTIAL WR ITE SEQUENCE (SPI MODE) SI CS 9 1 01 1 2 12 22 32 42 52 62 72 82 93 0 31 00000001 15 14 13 12 210 76543210 Instruction 16-bit Address Data Byte 1 SCK 0 2345671 8 SI CS 41 42 43 46 47 76543210 Data Byte n SCK 32 34 35 36 37 38 3933 40 76543210 Data Byte 3 76543210 Data Byte 2 44 45

DS20005157B-page 10  2012-2021 Microchip Technology Inc.

2.5 Read Mode Register Instruction

(RDMR) The Read Mode Register instruction ( RDMR) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: TABLE 2-2: MODE REGISTER The mode bits indicate the operating mode of the SRAM. The possible modes of operation are: 0 0 = Byte mode 1 0 = Page mode 0 1 = Sequential mode (default operation) 1 1 = Reserved Bits 0 through 5 are reserved and should always be set to ‘0’. See Figure 2-7 for the RDMR timing sequence.FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE ( RDMR) 76 5 4 3 2 1 0 MODE MODE 00000 0 W/R = writable/readable SO SI CS 91 01 1 1 21 31 41 5 11000000 765 4 2 1 0 Instruction Data from MODE RegisterHigh-Impedance SCK 0 2345671 8

 2012-2021 Microchip Technology Inc. DS20005157B-page 11 23LCV512

2.6 Write Mode Register Instruction

(WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table 2-2. This allows for setting of the Device Operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure 2-8 for the WRMR timing sequence. FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE ( WRMR)

2.7 Power-On State

The 23LCV512 powers on in the following state:

• The device is in low-power Standby mode (CS = 1)
• A high-to-low-level transition on CS is required to enter active state SO SI CS 91 01 1 1 21 31 41 5 01000000 765 4 21 0 Instruction Data to MODE Register High-Impedance SCK 0 2345671 8

DS20005157B-page 12  2012-2021 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE

3.1 Chip Select (CS )

A low level on this pin sele cts the device. A high level deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the high- impedance state, allowing multiple parts to share the same SPI bus. After power-up, a low level on CS is required, prior to any sequence being initiated.

3.2 Serial Output (SO)

The SO pin is used to transfer data out of the 23LCV512. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.

3.3 Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock.

3.4 Serial Dual Interface Pins(SIO0,

SIO1) The SIO0 and SIO1 pins are used for SDI mode of operation. Functionality of these I/O pins is shared with SO and SI.

3.5 Serial Clock (SCK)

The SCK is used to synchronize the communication between a host and the 23LCV512. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

3.6 VBAT supply Input

The VBAT pin is used as an input for external backup supply to maintain SRAM data when V CC is below the VTRIP point. If the VBAT function is not being used, it is recommended to connect this pin to VSS.

3.7 SPI and SDI Pin Designations Name

SO/SIO1 2 Serial Data Output/SDI Pin NC 3 No Connect VSS 4G r o u n d SI/SIO0 5 Serial Da ta Input/SDI Pin SCK 6 Serial Clock Input VBAT 7 External Backup Supply VCC 8 Power Supply CS SIO1 NC Vss Vcc VBAT SCK SIO0 SDI Mode: CS SO NC Vss Vcc VBAT SCK SI SPI Mode:

 2012-2021 Microchip Technology Inc. DS20005157B-page 13 23LCV512

4.0 DUAL SERIAL MODE

The 23LCV512 also supports SDI (Serial Dual) mode of operation when used wit h compatible host devices. As a convention for SDI mode of operation, two bits are entered per clock using the SIO0 and SIO1 pins. Bits are clocked MSB first.

4.1 Dual Interface Mode

The 23LCV512 supports SDI (Serial Dual) mode of operation. To enter SDI mode the EDIO command must be clocked in (Figure 4-1). It should be noted that if the MCU resets before the SRAM, the user will need to determine the serial mode of operation of the SRAM and reset it accordingly. Byte read and write sequence in SDI mode is shown in Figure 4-2 and Figure 4-3. FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE FIGURE 4-2: BYTE READ MODE SDI SCK 0 2345671 SI High-Impedance SO CS 00 0111 1 1 Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. Note: The first byte read after the address will be a dummy byte. CS 91 0 1 1 12 13 14 15 16 17 18 1902 3 45 671 8 642014 12 10 8 753 115 13 11 9 16-Bit AddressInstruction Dummy Byte 642 0 753 1 Data Out SCK SIO0 SIO1 1000 0001

DS20005157B-page 14  2012-2021 Microchip Technology Inc. FIGURE 4-3: BYTE WRITE MODE SDI

4.2 Exit SDI Mode

To exit from SDI mode, the RSTIO command must be issued. The command must be entered in the current device configuration see (Figure 4-4). FIGURE 4-4: RESET SDI MODE (RSTIO) – FROM SDI MODE Note: Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high. CS 91 0 1 1 1 2 13 14 1502 3 4 5 6 71 8 642014 12 10 8 753 115 13 11 9 16-Bit AddressInstruction Data In 642 0 753 1 SCK SIO1 0000 0001 SIO0 SCK 0 2 31 SIO0 CS 1111 SIO1 1111

 2012-2021 Microchip Technology Inc. DS20005157B-page 15 23LCV512

5.0 VBAT

The 23LCV512 features an internal switch that will maintain the SRAM contents. In the event that the VCC supply is not available, the voltage applied to the VBAT pin serves as the backup supply. The V BAT trip point is the point at which the internal switch operates the device from the VBAT supply and is typically 1.8V (VTRIP specification D012). When V CC falls below the VTRIP point the system will continue to maintain the SRAM contents. The following conditions apply: Supply Condition Read/Write Access Powered By VCC < VTRIP No V BAT VCC > VTRIP, VCC < VBAT Yes V CC VCC > VTRIP, VCC > VBAT Yes V CC

DS20005157B-page 16  2012-2021 Microchip Technology Inc.

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

8-Lead SOIC (3.90 mm) XXXXYYWW XXXXXXXT NNN Example: SN 0528 23LCVAI 1L7 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead TSSOP Example: XXXX TYWW NNN 3LVA I837 1L7 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN YYWW 23LCV512 I/P 1L7 0528

 2012-2021 Microchip Technology Inc. DS20005157B-page 17 23LCV512 B A For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] eB E A L 8X b 8X b1 c C PLANE .010 C N D NOTE 1 TOP VIEW END VIEWSIDE VIEW e

DS20005157B-page 18  2012-2021 Microchip Technology Inc. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing eB -- . 4 3 0 BSC: Basic Dimension. Theoretically exact value shown without tolerances. protrusions shall not exceed .010" per side. Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or Pin 1 visual index feature may vary, but must be located within the hatched area. § Significant Characteristic Dimensioning and tolerancing per ASME Y14.5M e DATUM A DATUM A e b e b e ALTERNATE LEAD DESIGN (NOTE 5) 5. Lead design above seating plane may vary, based on assembly vendor.

 2012-2021 Microchip Technology Inc. DS20005157B-page 19 23LCV512

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H 0.23 (L1) L R0.13 R0.13 VIEW C SEE VIEW C NOTE 1 D

DS20005157B-page 20  2012-2021 Microchip Technology Inc. Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75--AOverall Height

1.27 BSCePitch

protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H.

 2012-2021 Microchip Technology Inc. DS20005157B-page 21 23LCV512 RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-SN Rev F BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

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 2012-2021 Microchip Technology Inc. DS20005157B-page 25 23LCV512 APPENDIX A: REVISION HISTORY Revision B (06/2021) Replaced “Master” and “Slave” terminology with “Host” and “Client”, respectively. Removed “Preliminary” sta- tus. Updated PDIP , SOIC and TSSOP package draw- ings. Revision A (09/2012) Initial release.

 2012-2021 Microchip Technology Inc. DS20005157B-page 26 23LCV512 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

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• Development Systems Information Line Customers should contac t their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support

 2012-2021 Microchip Technology Inc. DS20005157B-page 27 23LCV512 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options are shown below.. PART NO. X /XX PackageTape & ReelDevice Device: 23LCV512 = 512 Kbit, 2.5 - 5.5V, SPI Serial SRAM, V BAT Tape & Reel: Blank = Standard packaging (tube) Tape & Reel Temperature Range: I= - 4 0 C to+85C Package: SN = ST = Plastic SOIC (3.90 mm body), 8-lead Plastic TSSOP (4.4 mm body), 8-lead Plastic PDIP (300 mil body), 8-lead Examples: a) 23LCV512-I/ST = 512 Kbit, 2.5 - 5.5V Serial SRAM, Industrial temp., TSSOP package b) 23LCV512-I/SN = 512 Kbit, 2.5 - 5.5V Serial SRAM, Industrial temp., SOIC package c) 23LCV512-I/P = 512 Kbit, 2.5 - 5.5V Se rial SRA M, Industrial temp., PDIP package – X Temp Range

 2012-2021 Microchip Technology Inc. DS20005157B-page 28 Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Infor- mation regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ens ure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN- TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life sup- port and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectu al property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP , SimpliPHY , SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2021, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-8277-2 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications cont ained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished wit hout violating Microchip's intellectual property rights. Microchip is willing to work with any customer who is concerned about the integrity of its code.
• Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that w e are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted w ork, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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