23LC1024T-I/STVAO

23A1024_V01 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 33

Technical content

Features

• SPI Bus Interface: - SPI compatible - SDI (dual) and SQI (quad) compatible - 20 MHz Clock rate for all modes
• Low-Power CMOS Technology: - Read current: 3 mA at 5.5V, 20 MHz - Standby current: 4 A at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
• 128-Kbit x 8-bit Organization: - 32-byte page
• Byte, Page and Sequential Mode for Reads and Writes
• High Reliability
• Temperature Ranges Supported:
• Automotive AEC-Q100 Qualified
• RoHS Compliant Packages
• 8-Lead PDIP
• 8-Lead SOIC
• 8-Lead TSSOP Package Types (not to scale)

Description

The Microchip Technology Inc. 23A1024/23LC1024 are 1-Mbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK), a data in line (SI) and a data out line (SO). Access to the device is controlled through a Chip Select (CS ) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. Pin Function Table Part Number VCC Range Temp. Ranges Dual I/O (SDI) Quad I/O (SQI) Max. Clock Frequency Packages 23A1024 1.7V-2.2V I, E Yes Yes 20 MHz (1) SN, ST, P 23LC1024 2.5V-5.5V I, E Yes Yes 20 MHz (1) SN, ST, P Note 1: 16 MHz for E-temp. - Industrial (I): -40 Ct o + 8 5 C - Extended (E): -40 Ct o+ 1 2 5C CS SO/SIO1 SIO2 VSS VCC HOLD/SIO3 SCK SI/SIO0 SOIC/TSSOP/PDIP Name Function CS Chip Select Input Pin SO/SIO1 Serial Output/SDI/SQI Pin SIO2 SQI Pin V SS Ground Pin SI/SIO0 Serial Input/SDI/SQI Pin SCK Serial Clock Pin HOLD /SIO3 Hold/SQI Pin VCC Power Supply Pin 1-Mbit SPI Serial SRAM with SDI and SQI Interface

DS20005142D-page 2  2012-2022 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†) TABLE 1-1: DC CHARACTERISTICS † NOTICE: Stresses above those listed under “Absolute Maximu m Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. DC CHARACTERISTICS Industrial (I): T A = -40°C to +85°C Extended (E): T A = -40°C to +125°C Param. D001 V CC Supply Voltage 1.7 — 2.2 V 23A1024 2.5 5.5 V 23LC1024 D002 V IH High-level Input Voltage 0.7 VCC —V CC + 0.3 V D003 V IL Low-level Input Voltage -0.3 — 0.2 VCC V 23A1024

0.1 VCC V 23LC1024

D004 V OL Low-level Output Voltage ——0 . 2V I OL = 1 mA D005 V OH High-level Output Voltage VCC - 0.5 — — V I OH = -400 A D006 ILI Input Leakage Current —— ± 1 A CS = VCC, VIN = VSS OR VCC D007 ILO Output Leakage Current —— ± 1 A CS = VCC, VOUT = VSS OR VCC D008 I CC Read Operating Current — 11 0 m A F CLK = 20 MHz; SO = O, 2.2V 31 0 m A F CLK = 20 MHz; SO = O, 5.5V D009 ICCS Standby Current — 14 A CS = VCC = 2.2V, Inputs tied to VCC or VSS, I-Temp —1 2 A CS = VCC = 2.2V, Inputs tied to VCC or VSS, E-Temp 41 0 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, I-Temp —2 0 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, E-Temp D010 CINT Input Capacitance — — 7 pF VCC = 5.0V, f = 1 MHz, TA = 25°C (Note 1) D011 VDR RAM Data Retention Voltage —1 . 0 — V (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This is the limit to which VCC can be lowered without losing RAM data. This parameter is periodically sampled and not 100% tested. 3: Typical measurements taken at room temperature.

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 3 23A1024/23LC1024 TABLE 1-3: AC TEST CONDITIONS TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): T A = -40°C to +85°C Extended (E): T A = -40°C to +125°C Param. No. Sym. Characteristic Min. Max. Units Test Conditions 1F CLK Clock Frequency —

20 MHz I-Temp

16 MHz E-Temp

2 TCSS CS Setup Time

25 — ns I-Temp 32 — ns E-Temp

3 TCSH CS Hold Time 50 — ns

4 TCSD CS Disable Time

25 — ns I-Temp 32 — ns E-Temp 5T SU Data Setup Time 10 — ns 6T HD Data Hold Time 10 — ns 7T R CLK Rise Time — 20 ns (Note 1) 8T F CLK Fall Time — 20 ns (Note 1) 9T HI Clock High Time 25 — ns I-Temp 32 — ns E-Temp

10 T LO Clock Low Time

25 — ns I-Temp 32 — ns E-Temp

11 T CLD Clock Delay Time

25 — ns I-Temp 32 — ns E-Temp

12 T V Output Valid from Clock Low —

13 T HO Output Hold Time 0 — ns (Note 1)

14 T DIS Output Disable Time — 20 ns

15 THS HOLD Setup Time 10 — ns

16 THH HOLD Hold Time 10 — ns

17 THZ HOLD Low to Output High-Z 10 — ns

18 THV HOLD High to Output Valid — 50 ns

Note 1: This parameter is periodically sampled and not 100% tested. AC Waveform Input Pulse Level 0.1 V CC to 0.9 VCC Input Rise/Fall Time 5 ns CL = 30 pF — Timing Measurement Reference Level Input 0.5 V CC Output 0.5 V CC

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 5 23A1024/23LC1024

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 23A1024/23LC1024 is a 1-Mbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. In addition, the 23A1024/23LC1024 is capable of operation in SDI and SQI modes. In SDI mode, the SI and SO data lines are bidirectional, allowing the transfer of two bits per clock pulse. In SQI mode, two additional data lines enable the transfer of four bits per clock pulse. The 23A1024/23LC1024 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last.

2.2 Modes of Operation

The 23X1024 has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Burst. Byte Operation – is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/ write operations are limited to only one byte. The Command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks (Figure 2-1, Figure 2-2). Page Operation – is selected when bits 7 and 6 in the MODE register are set to 10. The 23X1024 has 4096 pages of 32 bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure 2-3, Figure 2-4). Sequential Operation – is selected when bits 7 and 6 in the MODE register are set to 01. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x00000 (Figure 2-5, Figure 2-6).

2.3 Read Sequence

The device is selected by pulling CS low. The 8-bit READ instruction is tran smitted to the 23A1024/ 23LC1024 followed by the 24-bit address, with the first seven MSB’s of the address being “don’t care” bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automati cally incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFFh), the address counter rolls over to address 00000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin.

2.4 Write Sequence

Prior to any attempt to write data to the 23A1024/ 23LC1024, the device must be selected by bringing CS low. Once the device is select ed, the Write command can be started by issuing a WRITE instruction, followed by the 24-bit address, with the first seven MSB’s of the address being “don’t care” bits, and then the data to be written. A write is terminated by the CS being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. The internal Address Pointer is automatically incremented. When the Address Pointer reaches the highest address (1FFFFh), the address counter rolls over to (00000h). This allows the operation to continue indef initely, however, previous data will be overwritten.

DS20005142D-page 8  2012-2022 Microchip Technology Inc. and its subsidiaries FIGURE 2-5: SEQUENTIAL RE AD SEQUENCE (SPI MODE) SI CS 9 1 01 1 2 93 03 13 23 33 43 53 63 73 8 39 23 22 21 20 210 76543210 Instruction 24-bit Address Page X, Word Y SCK 0 2345671 8 SO CS 76543210 Page X+1, Word 1 SCK 76543210 Page X+1, Word 0 76543210 Page X, Word 31 SO CS 76543210 Page X+n, Word 31 SCK 76543210 Page X+n, Word 1 76543210 Page X+1, Word 31 SO SI SI 01000001

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 9 23A1024/23LC1024 FIGURE 2-6: SEQUENTIAL WR ITE SEQUENCE (SPI MODE) SI CS 9 1 01 1 2 93 03 13 23 33 43 53 63 73 8 39 00000001 23 22 21 20 210 76543210 Instruction 24-bit Address Data Byte 1 SCK 0 2345671 8 SI CS 49 50 51 54 55 76543210 Data Byte n SCK 40 42 43 44 45 46 4741 48 76543210 Data Byte 3 76543210 Data Byte 2 52 53 SO High-Impedance SO High-Impedance

DS20005142D-page 10  2012-2022 Microchip Technology Inc. and its subsidiaries

2.5 Read Mode Register Instruction

(RDMR) The Read Mode Register instruction ( RDMR) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: TABLE 2-2: MODE REGISTER The mode bits indicate the operating mode of the SRAM. The possible modes of operation are: 0 0 = Byte mode 1 0 = Page mode 0 1 = Sequential mode (default operation) 1 1 = Reserved Bits 0 through 5 are reserved and should always be set to ‘0’. See Figure 2-7 for the RDMR timing sequence.FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE ( RDMR) 76 5 4 3 2 1 0 MODE MODE 00000 0 W/R = writable/readable SO SI CS 91 01 1 1 21 31 41 5 11000000 765 4 2 1 0 Instruction Data from MODE RegisterHigh-Impedance SCK 0 2345671 8

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 11 23A1024/23LC1024

2.6 Write Mode Register Instruction

(WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table 2-2. This allows for setting of the Device operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure 2-8 for the WRMR timing sequence. FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE ( WRMR)

2.7 Power-On State

The 23A1024/23LC1024 powers on in the following state:

• The device is in low-power Standby mode (CS = 1)
• A high-to-low-level transition on CS is required to enter active state SO SI CS 91 01 1 1 21 31 41 5 01000000 765 4 21 0 Instruction Data to MODE Register High-Impedance SCK 0 2345671 8

DS20005142D-page 12  2012-2022 Microchip Technology Inc. and its subsidiaries

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE FIGURE 3-1: SPI, SDI and SQI Pin Configurations

3.1 Chip Select (CS )

A low level on this pin sele cts the device. A high level deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the high- impedance state, allowing multiple parts to share the same SPI bus. After power-up, a low level on CS is required, prior to any sequence being initiated.

3.2 Serial Output, Serial I/O (SO/SIO1)

The SO/SIO1 pin is used to transfer data out of the 23A1024/23LC1024 when the SPI bus is being used. When in SDI or SQI bus modes, the SO/SIO1 pin is a bidirectional I/O pin. Data is shifted out on this pin after the falling edge of the serial clock, and it is latched in on the rising edge of the serial clock.

3.3 Serial I/O 2 (SIO2)

The SIO2 pin is a bidirectional I/O pin used only in SQI mode. If not using SQI bus mode, this pin should not be left floating. Deciding to pull the SIO2 pin high would allow successful recovery of the bus from SQI bus mode in case an accidental EQIO command has been registered.

3.4 Serial Input, Serial I/O 0 (SI/SIO0)

The SI pin is used to transfer data into the device when the SPI bus is being used. When in SDI or SQI bus modes, the SI/SIO0 pin is a bidirectional I/O pin.

3.5 Serial Clock (SCK)

The SCK is used to synchronize the communication between a host and the 23A1024/23LC1024. Instruc- tions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

3.6 Hold, Serial I/O 3 (HOLD /SIO3)

When the device is in SQI bus mode, pin HOLD/SIO3 is a bidirectional I/O pin. When in SPI or SDI bus modes, the pin has the HOLD function. The HOLD pin is used to suspend transmission to the 23A1024/23LC1024 while in the middle of a serial sequence without having to avoid retransmitting the entire sequence over again. It must be held high any time this function is not being used. Once the device is SOIC/PDIP/TSSOP Symbol Description 1C S Chip Select Input

2 SO/SIO1 Serial Output (SPI)/Serial I/O 1 (SDI)/Serial I/O 1 (SQI)

3 SIO2 Serial I/O 2 (SQI)

5 SI/SIO0 Serial Input (SPI)/Serial I/O 0 (SDI)/Serial I/O 0 (SQI)

6 SCK Serial Clock Input

7H OLD/SIO3 Hold/Serial I/O 3 8V CC Power Supply CS SIO1 NU Vss VCC HOLD SCK SIO0 SDI Mode: CS SIO1 SIO2 Vss VCC SIO3 SCK SIO0 SQI Mode: CS SO NU Vss VCC HOLD SCK SI SPI Mode: Note: Pin 3 is not used in SPI and SDI modes, and should not be left floating (see Section 3.3 “Serial I/O (SIO2)”).

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 13 23A1024/23LC1024 selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 23A1024/ 23LC1024 must remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD should be brought high while the SCK pin is low, otherwise serial communic ation will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to low transition of the HOLD pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK. Hold functionality is not available when operating in SQI bus mode.

DS20005142D-page 14  2012-2022 Microchip Technology Inc. and its subsidiaries

4.0 DUAL AND QUAD SERIAL

The 23A1024/23LC1024 also supports SDI (Serial Dual) and SQI (Serial Quad) mode of operation when used with compatible host devices. As a convention for SDI mode of operation, two bits are entered per clock using the SIO0 and SIO1 pins. Bits are clocked MSB first. For SQI mode of operation, four bits of data are entered per clock, or one nibble per clock. The nibbles are clocked MSB first.

4.1 Dual Interface Mode

The 23A1024/23LC1024 supports Serial Dual Input (SDI) mode of operation. To enter SDI mode the EDIO command must be clocked in (Figure 4-1). It should be noted that if the MCU resets before the SRAM, the user will need to determine the se rial mode of operation of the SRAM and reset it accordingly. Byte read and write sequence in SDI mode is shown in Figure 4-2 and Figure 4-3. FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE SCK 0 2345671 SI High-Impedance SO CS 00 0111 1 1

DS20005142D-page 16  2012-2022 Microchip Technology Inc. and its subsidiaries

4.2 Quad Interface Mode

In addition to the Serial Dual interface (SDI) mode of operation Serial Quad Interface (SQI) is also supported. In this mode the HOLD functionality is not available. To enter SQI mode the EQIO command must be clocked in (Figure 4-4). FIGURE 4-4: ENTER SQI MODE (EQIO) FROM SPI MODE FIGURE 4-5: BYTE READ MODE SQI SCK 0 2345671 SI High-Impedance SO CS 00 0111 0 0 Note 1: Page and Sequential mode is similar in that additional bytes can be clocked out before CS is brought high. 2: The first byte read after the address will be a dummy byte. CS SCK 0 2345671 8 9 1 0 4020 16 12 8SIO0 1 0 5121 17 13 9 0 0 6222 18 14 10 0 0 7323 19 15 11 SIO1 SIO2 SIO3 Instruction 24-Bit Address Dummy Byte 10 11 4 0 5 1 6 2 7 3 Data Out

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 17 23A1024/23LC1024 FIGURE 4-6: BYTE WRITE MODE SQI

4.3 Exit SDI or SQI Mode

To exit from SDI mode, the RSTIO command must be issued. The command must be entered in the current device configuration, either SDI or SQI, see Figure 4-7 and Figure 4-8. FIGURE 4-7: RESET SDI MODE (RSTIO) – FROM SDI MODE CS SCK 0 2345671 8 9 0 0 404020 16 12 8SIO0 1 0 515121 17 13 9 0 0 626222 18 14 10 0 0 737323 19 15 11 SIO1 SIO2 SIO3 Instruction 24-Bit Address Data In Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. SCK 02 3 1 SIO0 CS SIO1 1 1 11 1 1 1 1

DS20005142D-page 18  2012-2022 Microchip Technology Inc. and its subsidiaries FIGURE 4-8: RESET SDI/SQI MO DE (RSTIO) – FROM SQI MODE SCK 0 1 SIO0 SIO1 SIO2 SIO3 1 1 1 1 1 1 1 1 CS

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 19 23A1024/23LC1024

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

8-Lead SOIC (3.90 mm) XXXXYYWW XXXXXXXT NNN Example: SN 2205 23A1024I 13F Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) RoHS-compliant JEDEC ® designator for Matte Tin (Sn) Note: For very small packages with no r oom for the RoHS-compliant JEDEC ® designator , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead TSSOP Example: XXXT YYWW NNN 3ABI 2205 13F Part Number 1st Line Marking Codes PDIP SOIC TSSOP 23A1024 23A1024 23A1024T 3ABT 23LC1024 23LC1024 23LCBT 3LBT Note: T = Temperature grade (I, E) T/XXXNNN XXXXXXXX YYWW 8-Lead PDIP I/P 13F 23A1024 2205 Example:

DS20005142D-page 20  2012-2022 Microchip Technology Inc. and its subsidiaries B A For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing No. C04-018-P Rev F Sheet 1 of 2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] eB E A L 8X b 8X b1 c C PLANE .010 C N D NOTE 1 TOP VIEW END VIEWSIDE VIEW e

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 21 23A1024/23LC1024 Microchip Technology Drawing No. C04-018-P Rev F Sheet 2 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing eB - - .430 BSC: Basic Dimension. Theoretically exact value shown without tolerances. protrusions shall not exceed .010" per side. Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or Pin 1 visual index feature may vary, but must be located within the hatched area. § Significant Characteristic Dimensioning and tolerancing per ASME Y14.5M e DATUM A DATUM A e b e b e ALTERNATE LEAD DESIGN (NOTE 5) 5. Lead design above seating plane may vary, based on assembly vendor.

DS20005142D-page 22  2012-2022 Microchip Technology Inc. and its subsidiaries

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-SN Rev J Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H ș c 4X ș1 4X ș1 (L1) L R VIEW C SEE VIEW C NOTE 1 D

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 23 23A1024/23LC1024 Microchip Technology Drawing No. C04-057-SN Rev J Sheet 2 of 2 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: 5. Datums A & B to be determined at Datum H. Foot Angle 0° – 8° 8°–0°Lead Angle 0.51–0.31bLead Width 0.25–0.17cLead Thickness 1.27–0.40LFoot Length 0.50–0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25–0.10A1Standoff -–1.25A2Molded Package Thickness 1.75––AOverall Height

1.27 BSCePitch

Footprint L1 1.04 REF Mold Draft Angle 5° – 15° ș ––0.07R1Lead Bend Radius ––0.07RLead Bend Radius

DS20005142D-page 24  2012-2022 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-SN Rev J BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

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DS20005142D-page 28  2012-2022 Microchip Technology Inc. and its subsidiaries APPENDIX A: REVISION HISTORY Revision D (July 2022)

• Replaced terminology “Master” and “Slave” with “Host” and “Client” respectively.
• Updated PDIP, SOIC and TSSOP package draw- ings.
• Added Automotive Product Identification System. Revision C (January 2015)
• Updated Features section.
• Updated Description section.
• Updated Section 2.0, Functional Description.
• Updated Table 2-1.
• Updated Section 3.0, Pin Descriptions.
• Updated Table 3-1.
• Updated Section 4.0, Dual and Quad Serial Mode.
• Minor typographical corrections. Revision B (November 2013) Added E-temp specs. Revision A (July 2012) Initial release.

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 29 23A1024/23LC1024 THE MICROCHIP WEBSITE Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:

• Product Support – Data sheets and errata, appli- cation notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com . Under “Support”, click on “Cus- tomer Change Notification” and follow the registra- tion instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representa- tive or Field Application Engineer (FAE) for support. Local sales offices are also available to help custom- ers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support

DS20005142D-page 30  2012-2022 Microchip Technology Inc. and its subsidiaries PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTape and ReelDevice Device: 23A1024: 23LC1024: 1-Mbit, 1.7V - 2.2V, SPI Serial SRAM 1-Mbit, 2.5V - 5.5V, SPI Serial SRAM Tape and Reel: Blank = Standard packaging (tube) Tape and Reel(1) Temperature Range: -40C to +85C (Industrial) -40C to +125C (Extended) Package: P= SN = ST = Plastic PDIP (300 mil body), 8-lead Plastic SOIC (3.90 mm body), 8-lead Plastic TSSOP (4.4 mm body), 8-lead Examples: a) 23A1024-I/ST: 1-Mbit, 1.7V-2.2V Serial SRAM, Industrial temp., TSSOP package b) 23LC1024T-I/SN: 1-Mbit, 2.5V-5.5V Serial SRAM, Industrial temp., Tape and Reel, SOIC package c) 23LC1024-I/P: 1-Mbit, 2.5V-5.5V Serial SRAM, Industrial temp., PDIP package d) 23A1024-E/ST: 1-Mbit, 1.7V-2.2V Serial SRAM, Extended temp., TSSOP package e) 23LC1024T-E/SN: 1-Mbit, 2.5V-5.5V Serial SRAM, Extended temp., Tape and Reel, SOIC package f) 23LC1024-E/P: 1-Mbit, 2.5V-5.5V Serial SRAM, Extended temp., PDIP package Temperature Option Range Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for pack- age availability with the Tape and Reel option. (1)

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 31 23A1024/23LC1024 PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTape and ReelDevice Device: 23LC1024: 1-Mbit, 2.5V - 5.5V, SPI Serial SRAM Tape and Reel: Blank = Standard packaging (tube) Tape and Reel (1) Temperature Range: -40C to +85C (AEC-Q100 Grad e 3) -40C to +125C (AEC-Q100 Grade 1) Package: SN = ST = Plastic SOIC (3.90 mm body), 8-lead Plastic TSSOP (4.4 mm body), 8-lead Variant (2,3): VAO = VXX = Standard Automotive Customer Specific Automotive Examples: a) 23LC1024-I/SNVAO b) 23LC1024T-I/SNVAO c) 23LC1024T-E/SNVAO d) 23LC1024-E/STVAO Temperature Option Range XXX Variant Note 1: Tape and Reel identifier only ap pears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for pack- age availability with the Tape and Reel option. 2: The VAO/VXX automotive variants have been designed, manufactured, tested and qualified in accordance with AEC-Q100 requirements for automotive applications. 3: For customers requesting a PPAP , a customer-specific part number will be generated and provided. A PPAP is not provided for VAO part num- bers. (1)( 2,3)

 2012-2022 Microchip Technology Inc. and its subsidiaries DS20005142D-page 32 This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure t hat your applicatio n meets with your specifications. Contact your lo cal Microchip sales office for additional support or, obtain additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE , INCIDENTAL, OR CONSE- QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses ar e conveyed, implicitly or otherwise, under any Microchip intellectual pr operty rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In- Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2022, Microchip Technology Incorporated and its subsidiar- ies. All Rights Reserved. ISBN: 978-1-6683-0288-0 Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure w hen used in the intended manner, within operating specifications, and under n ormal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip produ ct is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that w e are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to cont inuously improving the code protection features of our products. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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