MX23L25611 MCNIX | Alldatasheet

Document overview

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Technical content

FEATURES

  • Bit organization - 32M x 8 (byte mode) - 16M x 16 (word mode)  Fast access time - Random access: 100ns (max.) - Page access: 30ns (max.)  Page Size - 8 words per page PIN CONFIGURATION

70 PIN SSOP

P/N:PM0822 REV. 1.3, NOV. 21, 2002 MX23L25611  Current - Operating: 30mA (max.) @ 5MHz - Standby: 15uA (max.)  Supply voltage - 3.0V ~ 3.6V  Package - 70 pin SSOP  Temperature - 0~70°C PIN DESCRIPTION Symbol Pin Function A0~A23 Address Inputs D0~D14 Data Outputs D15/A-1 D15 (Word Mode) / LSB Address (Byte Mode) CE# Chip Enable Input OE# Output Enable Input BYTE# Word/Byte Mode Selection VCC Power Supply Pin VSS Ground Pin NC No Connection 256M-BIT (16M x 16 / 32M x 8) MASK ROM WITH PAGE MODE (SSOP ONLY) MODE SELECTION CE# OE# BYTE# D15/A-1 D0~D7 D8~D15 Mode Power H X X X High Z High Z - Stand-by L H X X High Z High Z - Active L L H Output D0~D7 D8~D15 Word Active L L L Input D0~D7 High Z Byte Active A21 A20 A18 A17 NC NC NC NC NC NC NC NC NC NC CE# VSS VSS OE# D10 D11 VSS A19 A10 A11 A12 A13 A14 A15 A16 A23 BYTE# NC NC NC NC NC NC NC NC NC NC A22 VSS VSS D15 D14 D13 D12 VCC VCC MX23L25611

P/N:PM0822 REV. 1.3, NOV. 21, 2002 MX23L25611 ABSOLUTE MAXIMUM RATINGS Item Symbol Ratings Voltage on any Pin Relative to VSS VIN -0.3V to 3.9V Ambient Operating Temperature Topr 0 °C to 70°C Storage Temperature Tstg -65 °C to 125°C BLOCK DIAGRAM Address Buffer Memory Array Page Buffer Page Decoder Word/ Byte Output Buffer D15/(D7) A23 A0/(A-1) CE# BYTE# OE# ORDER INFORMATION Part No. Access Time Package VCC MX23L25611MC-10 100ns 70 pin SSOP 3.0V~3.6V (under development) MX23L25611MC-12 120ns 70 pin SSOP 3.0V~3.6V (under development)

P/N:PM0822 REV. 1.3, NOV. 21, 2002 MX23L25611 AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.0V ~ 3.6V) Item Symbol 23L25611-10 23L25611-12 MIN. MAX. MIN. MAX. Read Cycle Time tRC 100ns - 120ns - Address Access Time tAA - 100ns - 120ns Chip Enable Access Time tCE - 100ns - 120ns Page Mode Access Time tPA - 30ns - 30ns Output Enable Time tOE - 30ns 0 30ns Output Hold After Address tOH 0ns - 0ns - Output High Z Delay tHZ - 20ns - 20ns AC Test Conditions Input Pulse Levels 0.4V~ 2.4V Input Rise and Fall Times 10ns Input Timing Level 1.5V Output Timing Level 1.5V Output Load See Figure Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance. DOUT C< 100pFIOL (load)=1.6mA IOH (load)= -0.4mA DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.0V ~ 3.6V) Item Symbol MIN. MAX. Conditions Output High Voltage VOH 2.4V - IOH = -0.4mA Output Low Voltage VOL - 0.4V IOL = 1.6mA Input High Voltage VIH 2.2V VCC+0.3V Input Low Voltage VIL -0.3V 0.2xVCC Input Leakage Current ILI - 10uA 0V, VCC Output Leakage Current ILO - 10uA 0V, VCC Operating Current ICC - 30mA f=5MHz, all output open CE#=VIL(Chip Enable) OE#=VIH(Output Disabled) Standby Current (TTL) ISTB1 - 1mA CE# = VIH Standby Current (CMOS) ISTB2 - 15uA CE# > VCC-0.2V Input Capacitance CIN - 10pF Ta = 25 °C, f = 1MHZ Output Capacitance COUT - 10pF Ta = 25 °C, f = 1MHZ

P/N:PM0822 REV. 1.3, NOV. 21, 2002 MX23L25611 TIMING DIAGRAM RANDOM READ PAGE READ tCE tAA tOH tHZ ADD ADD ADDADD CE# OE# DATA VALID VALID VALID tRC tOE A3-A23 (A-1), A0, A1, A2 DATA VALID ADD VALID 1'st ADD 2'nd ADD tPAtAA 3'rd ADD VALID VALID

P/N:PM0822 REV. 1.3, NOV. 21, 2002 MX23L25611

PACKAGE INFORMATION

P/N:PM0822 REV. 1.3, NOV. 21, 2002 MX23L25611

REVISION HISTORY

Revision # Description Page Date 1.0 1. Changed heading as "RELIMINARY ” P1 SEP/06/2001 2. Modify Pin Configuration--Pin#6~15, Pin#24,25,68,69 P1 1.1 1. Modify Pin Configuration--Pin#10~14, 25,26 P1 SEP/07/2001 1.2 1. Modify Pin Configuration P1 FEB/01/2002 2. Modify Operating Current:60mA-->30mA; P1,2 Standby Currrent(CMOS):50uA-->15uA 3. Modify MODE SELECTION P1 4. Add 120ns in AC Characteristics P3 5. Add Order Informaion P2 6. Modify 70 pin SOP --> 70 pin SSOP P1,2,5

1.3 Modify Package Information P5 NOV/21/2002

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