IDT2309A RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: mamiller
  • PDF pages: 9

Technical content

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER AUGUST 2012 2012 Integrated Device Technology, Inc. DSC - 6588/5c COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEATURES:

  • Phase-Lock Loop Clock Distribution
  • 10MHz to 133MHz operating frequency
  • Distributes one clock input to one bank of five and one bank of four outputs
  • Separate output enable for each output bank
  • Output Skew < 250ps
  • Low jitter <200 ps cycle-to-cycle
  • IDT2309A-1 for Standard Drive
  • IDT2309A-1H for High Drive
  • No external RC network required
  • Operates at 3.3V V DD
  • Available in SOIC and TSSOP packages IDT2309A3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309A enters power down. In this mode, the device will draw less than 12µA for Commercial Temperature range and less than 25µA for Industrial temperature range, and the outputs are tri-stated. The IDT2309A is characterized for both Industrial and Commercial operation. PLL CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Control Logic REF

16 CLKOUT

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION SOIC/ TSSOP TOP VIEW Symbol Rating Max. Unit VDD Supply Voltage Range –0.5 to +4.6 V VI (2) Input Voltage Range (REF) –0.5 to +5.5 V VI Input Voltage Range –0.5 to V (except REF) VDD+0.5 IIK (VI < 0) Input Clamp Current –50 mA IO (VO = 0 to VDD) Continuous Output Current ±50 mA VDD or GND Continuous Current ±100 mA TA = 55°C Maximum Power Dissipation 0.7 W (in still air)(3) TSTG Storage Temperature Range –65 to +150 °C Operating Commercial Temperature 0 to +70 ° C Temperature Range Operating Industrial Temperature -40 to +85 °C Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. NOTES: 1. Weak pull down on all outputs. 2. Weak pull ups on these inputs. PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS(1) Pin Name Pin Number Type Functional Description REF 1 IN Input reference clock, 5 Volt tolerant input CLKA1(1) 2 Out Output clock for bank A CLKA2(1) 3 Out Output clock for bank A VDD 4, 13 PWR 3.3V Supply GND 5, 12 GND Ground CLKB1(1) 6 Out Output clock for bank B CLKB2(1) 7 Out Output clock for bank B S2(2) 8 IN Select input Bit 2 S1(2) 9 IN Select input Bit 1 CLKB3(1) 10 Out Output clock for bank B CLKB4(1) 11 Out Output clock for bank B CLKA3(1) 14 Out Output clock for bank A CLKA4(1) 15 Out Output clock for bank A CLKOUT (1) 16 Out Output clock, internal feedback on this pin APPLICATIONS:

  • SDRAM  Telecom  Datacom  PC Motherboards/Workstations  Critical Path Delay Designs REF CLKA1 8 9 161 CLKA2 GND CLKB1 CLKOUT CLKA4 GND VDDVDD CLKB2 CLKB3 CLKB4 CLKA3

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter Conditions Min. Max. Unit VIL Input LOW Voltage Level — 0.8 V VIH Input HIGH Voltage Level 2 — V IIL Input LOW Current V IN = 0V — 50 µA IIH Input HIGH Current V IN = VDD — 100 µA VOL Output LOW Voltage Standard Drive I OL = 8mA — 0.4 V High Drive I OL = 12mA (-1H) VOH Output HIGH Voltage Standard Drive I OH = -8mA 2.4 — V High Drive I OH = -12mA (-1H) IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — 12 µA IDD Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 32 mA SWITCHING CHARACTERISTICS (2309A-1) - COMMERCIAL(1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t 2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge (2) Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge (2) Measured at VDD/2 in PLL bypass mode (IDT2309A only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs. Symbol Parameter Min. Max. Unit VDD Supply Voltage 3 3.6 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 CIN Input Capacitance — 7 pF OPERATING CONDITIONS - COMMERCIAL FUNCTION TABLE(1) S2 S1 CLKA CLKB CLKOUT (2) Output Source PLL Shut Down L L Tri-State Tri-State Driven PLL N L H Driven Tri-State Driven PLL N H L Driven Driven Driven REF Y H H Driven Driven Driven PLL N NOTES: 1. H = HIGH Voltage Level. L = LOW Voltage Level 2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew bet ween the REF and the output.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2309A-1H) - COMMERCIAL(1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, F OUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at V DD/2 in PLL bypass mode (IDT2309A only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs. DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL Symbol Parameter Conditions Min. Max. Unit VIL Input LOW Voltage Level — 0.8 V VIH Input HIGH Voltage Level 2 — V IIL Input LOW Current V IN = 0V — 50 µA IIH Input HIGH Current V IN = VDD — 100 µA VOL Output LOW Voltage Standard Drive I OL = 8mA — 0.4 V High Drive I OL = 12mA (-1H) VOH Output HIGH Voltage Standard Drive I OH = -8mA 2.4 — V High Drive I OH = -12mA (-1H) IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — 25 µA IDD Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 35 mA Symbol Parameter Min. Max. Unit VDD Supply Voltage 3 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 CIN Input Capacitance — 7 pF OPERATING CONDITIONS - INDUSTRIAL

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER SWITCHING CHARACTERISTICS (2309A-1H) - INDUSTRIAL(1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t 2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t 2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at V DD/2 in PLL bypass mode (IDT2309A only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit 2 1 — — V/ns tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs. SWITCHING CHARACTERISTICS (2309A-1) - INDUSTRIAL(1,2) Symbol Parameter Conditions Min. Typ. Max. Unit t1 Output Frequency 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t 2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at V DD/2 in PLL bypass mode (IDT2309A only) 1 5 8.7 ns t7 Device-to-Device Skew Measured at V DD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms NOTES: 1. REF Input has a threshold voltage of V DD/2. 2. All parameters specified with loaded outputs.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER Output 1.4V 1.4V Output REF VDD/2 Output CLKOUT Device 1 CLKOUT Device 2 VDD/2 VDD/2 VDD/2 1.4V1.4V 1.4V 2V0.8V t3 t4 0.8V 3.3V 2VOutput ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for th e PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay. For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs m ust be loaded equally. All Outputs Rise/Fall Time Input to Output Propagation Delay Device to Device Skew Output to Output SkewDuty Cycle Timing SWITCHING WAVEFORMS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER VDD OUTPUTS CLKOUT CLOAD VDD GND GND 0.1 F 0.1 F VDD OUTPUTS 10pF VDD GND GND 0.1 F 0.1 F 1K CLKOUT Test Circuit 1 (all Parameters Except t8) Test Circuit 2 (t8, Output Slew Rate On -1H Devices) TEST CIRCUITS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2309A 3.3V ZERO DELAY CLOCK BUFFER

ORDERING INFORMATION

Ordering Code Package Type Operating Range 2309A-1DCG 16-Pin SOIC Commercial 2309A-1DCGI 16-Pin SOIC Industrial 2309A-1HDCG 16-Pin SOIC Commercial 2309A-1HDCGI 16-Pin SOIC Industrial 2309A-1HPGG 16-Pin TSSOP Commercial 2309A-1HPGGI 16-Pin TSSOP Industrial IDT XXXXX XX X Package ProcessDevice Type Blank I 2309A-1 2309A-1H Commercial (0 oC to +70oC) Industrial (-40oC to +85oC) Zero Delay Clock Buffer with High Drive Small Outline IC SOIC - Green Thin Shrink Small Outline Package TSSOP - Green DC DCG PG PGG

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.