22CV10A-7 ANACHIP | Alldatasheet
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Technical content
Features
- Speeds ranging from 7ns to 25ns - Power as low as 30mA at 25MHz Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development/Programmer Support - Third party software and programmers - Anachip PLACE Development Software General Description The PEEL™22CV10A is a Programmable Electrically Eras- able Logic (PEEL™) device providing an attractive alterna- tive to ordinary PLDs. The PEEL™22CV10A offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 1), with speeds ranging from 7ns to 25ns and with power consumption as low as 30mA. EE-reprogrammability provides the conve- nience of instant reprogramming for development and a reusable production inventory, minimizing the impact of programming changes or errors. EE-reprogrammability Architectural Flexibility - 132 product term X 44 input AND array - Up to 22 inputs and 10 outputs - Up to 12 configurations per macrocell - Synchronous preset, asynchronous clear - Independent output enables - 24-pin DIP/SOIC/TSSOP and 28-pin PLCC Application Versatility - Replaces random logic - Pin and JEDEC compatible with 22V10 - Enhanced Architecture fits more logic than ordinary PLDs also improves factory testability, thus ensuring the highest quality possible. The PEEL™22CV10A is JEDEC file com- patible with standard 22V10 PLDs. Eight additional configu- rations per macrocell (a total of 12) are also available by using the “+” software/programming option (i.e., 22CV10A+ & 22CV10A++). The additional macrocell configurations allow more logic to be put into every design. Programming and development support for the PEEL™22CV10A are pro- vided by popular third-party programmers and develop- ment software. Anachip also offers free PLACE development software.
Figure 1. Pin Configuration Figure 2. Block Diagram
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
Anachip Corp.
Anachip Corp. Function Description The PEEL™22CV10A implements logic functions as sum- of-products expressions in a programmable-AND/ fixed-OR logic array. User-defined functions are created by program- ming the connections of input signals into the array. User- configurable output structures in the form of I/O macrocells further increase logic flexibility. Architecture Overview The PEEL™22CV10A architecture is illustrated in the block diagram of Figure 2. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable elec- trically-erasable AND array which drives a fixed OR array. With this structure, the PEEL™22CV10A can implement up to 10 sum-of-products logic expressions. Associated with each of the 10 OR functions is an I/O mac- rocell which can be independently programmed to one of 4 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions with either active-high or active-low polarity. AND/OR Logic Array The programmable AND array of the PEEL™22CV10A (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
44 Input Lines:
24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os 132 product terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14 and 16) used to form logical sums 10 output enable terms (one for each I/O) 1 global synchronous present term 1 global asynchronous clear term At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each prod- uct term is essentially a 44-input AND gate. A product term which is connected to both the true and complement of an input signal will always be FALSE, and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a “don’t care” state exists and that term will always be TRUE. When programming the PEEL™22CV10A, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is then configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL™ device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.) Variable Product Term Distribution The PEEL™22CV10A provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14 and 16 to form logical sums (see Figure 3). This distribution allows opti- mum use of device re-sources. Programmable I/O Macrocell The output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configura- tion of the PEEL™22CV10A to the precise requirements of their designs. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a D- type flip-flop and two signal-select multiplexers. The config- uration of each macrocell is determined by the two EEPROM bits controlling these multiplexers (refer to Table 1). These bits determine output polarity and output type (registered or non-registered). Equivalent circuits for the four macro-cell configurations are illustrated in Figure 5. Output Type The signal from the OR array can be fed directly to the out- put pin (combinatorial function) or latched in the D-type flip- flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Output Polarity Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters. Output Enable The output of each I/O macrocell can be enabled or dis- abled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is driven into the high-impedance state. Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bi- directional I/O. Opening every connection on the output
Figure 5. Four Configurations of the PEEL™22CV10A I/O Macrocell Table 1. PEEL™ 22CV10A Macrocell Configuration Bits
Figure 6. Twelve Configurations of the PEEL™22CV10A+ and PEEL22CV10A++ I/O Macrocell Table 2. PEEL™ 22CV10A+ & A++ Macrocell Configuration Bits
Table 6. Absolute Maximum Ratings Table 7. Operating Ranges Table 8. D.C. Electrical Characteristics over the recommended operating conditions
Table 9. A.C. Electrical Characteristics
- Test conditions assume: signal transition times of 3ns or less from the
- Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for
- VI and VO are not specified for program/verify operation.
- Test points for Clock and VCC in tR, tF are referenced at 10% and 90%
- “Input” refers to an Input pin signal.
- tOE is measured from input transition to VREF ± 0.1V, tOD is measured from
- Capacitances are tested on a sample basis.
- Test one output at a time for a duration of less than 1sec.
- ICC for a typical application: This parameter is tested with the device
programmed as an 8-bit Counter.
- PEEL™ Device test loads are specified in Section 6 of this Data Book.
- Parameters are not 100% tested. Specifications are based on initial
tion which may affect operational frequency.
- Available only for 22CV10A -15/I-15/-25/I-25 grades.
Table 6. Ordering Information
Anachip Corp. Part Number PEELTM22CV10A PI-25X Package P = Plastic 300 mil DIP S = SOIC Temperature Range andowe Options (Blank) = Commercial 0 to 70oC Speed Lead Free Blank : Normal L : Lead Free Package J = Plastic (J) Leaded Chip Carrier (PLCC) SuffixDevice T = TSSOP I = Industrial -40 to +85oC -7 = 7.5ns tpd -10 = 10ns tpd -15 = 15ns tpd -25 = 25ns tpd Anachip Corp. Head Office , Anachip USA 2F, No. 24-2, Industry E. Rd. IV, Science-Based 780 Montague Expressway, #201 Industrial Park, Hsinchu, 300, Taiwan San Jose, CA 95131 Tel: +886-3-5678234 Tel: (408) 321-9600 Fax: +886-3-5678368 Fax: (408) 321-9696 Email: sales_usa@anachip.com Website: http://www.anachip.com ©2004 Anachip Corp. Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life support devices or systems. Marks bearing © or ™ are registered trademar ks and trademarks of Anachip Corp.