2184

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADSP-2184 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 DSP Microcomputer FUNCTIONAL BLOCK DIAGRAMFEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 20K Bytes of On-Chip RAM, Configured as 4K Words On-Chip Program Memory RAM and 4K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable)

4 MByte Byte Memory Interface for Storage of Data

Tables and Program Overlays (Made Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design (Mode Selectable) Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

UART Emulation through Software SPORT Reconfiguration ICE-Port™ Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION The ADSP-2184 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2184 combines the ADSP-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2184 integrates 20K bytes of on-chip memory con- figured as 4K words (24-bit) of program RAM and 4K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment. The ADSP-2184 is available in 100-lead LQFP package. In addition, the ADSP-2184 supports instructions that include bit manipulations—bit set, bit clear, bit toggle, bit test— ALU constants, multiplication instruction (x squared), biased round- ing, result free ALU operations, I/O memory transfers, and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2184 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. ICE-Port is a trademark of Analog Devices, Inc. All trademarks are the property of their respective holders. SERIAL PORTS SPORT 1SPORT 0 MEMORY PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER 4K 3 24 PROGRAM MEMORY 4K 3 16 DATA MEMORY TIMER ADSP-2100 BASE ARCHITECTURE SHIFTERMACALU ARITHMETIC UNITS POWER-DOWN CONTROL PROGRAM SEQUENCER DAG 2DAG 1 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS EXTERNAL ADDRESS BUS INTERNAL DMA PORT EXTERNAL DATA BUS OR FULL MEMORY MODE HOST MODE

–3–REV. 0 The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. The sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2184 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and pro- gram memory. Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four pos- sible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses:

• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permit- ting the ADSP-2184 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP- 2184 can fetch an operand from program memory and the next instruction in the same cycle. When configured in host mode, the ADSP-2184 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH and BG). One execution mode (Go Mode) allows the ADSP-2184 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2184 can respond to eleven interrupts. There are up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2184 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-2184 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2184 SPORTs. For additional information on Serial Ports, refer to the ADSP- 2100 Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, double-buff- ered transmit and receive section.
• SPORTs can use an external serial clock or generate their own serial clock internally.
• SPORTs have independent framing for the receive and trans- mit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and m-law companding according to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream.
• SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. PIN DESCRIPTIONS The ADSP-2184 is available in a 100-lead LQFP package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, inter- rupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execu- tion. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is re- configurable, the default state is shown in plain text; alternate functionality is shown in italics.

–4– REV. 0 Common-Mode Pins # Input/ Pin of Out- Name(s) Pins put Function RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1 O Program Memory Select Output IOMS 1 O I/O Memory Select Output BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output IRQ2/ 1 I Edge- or Level-Sensitive Interrupt Request 1 PF7 I/O Programmable I/O Pin IRQL0/ 1 I Level-Sensitive Interrupt Requests 1 PF5 I/O Programmable I/O Pin IRQL1/ 1 I Level-Sensitive Interrupt Requests 1 PF6 I/O Programmable I/O Pin IRQE/ 1 I Edge-Sensitive Interrupt Requests 1 PF4 I/O Programmable I/O Pin PF3 1 I/O Programmable I/O Pin Mode C/ 1 I Mode Select Input—Checked only During RESET PF2 I/O Programmable I/O Pin During Normal Operation Mode B/ 1 I Mode Select Input—Checked only During RESET PF1 I/O Programmable I/O Pin During Normal Operation Mode A/ 1 I Mode Select Input—Checked only During RESET PF0 I/O Programmable I/O Pin During Normal Operation CLKIN, XTAL 2 I Clock or Quartz Crystal Input CLKOUT 1 O Processor Clock Output SPORT0 5 I/O Serial Port I/O Pins SPORT1/ 5 I/O Serial Port I/O Pins IRQ1:0 Edge- or Level-Sensitive Interrupts, FI, FO Flag In, Flag Out PWD 1 I Power-Down Control Input PWDACK 1 O Power-Down Control Output FL0, FL1, FL2 3 O Output Flags V DD and GND 16 I Power and Ground EZ-Port 9 I/O For Emulation Use NOTES 1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2184 processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. Full Memory Mode Pins (Mode C = 0) of Input/ Pin Name Pins Output Function A13:0 14 O Address Output Pins for Pro- gram, Data, Byte and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte and I/O Spaces (8 MSBs Are Also Used as Byte Memory Addresses) Host Mode Pins (Mode C = 1) of Input/ Pin Name Pins Output Function IAD15:0 16 I/O IDMA Port Address/Data Bus A0 1 O Address Pin for External I/O, Program, Data, or Byte Access D23:8 16 I/O Data I/O Pins for Program, Data Byte and I/O Spaces IWR 1 I IDMA Write Enable IRD 1 I IDMA Read Enable IAL 1 I IDMA Address Latch Pin IS 1 I IDMA Select IACK 1 O IDMA Port Acknowledge In Host Mode, external peripheral addresses can be decoded using the A0, BMS, CMS, PMS, DMS, and IOMS signals. Setting Memory Mode Memory Mode selection for the ADSP-2184 is made during chip reset through the use of the Mode C pin. This pin is multi- plexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are passive and active. Passive configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 100 kW , can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. Active configuration involves the use of a three-stateable exter- nal driver connected to the Mode C pin. A driver’s output en- able should be connected to the DSP’s RESET signal such that it only drives the PF2 pin when RESET is active (low). After RESET is deasserted, the driver should three-state, thus allow- ing full use of the PF2 pin as either an input or output.

–5–REV. 0 To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. This ensures that the pin will be held at a constant level and not oscillate should the three-state driver’s level hover around the logic switching point. Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2184 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP-2184 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software and the power-down control circuit. The inter- rupt levels are internally prioritized and individually maskable (except power-down and RESET). The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table I. Table I. Interrupt Priority & Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power-Down (Nonmaskable) 002C IRQ2 0004 IRQL1 0008 IRQL0 000C SPORT0 Transmit 0010 SPORT0 Receive 0014 IRQE 0018 BDMA Interrupt 001C SPORT1 Transmit or IRQ1 0020 SPORT1 Receive or IRQ0 0024 Timer 0028 (Lowest Priority) Interrupt routines can either be nested, with higher priority interrupts taking precedence, or processed sequentially. Inter- rupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2184 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nest- ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level-sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automati- cally maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. The following instructions allow global enable or disable servic- ing of the interrupts (including power-down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. ENA INTS; DIS INTS; When the processor is reset, interrupt servicing is enabled. LOW POWER OPERATION The ADSP-2184 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are:

• Power-Down
• Idle
• Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down The ADSP-2184 processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. Following is a brief list of power-down features. Refer to the ADSP-2100 Family User’s Manual, Third Edition, “System Interface” chapter, for detailed information about the power-down feature.
• Quick recovery from power-down. The processor begins executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS proces- sor clock. The external clock can continue running during power-down without affecting the lowest power rating and 200 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approxi- mately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start-up.
• Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit.
• Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power- down interrupt also can be used as a nonmaskable, edge- sensitive interrupt.
• Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor has entered power-down.

continues with the instruction following the IDLE instruction. divisor is given, is the standard IDLE instruction. or 128) before resuming normal operation. may be faster than the processor’s reduced internal clock rate. external program and data overlay memories (mode selectable). generate and latch address signals.

2048 LOCATIONS

Figure 2. Basic System Configuration

information on this power-down feature. is used, the XTAL input must be left unconnected. indicated by the CLKOUT signal when enabled. sor-grade crystal should be used. Figure 3. External Crystal Connections The RESET signal initiates a master reset of the ADSP-2184. clock continues to run and does not require stabilization time.

2000 CLKIN cycles ensures that the PLL has locked, but does

an external Schmidt trigger is recommended. tion, see Designing an EZ-ICE-Compatible Systems section. Data Memory, Byte Memory and I/O. can be read from on-chip program memory in a single cycle. external memory overlay spaces through the external data bus. 8-bit wide memory space through the Byte DMA (BDMA) port. memory by utilizing eight data lines as additional address lines. external registers or latches. The ADSP-2184 contains 4K · 24 of on-chip program RAM. organized as shown in Figure 4. Figure 4. Program Memory (Mode B = 0)

generated as shown in Table II.

0 Internal Not Applicable Not Applicable

1 External 13 LSBs of Address

2 External 13 LSBs of Address

B = 1. Figure 5 shows the memory map in this configuration. Figure 5. Program Memory (Mode B = 1) overlays. Figure 6 shows the organization of the data memory.

32 MEMORY–

Figure 6. Data Memory 2, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III. states specified by the DWAIT register. nections to peripherals or to bus interface ASIC data registers. act on address ranges as shown in Table IV.

–9–REV. 0 Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K · 8. The byte memory space on the ADSP-2184 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg · 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA, Full Memory Mode) The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses is done from the byte memory space to build the word size selected. Table V shows the data formats sup- ported by the BDMA circuit. Table V. Internal BTYPE Memory Space Word Size Alignment

00 Program Memory 24 Full Word

01 Data Memory 16 Full Word

10 Data Memory 8 MSBs

11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. The 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is gener- ated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of the values of Mode B, PMOVLAY or DMOVLAY. When the BWCOUNT register is written with a nonzero value, the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue opera- tions. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor and start execution at address 0 when the BDMA accesses have completed. Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2184. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’s memory- mapped control registers. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is com- pletely asynchronous and can be written to while the ADSP- 2184 is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This in- creases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal ( IS) latches this value into the IDMAA register. Once the address is stored, data can then either be read from or written to the ADSP-2184’s on-chip memory. Asserting the select line (IS) and the appropriate read or write line ( IRD and IWR respectively) signals the ADSP-2184 that a particular transaction is required. In either case, there is a one-processor- cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automati- cally incremented and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation.

–10– REV. 0 Bootstrap Loading (Booting) The ADSP-2184 has two mechanisms to allow automatic load- ing of the internal program memory after reset. The method for booting is controlled by the Mode A, B and C configuration bits as shown in Table VI. These four states can be compressed into two-state bits by allowing an IDMA boot with Mode C = 1. However, three bits are used to ensure future compatibility with parts containing internal program memory ROM. BDMA Booting When the MODE pins specify BDMA booting, the ADSP-2184 initiates a BDMA boot sequence when RESET is released. Table VI. Boot Summary Table MODE C MODE B MODE A Booting Method 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is config- ured in Full Memory Mode. 0 1 0 No Automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used but the pro- cessor does not automatically use or wait for these operations. 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is config- ured in Host Mode. Additional interface hardware is required. 1 0 1 IDMA feature is used to load any internal memory as de- sired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. The BDMA interface is set up during reset to the following de- faults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0; the BTYPE register is set to 0 to specify program memory 24-bit words; and the BWCOUNT register is set to 32. This causes 32 words of on- chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes pro- gram execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the ad- dresses to boot memory must be constructed externally to the ADSP-2184. The only memory address bit provided by the processor is A0. IDMA Port Booting The ADSP-2184 can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-2184 boots from the IDMA port. The IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to. Bus Request and Bus Grant The ADSP-2184 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request ( BR) signal. If the ADSP-2184 is not performing an external memory access, it responds to the active BR input in the following processor cycle by:

• Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant ( BG) signal, and
• Halting program execution. If Go Mode is enabled, the ADSP-2184 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2184 is performing an external memory access when the external device asserts the BR signal, it will not three- state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2184 is ready to execute an instruction but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2184 deasserts BG and BGH and executes the external memory access. Flag I/O Pins The ADSP-2184 has eight general purpose programmable input/ output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2184’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset.

Figure 8. Target Board Connector for EZ-ICE access timing requirements and switching characteristics. your option when the EZ-ICE is not being used.

• EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal.
• EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal.
• EZ-ICE emulation ignores RESET and BR when single- stepping.
• EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP’s external memory bus only if bus grant (BG) is asserted by the EZ-ICE board’s DSP.

–13– ADSP-2184 REV. 0 RECOMMENDED OPERATING CONDITIONS B Grade Parameter Min Max Unit VDD 4.5 5.5 V TAMB –40 +85 °C

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Typ Max Unit VIH Hi-Level Input Voltage 1, 2 @ VDD = max 2.0 V VIH Hi-Level CLKIN Voltage @ V DD = max 2.2 V VIL Lo-Level Input Voltage 1, 3 @ VDD = min 0.8 V VOH Hi-Level Output Voltage1, 4, 5 @ VDD = min IOH = –0.5 mA 2.4 V @ VDD = min IOH = –100 mA6 VDD – 0.3 V VOL Lo-Level Output Voltage1, 4, 5 @ VDD = min IOL = 2 mA 0.4 V IIH Hi-Level Input Current 3 @ VDD = max VIN = VDD max 10 mA IIL Lo-Level Input Current 3 @ VDD = max VIN = 0 V 10 mA IOZH Three-State Leakage Current 7 @ VDD = max VIN = VDD max8 10 mA IOZL Three-State Leakage Current 7 @ VDD = max VIN = 0 V8, tCK = 25 ns 10 mA IDD Supply Current (Idle)9 @ VDD = 5.0 14 mA IDD Supply Current (Dynamic) 10, 11 @ VDD = 5.0 TAMB = +25°C tCK = 25 ns 60 mA CI Input Pin Capacitance3, 6, 12 @ VIN = 2.5 V, fIN = 1.0 MHz, 8 pF TAMB = +25°C CO Output Pin Capacitance 6, 7, 12, 13 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C8 p F NOTES 1 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all ADSP-2184 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7. 8 0 V on BR. 9 Idle refers to ADSP-2184 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 12 Applies to LQFP package type. 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. SPECIFICATIONS

–14– REV. 0 ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2184 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS* Operating Temperature Range (Ambient) . . –40 °C to +85°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TIMING PARAMETERS GENERAL NOTES Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. TIMING NOTES Switching characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the proces- sor operates correctly with other devices. MEMORY TIMING SPECIFICATIONS The table below shows common memory device specifications and the corresponding ADSP-2184 timing parameters, for your convenience. Memory ADSP-2184 Timing Device Timing Parameter Specification Parameter Definition Address Setup to t ASW A0–A13, xMS Setup Write Start before WR Low Address Setup to t AW A0–A13, xMS Setup Write End before WR Deasserted Address Hold Time t WRA A0–A13, xMS Hold before WR Low Data Setup Time t DW Data Setup before WR High Data Hold Time t DH Data Hold after WR High OE to Data Valid t RDD RD Low to Data Valid Address Access Time t AA A0–A13, xMS to Data Valid xMS = PMS, DMS, BMS, CMS, IOMS. FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tCK is defined as 0.5 t CKI. The ADSP-2184 uses an input clock with a frequency equal to half the instruction rate: a 20 MHz input clock (which is equivalent to 50 ns) yields a 25 ns proces- sor cycle (equivalent to 40 MHz). t CK values within the range of 0.5 tCKI period should be substituted for all relevant timing para- meters to obtain the specification value. Example: tCKH = 0.5 tCK – 7 ns = 0.5 (25 ns) – 7 ns = 5.5 ns WARNING! ESD SENSITIVE DEVICE

Figure 9. Clock Signals

–16– REV. 0 TIMING PARAMETERS Parameter Min Max Unit Interrupts and Flag Timing Requirements : tIFS IRQx, FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4 0.25 tCK + 15 ns tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25 tCK ns Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 0.25 tCK – 7 ns tFOD Flag Output Delay from CLKOUT Low5 0.5 tCK + 6 ns NOTES 1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information on interrupt servicing.) 2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. 4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5Flag outputs = PFx, FL0, FL1, FL2, Flag_out. tFOD tFOH tIFH tIFS CLKOUT FLAG OUTPUTS IRQx FI PFx Figure 10.␣ Interrupts and Flags

–17–REV. 0 Parameter Min Max Unit Bus Request–Bus Grant Timing Requirements : tBH BR Hold after CLKOUT High 1 0.25 tCK + 2 ns tBS BR Setup before CLKOUT Low 1 0.25 tCK + 17 ns Switching Characteristics : tSD CLKOUT High to xMS, RD, WR Disable 0.25 t CK + 10 ns tSDB xMS, RD, WR Disable to BG Low 0 ns tSE BG High to xMS, RD, WR Enable 0 ns tSEC xMS, RD, WR Enable to CLKOUT High 0.25 t CK – 7 ns tSDBH xMS, RD, WR Disable to BGH Low2 0n s tSEH BGH High to xMS, RD, WR Enable2 0n s NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recogniz ed on the following cycle. Refer to the ADSP-2100 Family User’s Manual , Third Edition, for BR/BG cycle relationships. 2BGH is asserted when the bus is granted and the processor requires control of the bus to continue. CLKOUT tSD tSDB tSE tSEC tSDBH tSEH tBS BR tBH CLKOUT PMS, DMS BMS, RD WR BG BGH Figure 11.␣ Bus Request–Bus Grant

–18– REV. 0 TIMING PARAMETERS Parameter Min Max Unit Memory Read Timing Requirements : tRDD RD Low to Data Valid 0.5 t CK – 9 + w ns tAA A0–A13, xMS to Data Valid 0.75 t CK – 12.5 + w ns tRDH Data Hold from RD High 1 ns Switching Characteristics : tRP RD Pulsewidth 0.5 tCK – 5 + w ns tCRD CLKOUT High to RD Low 0.25 t CK – 5 0.25 t CK + 7 ns tASR A0–A13, xMS Setup before RD Low 0.25 t CK – 6 ns tRDA A0–A13, xMS Hold after RD Deasserted 0.25 tCK – 3 ns tRWR RD High to RD or WR Low 0.5 t CK – 5 ns w = wait states · tCK. xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0 – A13 D tRDA tRWRtRP tASR tCRD tRDD tAA tRDH DMS, PMS, BMS, IOMS, CMS RD WR Figure 12.␣ Memory Read

–19–REV. 0 Parameter Min Max Unit Memory Write Switching Characteristics : tDW Data Setup before WR High 0.5 t CK – 7+ w ns tDH Data Hold after WR High 0.25 t CK – 2 ns tWP WR Pulsewidth 0.5 t CK – 5 + w ns tWDE WR Low to Data Enabled 0 ns tASW A0–A13, xMS Setup before WR Low 0.25 t CK – 6 ns tDDR Data Disable before WR or RD Low 0.25 t CK – 7 ns tCWR CLKOUT High to WR Low 0.25 t CK – 5 0.25 t CK + 7 ns tAW A0–A13, xMS, Setup before WR Deasserted 0.75 t CK – 9 + w ns tWRA A0–A13, xMS Hold after WR Deasserted 0.25 t CK – 3 ns tWWR WR High to RD or WR Low 0.5 t CK – 5 ns w = wait states · tCK. xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 D tWP tAW tCWR tDH tWDE tDW tASW tWWR tWRA tDDR DMS, PMS, BMS, CMS, IOMS RD WR Figure 13.␣ Memory Write

Figure 14. Serial Ports

1Start of Address Latch = IS Low and IAL High. 2End of Address Latch = IS High or IAL Low. 3Start of Write or Read = IS Low and IWR Low or IRD Low. Figure 15. IDMA Address Latch

1Start of Write = IS Low and IWR Low. 2End of Write = IS High or IWR High. 3If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. Figure 16. IDMA Write, Short Write Cycle

1Start of Write = IS Low and IWR Low. 2If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 3If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual , Third Edition . Figure 17. IDMA Write, Long Write Cycle

1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High. 3DM read or first half of PM read. Figure 18. IDMA Read, Long Read Cycle

–25–REV. 0 Parameter Min Max Unit IDMA Read, Short Read Cycle Timing Requirements : tIKR IACK Low before Start of Read 1 0n s tIRP Duration of Read 15 ns Switching Characteristics : tIKHR IACK High after Start of Read 1 15 ns tIKDH IAD15–0 Data Hold after End of Read 2 0n s tIKDD IAD15–0 Data Disabled after End of Read 2 10 ns tIRDE IAD15–0 Previous Data Enabled after Start of Read 0 ns tIRDV IAD15–0 Previous Data Valid after Start of Read 15 ns NOTES 1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High. tIRP tIKR PREVIOUS DATA tIKHR tIRDV tIKDD tIRDE tIKDH IAD 15–0 IACK IS IRD Figure 19.␣ IDMA Read, Short Read Cycle

capability of the output drivers as a function of output voltage. Figure 20. Typical Drive Currents C = load capacitance, f = output switching frequency.

• External data memory is accessed every cycle with 50% of the address pins switching.
• External data memory writes occur every other cycle with 50% of the data pins switching.
• Each address and data pin has a 10 pF total load at the pin.
• The application operates at V DD = 5.0 V and tCK = 25 ns. Total Power Dissipation = P INT + (C · VDD 2 · f) PINT = internal power dissipation from Power vs. Frequency graph (Figure 21). (C · VDD 2 · f) is calculated for each output: # of Pins 3 C 3 VDD 2 3f Address, DMS 8 · 10 pF · 52 V · 40 MHz = 80 mW Data Output, WR 9 · 10 pF · 52 V · 20 MHz = 45 mW RD 1 · 10 pF · 52 V · 20 MHz = 5 mW CLKOUT 1 · 10 pF · 52 V · 40 MHz = 10 mW 140 mW Total power dissipation for this example is PINT + 40 mW. VALID FOR ALL TEMPERATURE GRADES. 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14) 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 3IDLE REFERS TO ADSP-2184 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND. 4TYPICAL POWER DISSIPATION AT 5.0V V DD AND TA = 258C EXCEPT WHERE SPECIFIED. POWER (P IDLE n) – mW 62.1mW 34.7mW 32.8mW 34.3mW 36.6mW 70.55mW IDLE (16) IDLE (128) IDLE POWER, IDLE n MODES 2 POWER (P IDLE) – mW 82.28mW 91.52mWVDD = 5.5V 62.1mW 70.55mWVDD = 5.0V 44.73mW 51.705mWVDD = 4.5V POWER, IDLE 1, 2, 4 1/tCYC – MHz 33.33 40 175 400 275 250 225 200 375 350 300 325 330mW 250mW 180mW 300mW 225mW

2184 POWER, INTERNAL 1, 2, 3

Figure 21. Power vs. Frequency

Figure 27. Power-Down Supply Current

–29–REV. 0 100-Lead LQFP Package Pinout D19 D18 D17 D16 IRQE+PF4 IRQL0+PF5 GND IRQL1+PF6 DT0 TFS0 SCLK0 VDD DT1 TFS1 RFS1 DR1 GND SCLK1 ERESET RESET D15 D14 D13 D12 GND D11 D10 VDD GND D7/IWR D6/IRD D5/IAL D4/IS GND VDD D3/IACK D2/IAD15 D1/IAD14 D0/IAD13 BG EBG BR EBR A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 A12/IAD11 A13/IAD12 GND CLKIN XTAL VDD CLKOUT GND VDD WR RD BMS DMS PMS IOMS CMS 100 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) ADSP-2184 IRQ2+PF7 RFS0 DR0 EMS EE ELOUT ECLK ELIN EINT A3/IAD2 A2/IAD1 A1/IAD0 PWDACK BGH FL0 FL1 FL2 D23 D22 D21 D20 GND PF1 [MODE B] GND PWD VDD PF0 [MODE A] PF2 [MODE C] PF3

–30– REV. 0 LQFP Pin Configurations LQFP Pin LQFP Pin LQFP Pin LQFP Pin Number Name Number Name Number Name Number Name

1 A4/ IAD3 26 IRQE + PF4 51 EBR 76 D16

2 A5/ IAD4 27 IRQL0 + PF5 52 BR 77 D17

3G N D 2 8 G N D5 3 EBG 78 D18

4 A6/ IAD5 29 IRQL1 + PF6 54 BG 79 D19

5 A7/ IAD6 30 IRQ2 + PF7 55 D0/ IAD13 80 GND

6 A8/ IAD7 31 DT0 56 D1/ IAD14 81 D20

7 A9/ IAD8 32 TFS0 57 D2/ IAD15 82 D21

8 A10/ IAD9 33 RFS0 58 D3/ IACK 83 D22

9 A11/ IAD10 34 DR0 59 VDD 84 D23

10 A12/ IAD11 35 SCLK0 60 GND 85 FL2

11 A13/ IAD12 36 VDD 61 D4/ IS 86 FL1

12 GND 37 DT1 62 D5/ IAL 87 FL0

13 CLKIN 38 TFS1 63 D6/ IRD 88 PF3

14 XTAL 39 RFS1 64 D7/ IWR 89 PF2 [Mode C]

15 VDD 40 DR1 65 D8 90 VDD

16 CLKOUT 41 GND 66 GND 91 PWD

17 GND 42 SCLK1 67 VDD 92 GND

18 VDD 43 ERESET 68 D9 93 PF1 [Mode B]

19 WR 44 RESET 69 D10 94 PF0 [Mode A]

20 RD 45 EMS 70 D11 95 BGH

21 BMS 46 EE 71 GND 96 PWDACK

22 DMS 47 ECLK 72 D12 97 A0

23 PMS 48 ELOUT 73 D13 98 A1/ IAD0

24 IOMS 49 ELIN 74 D14 99 A2/ IAD1

25 CMS 50 EINT 75 D15 100 A3/ IAD2

The ADSP-2184 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [␣ ] are state bits latched from the value of the pin at the deassertion of RESET.

–31–REV. 0 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) SEATING PLANE 0.030 (0.75) 0.024 (0.60) TYP 0.020 (0.50) 0.063 (1.60) MAX 128 TYP 0.007 (0.177) 0.005 (0.127) TYP 0.003 (0.077) 68 ± 48 08 – 78 0.004 (0.102) MAX LEAD COPLANARITY TOP VIEW (PINS DOWN) 100 76 0.011 (0.27) 0.009 (0.22) TYP 0.007 (0.17) 0.640 (16.25) 0.630 (16.00) TYP SQ 0.620 (15.75) 0.020 (0.50) BSC LEAD PITCH 0.553 (14.05) 0.551 (14.00) TYP SQ 0.549 (13.95) 0.472 (12.00) BSC LEAD WIDTH NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08) 0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED ORDERING GUIDE Ambient Instruction Temperature Rate Package Package Part Number Range (MHz) Description Option* ADSP-2184BST-160 –40 °C to +85°C 40.0 100-Lead LQFP ST-100 *ST = Plastic Thin Quad Flatpack (LQFP). OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3418–2–5/99PRINTED IN U.S.A.