21140

21140 ETC | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 43

Technical content

1 DECchip 21140 Overview

The DECchip 21140 PCI Fast Ethernet LAN Controller (21140) supports the peripheral component interconnect (PCI) bus. It provides a direct interface connection to the PCI and adapts easily to most other standard buses. The 21140 software interface and data structures are optimized to minimize the host CPU load and to allow for maximum flexibility in the buffer descriptor management. The 21140 contains large onchip FIFOs, so no additional onboard memory is required.

1.1 Generai Description

The 21140 interfaces with the PCI bus using onchip control and status registers (CSRs), and a shared CPU memory area that is set up mainly during initialization. This minimizes the processor involvement in the 21140 operation during normal reception and transmission. The 21140 is compliant with the PCI Local Bus Specification, Revision 2.0. Bus traffic is also minimized by filtering out received runt frames and by automatically retransmitting collided frames without needing to repeat a fetch from shared memory. On the network side, the 21140 provides two ports: a serial (SRL) 10-Mb/s port and a media independent interface/symbol (MII/SYM) 100-Mb/s port. The 10-Mb/s port provides a direct interface to the external 10-Mb/s front-end decoder (ENDEC). The 100-Mb/s port supports two operational modes: a direct interface to the external 100-Mb/s ENDEC and a full implementation of the MII standard. The 21140 includes the onchip physical coding sublayer (PCS) and the scrambler for efficient 1OOBASE-T (CATS5 cable) implementation. It is also capable of functioning in a full-duplex environment for both the 10-Mb/s and 100-Mb/s ports. MH 2841136 0033137 cae Preliminary Information 1

1.2 Features

The 21140 has the following features: * Offers a single-chip Fast Ethernet controller for PCI local bus: - Provides a direct interface to PCI bus - Supports two network ports: 10-Mb/s and 100-Mb/s ¢ Supports full-duplex operation on both 10-Mb/s and 100-Mb/s ports * Contains large independent receive and transmit FIFOs; no additional onboard memory required ¢ Provides standard 100-Mb/s MII supporting CATS unshielded twisted-pair (UTP), CAT5 UTP, shielded twisted-pair (STP) and fiber cables * Contains onchip scrambler and PCS for CATS to significantly reduce cost of 100BASE-T solutions * Supports MII management functions * Includes a powerful onchip DMA with programmable burst size providing for low CPU utilization ¢ Implements unique, patent-pending intelligent arbitration between DMA channels to minimize underflow or overflow ¢ Supports PCI clock speed range from 25 to 33 MHz « Supports either big or little endian byte ordering * Implements JTAG-compatible test-access port with boundary-scan pins ¢ Supports IEEE 802.3, ANSI 8802-3, and Ethernet standards * Offers a unique, patented solution to Ethernet capture-effect problem ¢ Contains a variety of flexible address filtering modes (including perfect, hash tables, inverse perfect, and promiscuous): - 16 perfect addresses (normal or inverse filtering) - 512 hash-filtered addresses - 512 hash-filtered multicast addresses and one perfect address — Pass all multicast — Promiscuous * Provides external and internal loopback capability on both ports 2. Preliminary Information mm 2841136 0033138 1159 ||

¢ Contains 8-bit, general-purpose, programmable register and corresponding V/O pins * Provides serial MicroWire interface for Ethernet address external ROM * Provides LED support for various network activity indications ¢ Implements low-power, 3.3-V complementary metal-oxide semiconductor (CMOS) process technology; interfaces to 5.0-V logic environment

1.3 Microarchitecture

The following list describes the 21140 hardware components, and Figure 1 shows a block diagram of the 21140. * PCI interface—Includes all interface functions to the PCI bus; handles all interconnect control signals, and executes PCI direct memory access (DMA) and Y/O transactions * DMA—Contains dual receive and transmit controller; supports bursts of up to 32 longwords; handles data transfers between CPU memory and onchip memory ¢ FIFOs—Contains two FIFOs for receive and transmit; supports automatic packet deletion on receive (runt packets or after a collision) and packet retransmission after a collision on transmit ¢ TxM—Handles all CSMA/CD! MAC? transmit operations, and transfers data from transmit FIFO to the ENDEC for transmission ¢ RxM—Handles all CSMA/CD receive operations, and transfers the data from the ENDEC to the receive FIFO ¢ Physical coding sublayer—Implements the encoding and decoding sublayer of the 100BASE-TX (CATS) specification including the squelch ¢ Scrambler/descrambler—Implements the twisted-pair physical layer medium dependent (TP-PMD) scrambler/descrambler scheme * General-purpose register—Enables software to use for input or output functions

1 Carrier-sense multiple access with collision detection

? Media access control MB 2841136 0033135 OSS a Preliminary Information 3

¢ Serial interface—Provides a 7-wire conventional interface to the Ethernet ENDEC components ¢ MII/SYM interface— Provides a full MII signal interface and a direct interface to the 100-Mb/s ENDEC for CATS ¢ Serial ROM—Provides a direct interface to the MicroWire Ethernet address ROM and other system parameters

4 Prelimi i

reliminary information wy 2344336 0033140 877 Ml

Figure 1. DECchip 21140 Block Diagram

2 Pinout

The 21140 is packaged in a 144-pin PQFP. The tables in this section provide a description of the pins and their respective signal definitions. Table 1 lists the tables in this section. Figure 2 shows the 21140 pinout. Table 1 Index to Pinout Tables Logic signals Table 2 Power pins Table 3 Functional signals description Table 4 Input pins Table 5 Output pins Table 6 Input/output pins Table 7 Open drain pins Table 8 Signal functions Table 9

6 Preliminary Information gy 2841236 003342 b4T =

Figure 2. DECchip 21140 Pinout Diagram (Top View)

4921098755432 OSE TE SES D1 OGBTESESEIOS

2.1 Signal Reference Tables

Table 2 provides an alphabetical list of the 21140 logic names and their pin numbers. Table 3 provides a list of the 21140 power pin numbers. Table 2 Logic Signals Pin Pin Pin Signal Number Signal Number Signal Number ad<00> 72 ad<24> 20 intl 1 ad<01> 71 ad<25> 19 irdy_1 40 ad<02> 69 ad<26> 17 mii_clsn 112 ad<03> 68 ad<27> 16 mii_crs 3 ad<04> 66 ad<28> 14 mii_dv ill ad<05> 65 ad<29> 13 mii_err 110 ad<06> 63 ad<30> 11 mii_mde 106 ad<07> 62 ad<31> 10 mii_mdio 105 ad<08> 60 e_be_l<00> 61 mii/srl 133 ad<09> 58 c_be_l<01> 48 mii/sym_relk 114 ad<12> 54 devsel_l 42 mii/sym_rxd<02> 117 ad<13> 52 frame_l 39 mii/sym_rxd<03> 118 ad<14> 51 gep<00> 80 mii/sym_tclk 123 ad<15> 50 gep<01> 81 mii/sym_txd<00> 126 ad<16> 35 gep<02> 82 mii/sym_txd<01> 127 ad<17> 34 gep<03> 83 mii/sym_txd<02> 130 ad<18> 30 gep<04> 86 mii/sym_txd<03> 131 ad<19> 29 gep<05> 87 mii/sym_txen. 125 ad<20> 27 gep<06> 88 ne 91 ad<21> 26 gep<07> 89 ne 92 ad<22> 25 gnt_l 7 ne 93 ad<23> 24 idsel 22 ne 94 (continued on next page)

8 Preliminary Information Ml 2841136 0033244 4le a

Table 3. Power Pins

Address and appropriate bus commands are driven during this cycle. Data and the appropriate byte enable codes are driven during this cycle. All pin names with the _ suffix are asserted low. The following abbreviations are used in Table 4. Table 2. and data bits are multiplexed on the same and big endian byte ordering can be used.

10 Preliminary Information gg 2341236 poaab4b 295 =

Table 2. enable lines. Bus command and byte enable are multiplexed on the same PCI pins. these four bits provide the bus command. determines which byte lines carry valid data. is the final data phase transaction. Table 2. as either status pins or control pins. These access to the bus is granted.

Table 4 (Cont.) Functional Description of DECchip 21140 Signals eases ll Pin Signal Type Number Description “ee int_l op 1 Interrupt request asserts when one of the appropriate bits of CSRS5 sets and causes an interrupt, provided that the corresponding mask bit in CSR7 is not asserted. Interrupt request deasserts by writing a 1 into the appropriate CSR5 bit. If more than one interrupt bit is asserted in CSR5 and the host doesn’t clear all input bits, the 21140 deasserts int_l for one cycle to support edge-triggered systems. This pin must be pulled up by an external resistor. irdy_l vo 40 Initiator ready indicates the bus master’s ability to complete the current data phase of the transaction. A data phase is completed on any rising edge of the clock when both irdy_l and target ready trdy_l are asserted. Wait cycles are inserted until both irdy_l and trdy_} are asserted together. When the 21140 is the bus master, irdy_l is asserted during write operations to indicate that valid data is present on the 32-bit ad lines. During read operations, the 21140 asserts irdy_] to indicate that it is ready to accept data. mii_elsn I 112 Collision detected is asserted when detected by an external physical layer protocol (PHY) device. mii_crs I 113 Carrier sense is asserted by the PHY when the media is active. mii_dv I lll Data valid is asserted by an external PHY when receive data is present on the mii/sym_rxd lines and deasserted at the end of the packet. This signal should be synchronized with the mii/sym_relk signal. (continued on next page)

12 Preliminary Information M™ 2841136 0033148 Obs mu

Table 4 (Cont.) Functional Description of DECchip 21140 Signals eee Pin Signal Type Number Description Ah mii_err I 110 Receive error asserts when a data decoding error is detected by an external PHY device. This signal is synchronized to mii/sym_relk and can be asserted for a minimum of one receive clock. When asserted during a packet reception, it sets the cyclic redundancy check (CRC) error bit in the receive descriptor (RDESO). mii_mdc le} 106 MII management data clock is sourced by the 21140 to the PHY devices as a timing reference for the transfer of information on the mii_mdio signal. mii_mdio vo 105 MII management data input/output transfers control information and status between the PHY and the 21140. mii/srl ie) 133 Indicates the selected port: SRL or MII/SYM. When asserted, the MII/SYM port is active. When deasserted, the SRL port is active. mii/sym_relk I 114 Supports either the 25-MHz or 2.5-MHz receive clock. This clock is recovered by the PHY. mii/sym_ I See Four parallel receive data lines when MIT rxd<03:00> Table 2. mode is selected. This data is driven by an external PHY that attached the media and should be synchronized with the mii/sym_relk signal. mii/sym_telk I 123 Supports the 25-MHz or 2.5-MHz transmit clock supplied by the external PMD device. This clock should always be active. mii/sym_ [e} See Four parallel transmit data lines. This txd<03:00> Table 2. data is synchronized to the assertion of the mii/sym_telk signal and is latched by the external PHY on the rising edge of the mii/sym_telk signal. mii/sym_txen oO 125 Transmit enable signals that the transmit is active to an external PHY device. This signal is ignored in PCS mode (CSR6<23>). (continued on next page) mM 28411236 0033149 TTY Preliminary Information 13

Table 4 (Cont.) Functional Description of DECchip 21140 Signals e_e__eeoovtrreeeeee Pin Signal Type Number Description signa’ ne oO 101 No connection. ne fe) 102 No connection. ne oO 103 No connection. ne oO 104 No connection. par Vo 47 Parity is calculated by the 21140 as an even parity bit for the 32-bit ad and 4-bit e_be_l lines. During address and data phases, parity is calculated on all the ad and c_be_l lines whether or not any of these lines carry meaningful information. pei_clk I 5 The clock provides the timing for the 21140 related PCI bus transactions. All the bus signals are sampled on the rising edge of pei_elk. The clock frequency range is between 25 MHz and 33 MHz. perr_1 yo 45, Parity error asserts when a data parity error is detected. When the 21140 is the bus master and a parity error is detected, the 21140 asserts. both CSR5 bit 13 (system error) and CFCS bit 8 (serr_] enable). Next, it completes the current data burst transaction, then stops operation. After the host clears the system error, the 21140 continues its operation. When the 21140 is the bus target and a parity error is detected, the 21140 asserts perr_l. This pin must be pulled up by an external resistor. rev_match oO 122 Receive match indication is asserted when a received packet has passed address recognition. req ° 8 Bus request is asserted by the 21140 to indicate to the bus arbiter that it wants to use the bus. (continued on next page) 14 Preliminary Information . M™ 2841136 0033150 716 me

Table 4 (Cont.) Functional Description of DECchip 21140 Signals Ee Pin Signat Type Number Description a rst_l I 2 Resets the 21140 to its initial state. This signal must be asserted for at least 10 active PCI clock cycles. When in the reset state, all PCI output pins are put into tristate and all PCI O/D signals are floated. rsv_vss<07:00> I See Reserved. Must be tied to vss. Table 2. sd I 109 Signal detect indication supplied by an external physical layer medium dependent (PMD) device. serr_l vo 46 If an address parity error is detected and CFCS bit 31 (detected parity error) is enabled, 21140 asserts both serr_l (system error) and CFCS bit 30 (signal system error). When an address parity error is detected, system error asserts two clocks after the failing address. This pin must be pulled up by an external resistor. sr_ck fe) 78 Serial ROM clock signal. sr_cs fe) 79 Serial ROM chip-select signal. sr_di fe} 77 Serial ROM data-in signal. sr_do I 16 Serial ROM data-out signal. srl_clsn I 134 Collision detect signals a collision occurrence on the Ethernet cable to the 21140. It may be asserted and deasserted asynchronously by the external ENDEC to the receive clock. srlrelk I 137 Receive clock carries the recovered receive clock supplied by an external ENDEC. During idle periods, srl_relk may be inactive. srl_rxd I 135 Receive data carries the input receive data from the external ENDEC. The incoming data should be synchronous with the srl_relk signal. (continued on next page) MB 2841136 0033151 b5° Preliminary Information 15

Table 4 (Cont.) Functional Description of DECchip 21140 Signals ae Pin Signal Type Number Description sion’ OO OE srl_rxen I 136 Receive enable signals activity on the Ethernet cable to the 21140. It is asserted when receive data is present on the Ethernet cable and deasserted at the end of a frame. It may be asserted and deasserted asynchronously to the receive clock (srl_relk) by the external ENDEC. srl_telk I 139 Transmit clock carries the transmit clock supplied by an external ENDEC. This clock must always be active (even during reset). srl_txd (9) 138 Transmit data carries the serial output data from the 21140. This data is synchronized to the srl_telk signal. srl_txen oO 140 ‘Transmit enable signals an external ENDEC that the 21140 transmit is in progress. stop_l vo 43 Stop indicator indicates that the current target is requesting the bus master to stop the current transaction. ‘The 21140 responds to the assertion of stop_1 when it is the bus master, either to disconnect, retry, or abort. sym_link fe) 124 Indicates that the descrambler is locked to the input data signal. sym_rxd<04> Tr 119 Receive data, together with the four receive lines mii/sym_rxd<03:00>, provide five parallel lines of data in symbol form for use in PCS mode (100BASE-T, CSR6<23>). This data is driven by an external PMD device and should be synchronized to the mii/sym_rclk signal. sym_txd<04> oO 132 Transmit data, together with the four transmit lines mii/sym_txd<03:00>, provide five parallel lines of data in symbol form for use in PCS mode (100Base-T, CSR6<23>). This data is synchronized on the rising edge of the mii/sym_telk signal. (continued on next page)

16 Preliminary Information

Table 4 (Cont.) Functional Description of DECchip 21140 Signals Pin Signal Type Number Description tek I 141 JTAG clock shifts state information and test data into and out of the 21140 during JTAG test operations. This pin should not be left unconnected. tdi I 143 JTAG data in is used to serially shift test data and instructions into the 21140 during JTAG test operations. This pin should not be left unconnected. tdo oO 144 JTAG data out is used to serially shift test data and instructions out of the 21140 during JTAG test operations. tms I 142 JTAG test mode select controls the state operation of JTAG testing in the 21140. This pin should not be left unconnected. trdy_l vO 41 Target ready indicates the target agent’s ability to complete the current data phase of the transaction. A data phase is completed on any clock when both trdy_l and irdy_l are asserted. Wait cycles are inserted until both irdy_} and trdy_l are asserted together. When the 21140 is the bus master, target ready is asserted by the bus slave on the read operation indicating that valid data is present on the ad lines. During a write cycle, it indicates that the target is prepared to accept data. vdd P See 3.3-volt supply input voltage. Table 3. vdd_clamp P 73 5-volt power. vss P See Ground pins. Table 3. Preliminary Information 17 Mm 2441136 0033153 425 reliminary Information

2.2 Pin Tables

This section contains four types of pin tables: ¢ Table 5 lists the input pins. * Table 6 lists the output pins. e Table 7 lists the input/output pins. ¢ Table 8 lists the open drain pins. Table 5 Input Pins i ee Active Active Signal Level Signal Level prone gnt_l Low sd High idsel High sr_do High mii_clsn High srl_clsn High mii_crs High srl_relk = mii_dv High srl_rxd - mii_err High srl_rxen High mii/sym_relk - srl_telk — mii/sym_telk - tek _ pei_clk - tdi - rst_l Low tms High rsv_vss<07:00> - a

18 Preliminary Information

¥ WM 2841136 O033,54 3b] we

mii_mde - st_es High mii/srl - sr_di High mii/sym_txd<03:00> — srl_txd - mii/sym_txen High srl_txen High ne - sym_link High rev_match High sym_txd<04> - req_] Low tdo High sr_ck - Table 7 Input/Output Pins Active Active Signal Level Signal Level ad<31:00> -— mii_mdio - devsel_] Low perr_] Low frame_l Low serr_l Low gep<07:00> _ stop_l Low irdy_l Low trdy_l Low Table 8 Open Drain Pins Active Signal Level intl Low

2.3 Signal Grouping by Function

Table 9 lists the signals according to their interface function. Preliminary Information 19 MH 2441136 0033155 2Ts

PCI Address and data ad<31:00>, par Arbitration gnt_l, req_l Bus command and byte enable c_be_1<03:00> Device select devsel_l, idsel Error reporting perr_l, serr_l Interrupt int_l System pei_clk, rst_l Control signals frame_l, stop_l, irdy_l, trdy_l MIV/symbol Transmit data lines mii/sym_txd<03:00> Network port Receive data lines mii/sym_rxd<03:00> Transmit, receive clocks mii/sym_telk, mii/sym_rclk SYM mode sym_rxd<04>, sym_txd<04> Signal detection sd Transmit enable mii/sym_txen Collision detect mii_clsn Error reporting mii_err Data control mii_dv, mii_crs MII management data clock mii_mde MII management data mii_mdio input/output Serial port ‘Transmit and receive data srl_txd, srl_rxd Transmit control srl_txen, srl_telk Receive control srl_rxen, srl_relk Collision detect srl_clsn Miscellaneous LED indicators rev_match, sym_link General-purpose pins gep<07:00> MII/SYM and serial port select mii_srl (continued on next page)

20 Preliminary Information mm 2842136 0033b5b 134 a

Table 9 (Cont.) Signal Functions Interface Function Signal Test access port JTAG test operations tek, tdi, tdo, tms Ethernet ID Address ROM sr_ck, sr_cs, sr_di, sr_do port Power 3.3-volt and 5-volt supply input —- vdd, vdd_clamp Ground vss Prelimit Inte ti M™ 2841136 00393157 070 = reliminary Information 21

3 Electrical and Environmental Specifications

This section contains the electrical and environmental specifications of the 21140. Stresses greater than the maximum or less than the minimum ratings can cause permanent damage to the 21140. Exposure to the maximum or minimum ratings for extended periods of time lessen the reliability of the 21140.

3.1 Voltage Limit Ratings

Table 10 lists the voltage limit ratings. Table 10 Voltage Limit Ratings Parameter Minimum Maximum Power supply voltage +3.135 V +3.465 V vdd_clamp (5.0 V) 44.75 V +5.25 V ESD protection voltage - +2000 V

3.2 Temperature Limit Ratings

Table 11 lists the temperature limit ratings. Table 11 Temperature Limit Ratings Parameter Minimum Maximum Storage temperature 55°C +125°C Operating temperature o°c 70°C 22 Preliminary Information mm 2841136 o033158 TO? |

3.3 Supply Current and Power Dissipation

The values in Table 12 are estimates based on a PCI clock frequency of 38 MHz and a network data rate of 10-Mb/s for SRL and 100-Mb/s for MII. Table 12 Supply Current and Power Dissipation Symbol Conditions Typical Maximum Units IDD vdd=3.465 V, Ta=70°C 160 210 mA Power vdd=3.465 V, Ta=70°C 0.52 0.72 WwW

3.3.1 PCI I/O Voltage Specifications

The 21140 meets the I/O voltage specifications listed in Table 13. Table 13 /O Voltage Specifications for 5.0-Volt Environment Category PCI VO PCI Output PCI Input Vil 08 V - 0.8 V Vih 2.0V - 2.0V Vol! 0.55 V 0.55 V - Voh 24V 24V - Toh -2mA -2 mA - Toz +/-70 pA +/-70 pA - Max Vin vdd_clamp + 0.5 V - vdd_clamp + 0.5 V pale resistors (including frame 1, trdy I, irdy 1, devsel I, stop.l, serr_l, and perr |) must ave 6 milliamps. MH 2841136 0033159 943 a Preliminary Information 23

3.3.2 PCI Reset

PCI reset (pei_rst) is an asynchronous signal that must be active for at least 10 active PCI clock (pei_clk) cycles. Figure 3 shows the PCI reset timing characteristics, and Table 14 lists the PCI reset signal limits. Figure 3 PCI Reset Timing Diagram pei_rst ~~ \\_ 10 pei_elk Cycles L-09902 Al Table 14 PCI Reset Timing Symbol Parameter Minimum Maximum Conditions Trst pei_rst pulse width 10*Teycle Not applicable pei_clk active

24 Preliminary Information

% ME 284113b 0033160 bbS ml

3.3.3 PCI Clock Specifications

The clock frequency range for the PCI is between 25 MHz and 33 MHz. Figure 4 shows the PCI clock specification timing characteristics, and Table 15 lists the frequency-derived clock specifications. Figure 4 PCI Clock Specifications Timing Diagram Thigh 20 V A coe fn. Tlow Teycle Ls.03910 Al Table 15 PCI Clock Specifications Symbol Parameter Minimum Maximum Notes Teycle Cycle time 30 ns 40 ns - Thigh pei_clk high time 12 ns 24 ns At2V Tlow pei_clk low time 12 ns 24 ns At 0.8 V TrTf pei_clk slew rate 1V/ns 4 Vins - ‘Rise and fall times are specified in terms of the edge rate measured in V/ns. Parameter design guarantee. Mm 2842136 OO33Ib1 STI | Preliminary Information 25

3.3.4 Other PCI Signals

Figure 5 shows the timing diagram characteristics, and Table 16 lists the other PCI signals. This timing is identical to the timing for the general-purpose register signals, Figure 5 Timing Diagram for Other PCI Signals Clk Tval (min) Van >| Ton Tot Tsu Th MLo-010331 Table 16 Other PCI Signals Symbol Parameter Minimum Maximum Conditions Tval clk-to-signal valid 2ns ll ns Cload = 50 pF delay Ton? Float-to-active delay 2ns - - from clk Toff Active-to-float delay - 28 ns - from clk Tsu Input signal valid Tns - - setup time before clk Th Input signal hold time 0 ns - - from clk Tr Unloaded output rise - 2ns 0.4 V to 2.4V time Th Unloaded output fall - 2ns 24V t004V time 1Parameter design guarantee.

26 Preliminary Information

M@™ 2441156 0033162 438

3.4 Serial and Mil Interface Specifications

Table 17 lists the specifications for the serial and MII interfaces. Table 17 Serial and MIl Interface Specifications Symbol Definition Conditions Minimum = Maximum —_Units Ven Output high voltage In = —4mA 24 - v Vor Output low voltage Ty = 4mA - 04 v Vin Input high voltage - 2.0 - v Va Input low voltage - - 0.8 v la Input current Vin = Veo or Vss 10.0 10.0 pA Ton Maximum tristate output Vin = Vag or Ves ~10.0 10.0 pA leakage current

3.5 Serial Port Timing

This section describes the serial port timing limits. Preliminary Information 27 M@@® 2641136 0033163 374

3.5.1 Serial 10-Mb/s Timing—Transmit

Figure 6 shows the serial port transmit timing characteristics, and Table 18 lists the serial port transmit timing limits. Figure 6 Serial Port Timing Diagram—Transmit Ttet Tter Ttol| | Ttch srl_telk | - one PX) Ce : ; ITtep, Tteh sri_txen MLO-0190114 Table 18 Serial Port Timing—Transmit Symbol Definition Minimum Maximum Units Ttel srl_tclk low time 45 55 ns Ttch srl_telk high time 45 55 ns ‘Teer! srl_telk rise time - 8 ns Ttef! srl_telk fall time - 8 ns Ttdp srl_telk fall time to srl_txd valid - 40 ns Ttdh srl_txd hold after srl_telk fall time 5 - ns Ttep srl_telk fall time to srl_txen valid - 40 ns Tteh srl_txen hold after srl_telk fall time 5 - ns 1parameter design guarantee.

28 Preliminary Information

M@ 2841136 0033164 200

3.5.2 Serial 10-Mb/s Timing—Collision

Figure 7 shows the serial port collision timing characteristics, and Table 19 lists the serial port collision timing limit. Figure 7 Serial Port Timing Diagram—Collision srl_cisn Telh MLo-013012 Table 19 Serial Port Timing—Collision Symbol Definition Minimum Maximum — Units Telh! srl_clsn high time 20 - ns 1Pparameter design guarantee. 2841136 0033165 147 a Preliminary Information 29

3.5.3 Serial 10-Mb/s Timing—Receive, Start of Packet

Figure 8 shows the serial port timing characteristics in receive mode, start of packet; and Table 20 lists the serial port timing limits in receive mode, start of packet. Figure 8 Serial Port Timing Diagram—Receive, Start of Packet Trer Tref Trel} | Trch I sri_reik | Trds Trdh srl_rxen / MLO-013013

3.5.4 Serial 10-Mb/s Timing—Receive, End of Packet

Figure 9 shows the serial port timing characteristics in receive mode, end of packet; and Table 20 lists the serial port timing limits in receive mode, end of packet. 30. Preliminary Information M™® 2841136 00331bb 043

Figure 9 Serial Port Timing Diagram—Receive, End of Packet sri_rclk Treh srl_rxen MLo-013014 Table 20 Serial Port Timing—Receive, Start and End of Packet Symbol Definition Minimum Maximum Units Tree srl_relk cycle time 85 us ns Trel srl_relk low time 38 80 ns Treh srl_relk high time 38 80 ns Trer! srl_relk rise time - 8 ns ‘Tref? srl_relk fall time - 8 ns ‘Trds srl_rxd setup to srl_relk fall time 10 - ns Trdh srl_rxd hold after srl_relk fall time 5 - ns Trel srl_rxen low time 120 - ns ‘Treh srl_rxen hold after srl_relk rise time 40 - ns 1Parameter design guarantee.

3.6 Mil Port Timing

This section describes the MII port timing limits. Preliminary Information 31 = 2641136 0033167 TLT a reliminary "

3.6.1 MII 100-Mb/s Timing—Transmit

Figure 10 shows the MII port transmit timing characteristics, and Table 21 lists the MII port transmit timing limits. Figure 10 Mil Port Timing Diagram—Transmit be Tec > Tor ml bx ml be tot | Teh | |_Jel | ese ne | mii/sym_tclk FNP VS VS VT ‘tw I mii/sym_txd<03:00> | Trh mii/sym_txen ii \\ L-03903 AI Table 21 Mil Port Timing—Transmit Symbol _Definition Minimum Typical Maximum —_Units ‘Tec! mii/sym_telk cycle time - 40 - ns Teh mii/sym_telk high time 4 - 26 ns Te mii/sym_telk low time 14 - 26 ns Ter mii/sym_telk rise time - 8 - ns Tef mii/sym_telk fall time - 8 - ns Trv? mii/sym_telk rise to - - 16 ns mii/sym_txen valid time or mii/sym_telk rise to mii/sym_txd valid time ‘Trh mii/sym_txen hold after 5 - - ns mii/sym_telk rise time 14/- 100 parts per million. 2Outputs transmit data (mii/sym_txd) and transmit enable (mii/sym_txen) are driven internally from the rising edge of mii/sym_telk. 32. Preliminary Information MH 2641136 0033168 55b

3.6.2 MIl 100-Mb/s Timing—Receive

Figure 11 shows the MII port receive timing characteristics, and Table 22 lists the MII port receive timing limits. Figure 11 Mil Port Timing Diagram—Receive

1 Tec 1

Tor | le ml bee Tot | | [Teh | Tel) | | ba Lae ot | | \\ mil/sym_rcik ae ne f ' | se! Tts be Th »! mil_dv / \\ -03908.A1 Table 22 Mil Port Timing—Receive Symbol _Definition Minimum Typical = Maximum —_Units ‘Tee mii/sym_relk cycle time - 40 - ns ‘Teh mii/sym_relk high time 14 - 26 ns Tel mii/sym_relk low time 14 - 26 ns Ter mii/sym_relk rise time - 8 - ns Tet mii/sym_relk fall time - 8 - ns Tts! mii/sym_rxd setup (both 10 - - ns rise and fall transactions) to mii/sym_rclk rise time or mii_dv setup (both rise and fall transactions) to mii/sym_relk rise time Tth mii/sym_rxd hold (both rise 10 - - ns and fall transactions) after mii/sym_relk rise time or mii_dv hold (both rise and fall transactions) after mii/sym_relk rise time lnputs receive data (mii/sym_rxd) and data valid (mii_dv) are latched internally on the rising edge of mii/sym_relk. Preli Information 33 M™ 2841136 0033169 892 retiminary hnforma

3.6.3 Mil 100-Mb/s Timing—Signal Detect

Figure 12 shows the MII port signal detect timing characteristics, and Table 23 lists the MII port signal detect timing limits. Figure 12 MIl Port Timing Diagram—Signal Detect mil/sym_relk oy en ee a ee a ee ee Tis | | Tth a a Cae 4.03908 Al Table 23 Mil Port Timing—Signal Detect Symbol _ Definition Minimum = Maximum —_Units Tts! sd setup (both rise and fall transactions) 10 - ns to mii/sym_relk fall time Teh! ‘sd hold (both rise and fall transactions) 12 - ns after mii/sym_relk fall time Mnput signal detect (sd) is latched internally on the falling edge of mii/sym_rclk.

34 Preliminary Information

% MB 2843136 0033170 504 ml

3.6.4 MII 100-Mb/s Timing—Receive Error

Figure 13 shows the MII port receive error timing characteristics, and Table 24 lists the MII port receive error timing limits. Figure 13 Mil Port Timing Diagram—Receive Error mii/sym_retk —S\\SJ NSS \\S- Tts | Tth ae KS mii_err } \\ LJ-03906 AI Table 24 Mil Port Timing—Receive Error Symbol _Definition Minimum = Maximum —_Units ‘Tes! mii_err setup (both rise and fall 10 - ns transactions) to mii/sym_relk rise time Tth! mii_err hold (both rise and fall 10 - ns transactions) after mii/sym_relk rise time lnput receive error (mii_err) is latched internally on the rising edge of mii/sym_rclk. ME 2841136 0033171 440 Preliminary Information 35

3.6.5 MIl 100-Mb/s Timing—Carrier Sense and Collision

Figure 14 shows the MII port carrier sense and collision timing characteristics, and Table 25 lists the MII port carrier sense and collision timing limits. Figure 14 Ml Port Timing Diagram—Carrier Sense and Collision mii_cisn / \\ Lv-03928 Al Table 25 Mil Port Timing—Carrier Sense and Collision Symbol _ Definition Minimum = Maximum —_—_Units ‘Telh mii_ers, mii_clsn high time 20 - ns 36 Preliminary Information ma 2841136 goa3172 38? nm

3.7 Ethernet ID Port Timing

Figure 15 shows the Ethernet ID port timing, and Table 26 lists the characteristics. This timing is identical to the timing for the MIT management signals (mii_mdio and mii_mde). Figure 15 Ethernet ID Port Timing Diagram i i] sr_cs, st_ck | | sr_di, sr_do elle ee Tsr Tet L-03909 AI Table 26 Ethernet ID Port Timing Characteristics nee ee Symbol Definition Minimum Maximum Units Tsr Rise time - 10 ns Tsf Fall time - 10 ns MM 284113b 0033173 213 Preliminary Information 37

3.8 Boot ROM Port Timing

The boot ROM port is not implemented in this release.

3.9 JTAG Boundary Scan Timing

Figure 16 shows the JTAG boundary scan timing, and Table 27 lists the interface signal timing relationships. Figure 16 JTAG Boundary Scan Timing Diagram Tek_cycle Tok f ~ ~| wl le tek ml tms_s_ |Tms_h ae aa (DO | f Td_s 'Tdih | Tdo_d an oe oe 109808.

38 Preliminary Information mm 2841136 0033174 157 =

Table 27 JTAG Interface Signal Timing Relationships Oe Symbol Parameter Minimum Maximum Units EE Tms_s tms setup time 20 - ns Tms_h tms hold time 5 - ns Tdi_s tdi setup time 20 - ns Tdi_h tdi hold time 5 - ns Tdo_d tdo delay time - 20 ns ‘Tek_r! tek rise time - 3 ns ‘Tek_f! tek fall time - 3 ns Tek_cycle tek cycle time 90 - ms eee ‘Parameter design guarantee. WH 2841136 0033175 OFb Ba Preliminary Information 39

4 Mechanical Specifications

The 21140 is contained in a 144-pin plastic quad flat pack (PQFP). Table 28 lists the mechanical specifications, and Figure 17 shows the mechanical layout of the 21140. Table 28 Mechanical Specifications Item Minimum Nominal’ Maximum’ A - - 4.07 Al 0.25 - - A2 3.17 3.37 3.67 D - 31.20 BSC - D1 - 28.00 BSC - D3 22.75 Reference 22.75 Reference 22.75 Reference L 0.65 0.80 1.00 N - 144 - P 0.65 BSC 0.65 BSC 0.65 BSC Ww 0.22 0.30 0.38 a o - 7? ee

40 Preliminary information gm 2841136 003317b Tee =

Figure 17 Mechanical Layout of the DECchip 21140 N #1 Pin —p oe! = Pin 1 1D —sis BE wo ES ES = = =) Ss + = © ®E . ERERSREASHEEARAEAPAGEE EEE BS See Detail “A” A sana HO 8

1.626 Reference q

(0.064) 13/0. FF cos 0-008) Detail "A" AZ p12 oe (~ \\ ro Note: All dimensions are in millimeters. mLo.019029 BM 2841136 0033177 969 Preliminary Information 41

Technical Support and Ordering Information Technical Support If you need technical support or help deciding which literature best meets your needs, call the Digital Semiconductor Information Line: United States and Canada = 1-800-332-2717 TTY (United States only) 1-800-332-2515 Outside North America +1-508-568-6868 Ordering Digital Semiconductor Products To order the DECchip 21140 PCI Fast Ethernet LAN Controller and evaluation board, contact your local distributor. You can order the following semiconductor products from Digital: Product Order Number DECchip 21140 PCI 21140-AA Fast Ethernet LAN Controller DECchip 21140 Evaluation Board Kit 21A40-03 Ordering Associated Literature The following table lists some of the available Digital Semiconductor literature. For a complete list, contact the Digital Semiconductor Information Line. For ordering information, see the Ordering Electronically and Ordering by Telephone and Through Direct Mail sections. Title Order Number DECchip 21140 PCI Fast Ethernet LAN Controller EC-QCOAA-TE Product Brief DECchip 21140 PCI Fast Ethernet Evaluation Board EC-QD2SA-TE User’s Guide W@™ 2841136 0033178 aTS 4a

To place an order through your account at the Electronic Store, dial 1-800-234-1998, using a modem set to 2400- or 9600-baud. You must use a VT terminal or terminal emulator set at 8 bits, no parity. If you need assistance using the Electronic Store, call 1-800-DIGITAL (1-800-344-4825) and ask for an Electronic Store specialist. Ordering by Telephone and Through Direct Mail eee From Call Write USA. DECdirect Digital Equipment Corporation Phone: 1-800-DIGITAL P.O, Box CS2008 (1-800-344-4825) Nashua, NH 03061 FAX: 603-884-5597 Puerto Rico Phone: 809-781-0505 Digital Equipment Corporation FAX: 809-749-8377 3 Digital Plaza, 1st Street Suite 200 Metro Office Park San Juan, Puerto Rico 00920 Canada Phone: 1-800-267-6215 Digital Equipment of Canada Ltd. FAX: 613-592-1946 100 Herzberg Road Kanata, Ontario, Canada K2K 2A6 Attn: DECdirect Sales International ~ Local Digital subsidiary or approved distributor Internal orders DTN 264-3030 U.S. Software Supply Business 603-884-3030 Digital Equipment Corporation FAX: 603-884-9690 10 Cotton Road Nashua, NH 03063-1260 MM 2841136 0033179 731) 3