LT1977 LINER | Alldatasheet
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■ High Voltage Power Conversion ■ 14V and 42V Automotive Systems ■ Industrial Power Systems ■ Distributed Power Systems ■ Battery-Powered Systems , LTC and LT are registered trademarks of Linear Technology Corporation. ■ Wide Input Range: 3.3V to 60V ■ 1.5A Peak Switch Current ■ Burst Mode Operation: 100µA Quiescent Current** ■ Low Shutdown Current: IQ < 1µA ■ Power Good Flag with Programmable Threshold ■ Load Dump Protection to 60V ■ 500kHz Switching Frequency ■ Saturating Switch Design: 0.2Ω On-Resistance ■ Peak Switch Current Maintained Over Full Duty Cycle Range* ■ 1.25V Feedback Reference Voltage ■ Easily Synchronizable ■ Soft-Start Capability ■ Small 16-Pin Thermally Enhanced TSSOP Package High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100µA Quiescent Current Burst Mode is a registered trademark of Linear Technology Corporation. *U.S. Patent 6,498,466 and 6,531,909 **See Burst Mode Operation section for conditions The LT 1977 is a 500kHz monolithic buck switching regulator that accepts input voltages up to 60V. A high efficiency 1.5A, 0.2Ω switch is included on the die along with all the necessary oscillator, control and logic cir- cuitry. Current mode topology is used for fast transient response and good loop stability. Innovative design techniques along with a new high volt- age process achieve high efficiency over a wide input range. Efficiency is maintained over a wide output current range by employing Burst Mode operation at low currents, utilizing the output to bias the internal circuitry, and by using a supply boost capacitor to fully saturate the power switch. Patented circuitry maintains peak switch current over the full duty cycle range.* Shutdown reduces input supply current to less than 1µA. External synchronization can be implemented by driving the SYNC pin with logic-level inputs. A single capacitor from the C SS pin to the output provides a controlled output voltage ramp (soft-start). The device also has a power good flag with a programmable threshold and time-out and thermal shutdown protection. The LT1977 is available in a 16-pin TSSOP package with exposed pad leadframe for low thermal resistance. The LT1976, a 200kHz reduced switch frequency version of the LT1977, is also available. See the Applications Information section for selection criteria between the LT1976 and LT1977. VIN SHDN BOOST LT1977 2.2µF 100V CER 330pF 0.1µF 0.1µF 10µH 1N4148 1µF SYNC CT GND 100µF 6.3V TANT V OUT 3.3V VIN 10MQ100N 1500pF 26k 165k 100k
1977 TA01
14V to 3.3V Step-Down Converter with 100µA No Load Quiescent Current Efficiency and Power Loss vs Load Current LOAD CURRENT (A) 0.0001 EFFICIENCY (%) POWER LOSS (W) 0.001 0.01 0.1 1
1977 TA02
0.001 0.01 0.1 VIN = 12V 3.3V EFFICIENCY TYPICAL POWER LOSS Supply Current vs Input Voltage INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 10 20 30 40
1977 F05
VOUT = 3.3V TA = 25°C DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U
(Note 1) Operating JunctionTemperature Range ORDER PART NUMBER Consult LTC Marketing for parts specified with wider operating temperature ranges. LT1977EFE LT1977IFE ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V unless otherwise noted. TJMAX = 125°C, θJA = 45°C/W, θJC(PAD) = 10°C/W EXPOSED PAD IS GND (PIN 17) MUST BE SOLDERED TO GND (PIN 8) FE PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW NC SW NC V IN NC BOOST CT GND PG SHDN SYNC PGFB FB V C BIAS C SS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VSHDN SHDN Threshold 1.15 1.3 1.45 V ISHDN SHDN Input Current SHDN = 12V ● 52 0 µA Minimum Input Voltage (Note 3) ● 2.4 3 V IVINS Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 µA Supply Sleep Current (Note 4) BIAS = 0V, FB = 1.35V ● 170 250 µA FB = 1.35V ● 45 75 µA IVIN Supply Quiescent Current BIAS = 0V, FB = 1.15V 4.10 mA BIAS = 5V, FB = 1.15V 3.25 mA Minimum BIAS Voltage (Note 5) ● 2.7 3 V IBIASS BIAS Sleep Current (Note 4) ● 110 180 µA IBIAS BIAS Quiescent Current SYNC = 3.3V 700 900 µA Minimum Boost Voltage (Note 6) I SW = 1.5A 1.8 V Input Boost Current (Note 7) I SW = 1.5A 40 mA VREF Reference Voltage (VREF) 3.3V < V VIN < 60V ● 1.225 1.25 1.275 V IFB FB Input Bias Current 75 200 nA EA Voltage Gain (Note 8) 900 V/V EA Voltage gm dI(VC)= ±10µA 450 650 900 µMho EA Source Current FB = 1.15V 20 40 55 µA EA Sink Current FB = 1.35V 15 30 40 µA VC to SW gm 3A / V VC High Clamp 2.1 2.2 2.4 V IPK SW Current Limit ● 1.5 2.4 3.5 A FE PART MARKING 1977EFE 1977IFE
ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switch On Resistance (Note 9) ● 0.2 0.4 Ω Switching Frequency ● 425 500 575 kHz Maximum Duty Cycle 86 92 % Minimum SYNC Amplitude 1.5 2.0 V SYNC Frequency Range 575 700 kHz SYNC Input Impedance 85 k Ω ICSS CSS Current Threshold (Note 10) 7 13 20 µA IPGFB PGFB Input Current 25 100 nA VPGFB PGFB Voltage Threshold (Note 11) ● 88 90 92 % ICT CT Source Current (Note 11) 2 3.6 5.5 µA CT Sink Current (Note 11) 1 2 mA VCT CT Voltage Threshold (Note 11) 1.16 1.2 1.26 V PG Leakage (Note 11) V PG = 12V 0.1 1 µA PG Sink Current (Note 11) PGFB = 1V, PG = 400mV 100 200 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1977EFE is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT1977IFE is guaranteed and tested over the full –40°C to 125°C operating junction temperature range. Note 3: Minimum input voltage is defined as the voltage where switching starts. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: Supply input current is the quiescent current drawn by the input pin. Its typical value depends on the voltage on the BIAS pin and operating state of the LT1977. With the BIAS pin at 0V, all of the quiescent current required to operate the LT1977 will be provided by the V IN pin. With the BIAS voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the BIAS pin. Supply sleep current is defined as the quiescent current during the “sleep” portion of Burst Mode operation. See Applications Information for determining application supply currents. Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I BIAS is sourced into the pin. Note 6: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 7: Boost current is the current flowing into the BOOST pin with the pin held 3.3V above input voltage. It flows only during switch on time. Note 8: Gain is measured with a VC swing from 1.15V to 750mV. Note 9: Switch on resistance is calculated by dividing VIN to SW voltage by the forced current (1.5A). See Typical Performance Characteristics for the graph of switch voltage at other currents. Note 10: The CSS threshold is defined as the value of current sourced into the CSS pin which results in an increase in sink current from the VC pin. See the Soft-Start section in Applications Information. Note 11: The PGFB threshold is defined as the percentage of VREF voltage which causes the current source output of the CT pin to change from sinking (below threshold) to sourcing current (above threshold). When sourcing current, the voltage on the CT pin rises until it is clamped internally. When the clamp is activated, the output of the PG pin will be set to a high impedance state. When the C T clamp is inactive the PG pin will be set active low with a current sink capability of 200µA.
TYPICAL PERFOR A CE CHARACTERISTICS UW FB Voltage Oscillator Frequency SHDN Threshold SHDN Pin Current Shutdown Supply Current Sleep Mode Supply Current Bias Sleep Current
1.20 VOLTAGE (V)
1.21 1.23 1.24 1.25 1.30 1.27 1.22 1.28 1.29 1.26 TEMPERATURE (°C) –50 0 50 75
1977 G01
–25 25 100 125 TEMPERATURE (°C) –50
450 FREQUENCY (kHz)
1977 G02
–25 25 100 125 VOLTAGE (V) 1.35
1977 G03
1.20 1.10 1.05 1.00 1.40 1.30 1.25 0.15 TEMPERATURE (°C) –50 0 50 75–25 25 100 125 SHDN VOLTAGE (V) CURRENT (µA) 1.5 2.5 3.5 10 20 30 40
1977 G04
4.5 5.5 1.0 2.0 3.0 4.0 5.0 TJ = 25°C CURRENT (µA)
1977 G05
TEMPERATURE (°C) –50 0 50 75–25 25 100 125 VIN = 60V VIN = 42V VIN = 12V CURRENT (µA)
1977 G06
VBIAS = 0V VBIAS = 5V TEMPERATURE (°C) –50 0 50 75–25 25 100 125 CURRENT (µA)
1977 G07
TEMPERATURE (°C) –50 0 50 75–25 25 100 125 PGFB Threshold VOLTAGE (V)
1977 G08
1.16 1.08 1.04 1.00 1.20 1.12 1.14 1.06 1.02 1.18 1.10 TEMPERATURE (°C) –50 0 50 75–25 25 100 125 PG Sink Current CURRENT (µA)
1977 G09
TEMPERATURE (°C) –50 0 50 75–25 25 100 125
TYPICAL PERFOR A CE CHARACTERISTICS UW Switch Peak Current Limit Soft-Start Current Threshold vs FB Voltage Frequency Foldback Percentage TEMPERATURE (°C) –50 1.5 PEAK SWITCH CURRENT (A)2.0 2.5 3.0 3.5 –25 –0 25 50
1977 G10
FB VOLTAGE (V) CURRENT (µA) 0.2 0.4 0.6 0.8
1977 G11
1.0 1.2 SOFT-START DEFEATED TJ = 25°C FB PIN VOLTAGE (V) FOLDBACK PERCENTAGE (%) 100
1977 G12
0.25 0.5 0.75 1.25 Switch On Voltage (VCESAT) LOAD CURRENT (A) –0.1 VOLTAGE (mV) 150 200 250 500 350 0.3 0.7 0.9
1977 G13
TJ = 125°C TJ = 25°C TJ = –50°C INPUT VOLTAGE (V) SUPPLY CURRENT (µA) 100 10 20 30 40 VOUT = 3.3V TA = 25°C Supply Current vs Input Voltage LOAD CURRENT (A) INPUT VOLTAGE (V) 6.0 7.0 8.0
1977 G19
5.0 4.0 5.5 6.5 7.5 4.5 3.5 3.0 0.25 0.5 0.75 1.25 VOUT = 5V START-UP RUNNING VOUT = 3.3V START-UP RUNNING Minimum Input Voltage Burst Mode Threshold vs Input Voltage INPUT VOLTAGE (V) LOAD CURRENT (mA) 300 400 500
1977 G20
7 9 11 1561 4 8 10 12 16 17 18 19 Burst Mode EXIT (INCREASING LOAD) Burst Mode ENTER (DECREASING LOAD) VOUT = 3.3V L = 10µH COUT = 100µF Minimum On Time Boost Current vs Load Current TEMPERATURE (°C) –50 ON TIME (ns) 150 200 250 500 350 0 50 75
1977 G21
–25 25 100 125 LOAD CURRENT = 0.5A LOAD CURRENT = 1A LOAD CURRENT (A) BOOST CURRENT (mA)
1977 G22
NC (Pins 1, 3, 5): No Connection. SW (Pin 2): The SW pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the SW pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is –0.8V. V IN (Pin 4): This is the collector of the on-chip power NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the path short from the V IN pin through the input bypass capacitor, through the catch diode back to SW. All trace inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. BOOST (Pin 6): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.2 Ω FET structure. C T (Pin 7): A capacitor on the CT pin determines the amount of delay time between the PGFB pin exceeding its thresh- old (V PGFB) and the PG pin set to a high impedance state. When the PGFB pin rises above VPGFB, current is sourced from the CT pin into the external capacitor. When the volt- age on the external capacitor reaches an internal clamp (VCT), the PG pin becomes a high impedance node. The resultant PG delay time is given by t = CCT • VCT/ICT. If the TYPICAL PERFOR A CE CHARACTERISTICS UW No Load 1A Step Response Step Response Burst Mode Operation Burst Mode Operation VOUT 20mV/DIV ISW 500mA/DIV VIN = 12V VOUT = 3.3V IQ = 100µA 2µs/DIV
1977 G15
VIN = 12V VOUT = 3.3V COUT = 100µF IDC = 0mA 500µs/DIV
1977 G17
VIN = 12V VOUT = 3.3V COUT = 100µF IDC = 350mA 500µs/DIV
1977 G18
VIN = 12V VOUT = 3.3V IQ = 100µA 5ms/DIV
1977 G14
voltage on the PGFB pin drops below V PGFB, CCT will be discharged rapidly to 0V and PG will be active low with a 200µA sink capability. If the CT pin is clamped (Power Good condition) during normal operation and SHDN is taken low, the CT pin will be discharged and a delay period will occur when SHDN is returned high. See the Power Good section in Applications Information for details. GND (Pins 8, 17): The GND pin connection acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground. Keep the path between the GND pin and the load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the copper ground plane to reduce thermal resistance (see Applications Information). CSS (Pin 9): A capacitor from the CSS pin to the regulated output voltage determines the output voltage ramp rate during start-up. When the current through the CSS capaci- tor exceeds the CSS threshold (ICSS), the voltage ramp of the output is limited. The CSS threshold is proportional to the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltage greater than 0.9V (typical). See Soft-Start section in Applications Information for details. BIAS (Pin 10): The BIAS pin is used to improve efficiency when operating at higher input voltages and light load current. Connecting this pin to the regulated output volt- age forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. This architecture increases efficiency espe- cially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3V. V C (Pin 11): The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally used for frequency compensation, but can also serve as a current clamp or control loop override. V C sits at about 0.45V for light loads and 2.2V at maximum load. During the sleep portion of Burst Mode operation, the VC pin is held at a voltage slightly below the burst threshold for better transient response. Driving the VC pin to ground will disable switching and place the IC into sleep mode. FB (Pin 12): The feedback pin is used to determine the output voltage using an external voltage divider from the output that generates 1.25V at the FB pin . When the FB pin drops below 0.9V, switching frequency is reduced, the SYNC function is disabled and output ramp rate control is enabled via the C SS pin. See the Feedback section in Applications Information for details. PGFB (PIN 13): The PGFB pin is the positive input to a comparator whose negative input is set at V PGFB. When PGFB is taken above VPGFB, current (ICSS) is sourced into the CT pin starting the PG delay period. When the voltage on the PGFB pin drops below VPGFB, the CT pin is rapidly discharged resetting the PG delay period. The PGFB volt- age is typically generated by a resistive divider from the regulated output or input supply. See Power Good section in Applications Information for details. SYNC (Pin 14): The SYNC pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 30% and 70% duty cycle. The synchronizing range is equal to maximum initial operating frequency up to 700kHz. When the voltage on the FB pin is below 0.9V the SYNC function is disabled. See the Synchronizing section in Applications Information for details. SHDN (Pin 15): The SHDN pin is used to turn off the regulator and to reduce input current to less than 1µA. The SHDN pin requires a voltage above 1.2V with a typical source current of 3µA to take the IC out of the shutdown state. PG (Pin 16): The PG pin is functional only when the SHDN pin is above its threshold, and is active low when the internal clamp on the C T pin is below its clamp level and high impedance when the clamp is active. The PG pin has a typical sink capability of 200 µA. See the Power Good section in Applications Information for details.
14 SYNC
10 BIAS
13 PGFB
Figure 1. LT1977 Block Diagram
output voltage). This improves efficiency. than the input voltage, allowing switch to be saturated. switches to Burst Mode operation in light load situations. input supply current to 45µA. physically smaller inductor. the LT1977’s input range will be similar to the LT1976. limitation will cause a dropout in regulation. Table 1. LT1976/LT1977 Comparison voltage and provide several overload protection features. both parts before committing to a final design.
not affect operation during normal load conditions. does not affect operation during normal load conditions. below 0.9V, the soft-start circuitry will become active.
1977 F02
Figure 2. Feedback Network
ing voltage resulting in erratic operation. voltage by 2:1 for high surge applications. typical solid tantalum surface mount capacitors. Table 3. Surface Mount Solid Tantalum Capacitor ESR are prone to failure if they undergo high surge currents. dead shorted, do not harm the capacitors.
to be small compared to ESR or ESL. switch current limit does not fall off at high duty cycles. subharmonic oscillations in current mode converters. Figure 3. LT1977 Ripple Voltage Waveform
1977 F03
APPLICATIO S I FOR ATIOWU UU The LT1977 is able to maintain peak switch current limit over the full duty cycle range by using patented circuitry to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides. Maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. The following formula assumes continuous mode operation, implying that the term on the right (I P-P/2) is less than IOUT. II VV V LfV I I OUT MAX PK OUT IN OUT IN () ( ) ( ) Discontinuous operation occurs when: I VV V LfVOUT DIS OUT IN OUT IN () ( ) ( )≤ () For VOUT = 5V, VIN = 8V and L = 15µH: I ee A OUT MAX() .– – .–. . = () ( ) () ( ) ( ) 15 58 5 2 15 6 500 3 8 1 5 0 125 1 375 Note that there is less load current available at the higher input voltage because inductor ripple current increases. At VIN = 15V, duty cycle is 33% and for the same set of conditions: I ee A OUT MAX() .– – .–. . = () ( ) () ( ) ( ) 15 51 5 5 2 15 6 500 3 15 15 02 2 12 8 To calculate actual peak switch current in continuous mode with a given set of conditions, use: II VV V LfV SW PK OUT OUT IN OUT IN =+ () () ( ) ( )2 If a small inductor is chosen which results in discontinous mode operation over the entire load range, the maximum load current is equal to: I If L V VV VOUT MAX PK IN OUT IN OUT () –= () ( ) ( ) () ( ) CHOOSING THE INDUCTOR For most applications the output inductor will fall in the range of 5µH to 33µH. Lower values are chosen to reduce physical size of the inductor. Higher values allow more output current because they reduce peak current seen by the LT1977 switch, which has a 1.5A limit. Higher values also reduce output ripple voltage and reduce core loss. When choosing an inductor you might have to consider maximum load current, core and copper losses, allow- able component height, output voltage ripple, EMI, fault current in the inductor, saturation and of course cost. The following procedure is suggested as a way of han- dling these somewhat complicated and conflicting requirements. 1. Choose a value in microhenries such that the maximum load current plus half the ripple current is less than the minimum peak switch current (I PK). Choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the LT1977 is designed to work well in either mode. Assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. If maxi- mum load current is 0.5A, for instance, a 0.5A inductor may not survive a continuous 2A overload condition. For applications with a duty cycle above 50%, the inductor value should be chosen to obtain an inductor ripple current of less than 40% of the peak switch current. 2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so don’t omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continuous mode of opera- tion, but it errs only slightly on the high side for discon- tinuous mode, so it can be used for all conditions.
- Decide if the design can tolerate an “open” core geom-
when the magnetic field radiation will be a problem.
- After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc. department if you feel uncertain about the final choice. low profile, surface mounting, etc.
- •≤ + where: f = switching frequency tON = switch on time VF = diode forward voltage VIN = Input voltage I • R = inductor I • R voltage drop If this condition is not observed, the current will not be limited at IPK but will cycle-by-cycle ratchet up to some higher value. Using the nominal LT1977 clock frequency of 500kHz, a VIN of 12V and a (VF + I • R) of say 0.7V, the maximum tON to maintain control would be approximately 116ns, an unacceptably short time. The solution to this dilemma is to slow down the oscillator to allow the current in the inductor to drop to a sufficiently
Table 4. Inductor Selection Criteria
- I PK current demanded by the VC pin, the LT1977 will skip the next on cycle effectively reducing the oscillator fre- quency by a factor of 2. These oscillator frequency reduc- tions during short-circuit conditions allow the LT1977 to maintain current control. SOFT-START For applications where [V IN/(VOUT + V F)] ratios > 10 or large input surge currents can’t be tolerated, the LT1977 soft-start feature should be used to control the output capacitor charge rate during start-up, or during recovery from an output short circuit thereby adding additional control over peak inductor current. The soft-start function limits the switch current via the V C pin to maintain a constant voltage ramp rate (dV/dt) at the output capacitor. A capacitor (C1 in Figure 2) from the C SS pin to the regulated output voltage determines the output voltage ramp rate. When the current through the C SS capacitor exceeds the CSS threshold (ICSS), the voltage ramp of the output capacitor is limited by reducing the VC pin voltage. The CSS threshold is proportional to the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltages greater than 0.9V (typical). The output dV/dt can be approximated by: dV dt I C CSS SS but actual values will vary due to start-up load conditions, compensation values and output capacitor selection. Burst Mode OPERATION To enhance efficiency at light loads, the LT1977 automati- cally switches to Burst Mode operation (see Typical Performance Characteristics) which keeps the output
Figure 4. VOUT dV/dt
1977 F04
and even 100V and are price competitive with other types. Figure 6. Burst Mode with Shutdown Pin Figure 5. IQ vs VIN Good section for further information. Table 5. Catch Diode Selection Criteria
ing the best diode for the application. enough, damage the IC itself. series with the BOOST diode (Figure 7a option). ripple and improve start-up operation. pin has an internal sink current of 3µA.
1977 F07
Figure 7. BOOST Pin Configurations
graphs of SHDN and VIN currents versus input voltage. Figure 8. Undervoltage Lockout
1977 F08
short-circuit conditions) the sync function is disabled. hazardous conditions for the SW pin.
lated output or input supply. PGFB) and the PG pin set to a high impedance state.
1977 F10
Figure 10. Power Good Circuits
Figure 12. Suggested Layout Figure 11. High Speed Switching Path
1977 F12
1977 F11
subharmonic like oscillation. continuous copper plate that runs under the LT1977 die. This is the best thermal path for heat out of the package. terminations will reduce any additional heating effects.
APPLICATIO S I FOR ATIOWU UU tr = (VIN/1.1)ns tf = (VIN/1.8)ns tIR = tIF = (IOUT/0.05)ns f = switch frequency Example: with VIN = 12V, VOUT = 5V and IOUT = 1A: Pe e TBD W PW PW SW BOOST Q += + = = () () = = () + () = −03 1 5 12 57 6 1 2 1 12 500 3 0 04 0 125 0 172 0 297 51 3 2 12 0 002 12 0 0015 5 0 003 0 033 . ./ .. . . / . .. . Total power dissipation is: PTOT = 0.297 + 0.065 + 0.033 = 0.40W Thermal resistance for the LT1977 package is influenced by the presence of internal or backside planes. With a full plane under the FE16 package, thermal resistance will be about 45°C/W. No plane will increase resistance to about 150°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: T J = TA + QJA (PTOT) With the FE16 package (Q JA = 45 °C/W) at an ambient temperature of 70°C: Input Voltage vs Operating Frequency Considerations The absolute maximum input supply voltage for the LT1977 is specified at 60V. This is based solely on internal semi- conductor junction breakdown effects. Due to internal power dissipation the actual maximum V IN achievable in a particular application may be less than this. A detailed theoretical basis for estimating internal power loss is given in the section Thermal Considerations. Note that AC switching loss is proportional to both operating frequency and output current. The majority of AC switch- ing loss is also proportional to the square of input voltage. For example, while the combination of V IN = 40V, VOUT = 5V at 1A and fOSC = 500kHz may be easily achievable, si- multaneously raising VIN to 60V and fOSC to 700kHz is not possible. Nevertheless, input voltage transients up to 60V can usually be accommodated, assuming the resulting increase in internal dissipation is of insufficient time dura- tion to raise die temperature significantly. A second consideration is control. A potential limitation occurs with a high step-down ratio of V IN to VOUT, as this requires a correspondingly narrow minimum switch on time. An approximate expression for this (assuming con- tinuous mode operation) is given as follows: tON(MIN) = VOUT + VF/VIN(fOSC) where: VIN = input voltage VOUT = output voltage VF = Schottky diode forward drop fOSC = switching frequency A potential control problem arises if the LT1977 is called upon to produce an on time shorter than it is able to produce. Feedback loop action will lower then reduce the V C control voltage to the point where some sort of cycle- skipping or Burst Mode behavior is exhibited. In summary: 1. Be aware that the simultaneous requirements of high V IN, high IOUT and high fOSC may not be achievable in practice due to internal dissipation. The Thermal Con- siderations section offers a basis to estimate internal power. In questionable cases a prototype supply should be built and exercised to verify acceptable operation. 2. The simultaneous requirements of high V IN, low VOUT and high fOSC can result in an unacceptably short minimum switch on time. Cycle skipping and/or Burst Mode be- havior will result causing an increase in output voltage ripple while maintaining the correct output voltage. FREQUENCY COMPENSATION Before starting on the theoretical analysis of frequency response the following should be remembered—the worse
circuits. Read the Layout Considerations section first. inductor. The basic regulator loop is shown in Figure 12. amplifier and the power stage. capacitor and a typical 100µF tantalum output capacitor. PS Unity Gain Freq = 3/(2π • 100µF) = 4.7kHz. sponse will generally improve but two effects limit its value. the output voltage monitored for a well-damped behavior. Figure 14. Overall Loop Response
1977 F14
Figure 13. Model for Loop Response
1977 F13
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTIO U 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BC FE16 (BC) TSSOP 0204 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 13 4 5 6 7 8 10 9 4.90 – 5.10* (.193 – .201) 16 1514 13 12 11 1.10 (.0433) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 2.94 (.116) 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT 0.45 ±0.05
0.65 BSC
4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004 LT/TP 0604 1K PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1074/LT1074HV 4.4A (I OUT), 100kHz, High Efficiency Step-Down DC/DC Converters V IN: 7.3V to 45V/64V, VOUT(MIN) = 2.21V, IQ = 8.5mA, ISD < 10µA, DD5/7, TO220-5/7 LT1076/LT1076HV 1.6A (I OUT), 100kHz, High Efficiency Step-Down DC/DC Converters V IN: 7.3V to 45V/64V, VOUT(MIN) = 2.21V, IQ = 8.5mA, ISD < 10µA, DD5/7, TO220-5/7 LT1676 60V, 440mA (I OUT), 100kHz, High Efficiency Step-Down DC/DC V IN: 7.4V to 60V, VOUT(MIN) = 1.24V, IQ = 3.2mA, Converter I SD < 2.5µA, S8 LT1765 25V, 3A (I OUT), 1.25MHz, High Efficiency Step-Down DC/DC V IN: 3V to 25V, VOUT(MIN) = 1.20V, IQ = 1mA, ISD < 15µA, Converter SO-8, TSSOP16/E LT1766 60V, 1.2A (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 25µA, TSSOP16E LT1767 25V, 1.5A (I OUT), 1.25MHz, High Efficiency Step-Down DC/DC V IN: 3V to 25V, VOUT(MIN) = 1.20V, IQ = 1mA, ISD < 6µA, Converter MS8E LT1776 40V, 550mA (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 7.4V to 40V, VOUT(MIN) = 1.24V, IQ = 3.2mA, Converter I SD < 30µA, N8, S8 LTC®1875 1.5A (I OUT), 550kHz, Synchronous Step-Down DC/DC Converter V IN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 15µA, ISD < 1µA, TSSOP16 LT1940 Dual 1.2A (I OUT), 1.1MHz, High Efficiency Step-Down DC/DC V IN: 3V to 25V, VOUT(MIN) = 1.2V, IQ = 3.8mA, MS10 Converter LT1956 60V, 1.2A (I OUT), 500kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 25µA, TSSOP16E LT1976 60V, 1.5A (I OUT), 200kHz High Efficiency Step-Down DC/DC V IN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP16E Converter LT3010 80V, 50mA, Low Noise Linear Regulator V IN: 1.5V to 80V, VOUT(MIN) = 1.28V, IQ = 30µA, ISD < 1µA, MS8E LTC3407 Dual 600mA (I OUT), 1.5MHz, High Efficiency Step-Down DC/DC V IN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, MS10 Converter LTC3412 2.5A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter V IN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, TSSOP16E LTC3414 4A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter V IN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64µA, ISD < 1µA, TSSOP20E LT3430 60V, 2.5A (I OUT), 200kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 30µA, TSSOP16E LT3431 60V, 2.5A (I OUT), 500kHz, High Efficiency Step-Down DC/DC V IN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, Converter I SD < 30µA, TSSOP16E LT3433 60V, 400mA (I OUT), 200kHz, Buck-Boost DC/DC Converter V IN: 5V to 60V, VOUT: 3.3V to 20V, IQ = 100µA, TSSOP16E LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers V IN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 670µA, ISD < 20µA, QFN-32, SSOP-28