NI6583R NI | Alldatasheet

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NI 6583R User Guide and Specifications The NI 6583R is a single-ended and differential signaling device designed to work in conjunction with your NI FlexRIO™ FPGA module. The NI 6583 is available in two versions: one with low-voltage differential signals (LVDS) and another with multipoint low-voltage differential signals (MLVDS). The term, differential, in this document refers to both LVDS and MLVDS signals unless otherwise specified. This document contains signal information and specifications for the NI 6583R, which is composed of an NI FlexRIO FPGA module and the NI 6583. This document also contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA example VI and how to create and run your own LabVIEW project with the NI 6583R.

Contents

Note Before configuring your NI 6583R, you must install the appropriate software and hardware. instructions. Figure 1 shows an example of a properly connected NI FlexRIO device. Figure 1. NI 6583R FPGA module. NI 6583 refers only to your NI 6583 adapter module.

Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set. Figure 2. How to Use Your NI FlexRIO Documentation Set Table 1. NI FlexRIO Documentation Locations and Descriptions hardware kit and from the Start Menu. hardware kit and from the Start Menu. specifications for your adapter module. ni.com/ipnet Contains LabVIEW FPGA functions and intellectual property to share. ni.com/flexrio Contains product information and data sheets for NI FlexRIO devices.

  • These documents are also available at ni.com/manuals.

and NI SHB12X-B12X cable (192344-01), the NI 6583 pinout is reversed at the end connector. For example, the signal shown on pin 1 shown in Figure 3 maps to pin 73 at the end connector. Table 2 contains pin location and single-ended signal information for DDC A on the NI 6583. Table 2. NI 6583 DDC A Connector Pins DDC CLK OUT 33 Clock Terminal for the single-ended exported Sample clock. Ground Ground reference for signals.

Table 3 contains pin location and differential signal information for DDC B on the NI 6583. Table 3. NI 6583 DDC B Connector Pins DDC CLK OUT+ 65 Clock Positive terminal for the differential exported Sample clock. DDC CLK OUT– 66 Clock Negative terminal for the differential exported Sample clock. Data Positive bidirectional digital I/O data channels 0 through 15. PFI <1..3>+ 2, 5, 8 Control Positive bidirectional digital I/O trigger channels 1 through 3. PFI <1..3>– 3, 6, 9 Control Negative bidirectional digital I/O trigger channels 1 through 3. Ground Ground reference for signals.

Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals

Note For the DIO and PFI lines, drive the GPIO Direction high for output and low for input. For CLK OUT, drive the GPIO Direction high for enable and low for disable. Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals (Continued)

Table 5. NI 6583 Differential Signals and NI FlexRIO FPGA Module Signals

NI 6583R User Guide and Specifications 12 ni.com Connecting Cables and Accessories Use an NI SHC68-C68-D4 shielded cable (NI part number 781013-01) for connections to the DDC A connector. The NI SHC68-C68-D4 is designed for single-ended, high-speed digital signal transmission. The cable is shielded, with individual microcoaxial 50 Ω lines for each signal. Use an SHB12X-B12X shielded cable (NI part number 192344-01) for connections to the DDC B connector. This cable is designed for differential, high-speed digital signal transmission. Caution The NI 6583R must be operated with shielded cables and shielded accessories to ensure compliance with the Electromagnetic Compatibility (EMC) requirements defined in the Specifications section of this document. Do not use unshielded cables or accessories unless they are installed in a shielded enclosure with properly designed and shielded input/output ports and connected to the NI 6583R using a shielded cable. If unshielded cables or accessories are not properly installed and shielded, the EMC specifications for the NI 6583R are no longer guaranteed. The following NI cables and accessories are not properly shielded for EMC-compliant use with the NI 6583:  NI CB-2162 single-ended di gital I/O accessory  NI SHC68-H1X38 high-speed digita l flying-leads cable accessory  NI SMA-2164 prototyping accessory for NI 656X  NI SHB12X-H3X24 differential fl ying-lead/LA cable for HSDIO Using Accessories Note Whether you use NI cables and accessories or design your own, you should properly terminate cables to avoid improper measurements caused by signal reflections, overshoot, and undershoot. Single-Ended Accessories NI recommends using the NI CB-2162 single-ended digital I/O accessory to access the signals on the 68-pin DDC A connector and to terminate the DIO channels. The NI CB-2162 also provides a platform for circuit prototyping and DUT testing. The NI CB-2162 is specifically designed for use with single-ended devices. For more information about the NI CB-2162, refer to theNI CB-2162 User Guide. NI also offers the NI SMB-2163 breakout box for National Instruments single-ended digital waveform generator/analyzers. The NI SMB-2163 offers coaxial SMB connectors for each channel on the DDC A connector, providing an easy way to connect to other devices for testing and debugging. For more information about the NI SMB-2163, refer to the NI SMB-2163 User Guide.

NI SMB-2163, respectively, using the NI SHC68-C68-D4 cable. Figure 8. Connecting the NI CB-2162 Accessory Figure 9. Connecting the NI SMB-2163 Accessory

1 PXI/PXI Expre ss Chassis with NI 6583R

3 NI CB-2162 Accessory

3 NI SHC68-C68-D4 Cable

50 MHz Digital I/O

devices and circuits for interfacing, testing, or analysis. well. The following figure shows the single-ended digital flying lead cable. Figure 10. Single-Ended Flying Lead Cable Parts Locator Diagram

NI SMA-2164, refer to the NI SMA-2164 User Guide. Figure 11. Connecting the NI SMA-2164 Accessory

1 PXI/PXI Expre ss Chassis with an NI 65 83R

3 NI SMA-2164

100 MHz LVDS DIO

applications. This cable is shown in Figure 12. Figure 12. NI SHB12X-H3X24 Flying Lead Cable InfiniBand connector, you can also purchase this connector. and SHB12X-B12X shielded cable (192344-01), the NI6583 pinout is reversed at the end connector. and Connector Pinouts section in this document for more pinout information.

2 DDC B Connector

3 Removeable Sleeving

© National Instruments Corporation 17 N I 6583R User Guide and Specifications Using Your NI 6583R with a LabVIEW FPGA Example VI Note You must install the software before doing this example. Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for more information about installing your software. The NI FlexRIO Adapter Module Support installation software includes a variety of example projects to help get you started creating your LabVIEW FPGA program. This section demonstrates how to use an existing LabVIEW FPGA example project to generate and acquire samples with the NI 6583R. This example requires the NI SHC68-C68-D4 and the NI SHB12X-B12X shielded cables and the appropriate accessories for your device. Refer to the Using Accessories section of this document for more information about accessories. Note The examples available for your device are dependent on the version of the software and driver you are using. For information about which software versions are compatible with your device, visit ni.com/info and enter rdsoftwareversion as the Info Code. Each NI 6583 example project includes the following items:  A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware  A VI that runs on Windows that interacts with the LabVIEW FPGA VI Note In the LabVIEW FPGA Module software, NI FlexRIO adapter modules are referred to as IO Modules. Complete the following steps to run an example VI that generates a waveform on the even channels of your device and then acquires that waveform on the odd channels of your device. Hardware Configuration 1. For single-ended acquisi tion and generation, connect one end of the NI SHC68-C68-D4 shielded cable to DDC A on the NI 6583 front panel and one end to a single-ended accessory device. For differential acquisition and generation, connect one end of the NI SHB12X-B12X shielded cable to DDC B on the NI 6583 front panel and one end to a differential accessory device. Refer to the Using Accessories section of this document for more information about appropriate accessories for your device. 2. On your accessory device s, connect the first eight even channels (DIO <0..14>) to the first eight odd channels (DIO <1..15>). Software Configuration 1. Launch LabVIEW. 2. In the Getting Started window, click Find Examples to display the NI Example Finder. 3. In the NI Example Finder window, select Hardware Input and Output»FlexRIO» IO Modules»NI 6583. 4. Select NI 6583 Finite Acquisition and Generation - Simple.lvproj. 5. In the Project Explorer window, open NI 6583 Acquisition and Generation Simple (Host).vi under My Computer. The host VI opens. The VI uses the NI PXI-7952R as the FPGA target. If you are not using an NI PXI-7952R, complete the following steps to change the FPGA target. Note All example projects are configured for RIO0. If your device is not RIO0, you must update the target device name by right-clicking your device in the Project Explorer window, selecting Properties, and entering the correct target device name in the Resource box.

a. Select Window»Show Block Diagram to open the VI block diagram. select Configure Open FPGA VI Reference. e. Click OK in the Configure Open FPGA VI Reference window.

  1. On the front panel, select appropriate values in the Num Samples, Generation Mode, Generation

Constant, and DDC A Voltage Level controls.

  1. Click the Run button to run the VI. The NI 6583R generates a waveform on the even channels of

generated and acquired waveforms match, then the DDC x Verified? indicator illuminates. Figure 13. NI 6583 Acquisition and Generation Simple (Host) VI Front Panel

© National Instruments Corporation 19 N I 6583R User Guide and Specifications Creating a LabVIEW Project and Running a VI on an FPGA Target This section demonstrates how to create a LabVIEW project, an FPGA VI, and a host VI that acquires and generates single-ended data on the NI 6583R. This exercise also demonstrates how to compile the FPGA VI on your target and run a VI on the host machine. Note Disconnect all signals from the NI 6583R connectors before running this VI. Creating a Project 1. Launch LabVIEW, or if LabVIE W is already running, select File»New. 2. In the New dialog box, select Project»Empty Project. Click OK. The new project opens in the Project Explorer window. 3. Save the project as Static RW with Voltage.lvproj. Creating an FPGA Target VI 1. In the Project Explorer window, right-click My Computer and select New»Targets and Devices. 2. In the Add Targets and Devices on My Computer window, select the Existing Target or Device button and expand the FPGA Target. The target is displayed. 3. Select your device and click OK. The target and target properties are loaded into the project tree. 4. In the Project Explorer window, right-click the FPGA target and select New»VI. A blank VI opens. 5. Select Window»Show Block Diagram to open the block diagram window. 6. In the Project Explorer window, select FPGA Target (RIOx, PXI-79xxR). 7. Right-click IO Module and select Properties. In the General category, select National Instruments: NI 6583, and you can see the available component-level IP (CLIP) for the NI 6583 in the Component Level IP pane. If the category information is dimmed, select the Enable IO Module checkbox. Note For more information about CLIP items for the NI 6583, refer to the NI 6583 Component-Level Intellectual Property (CLIP) section of this document. 8. Select NI 6583 Basic Connector to use the connector-based CLIP. Click OK. 9. In the Project Explorer window, expand the IO Module (NI 6583 : NI 6583 Basic Connector) tree view. 10. Select SE_Data_Dir, SE_Data_Rd, SE_Data_Wr, Voltage_Family, Set_Voltage_Family, and Set_Voltage_Done, and drag them onto the block diagram. Tip If you hold down the <Ctrl> key, you can select multiple options at one time. 11. Add a While Loop around all six data nodes, as shown in Figure 14. 12. Wire a False constant to the stop condition of the While Loop. 13. Wire indicators from the output terminals of the IO Module\\SE_Data_Rd and IO Module\\Set_Voltage_Done nodes. 14. Wire controls from the input terminals of the IO Module\\Set_Voltage_Family, IO Module\\SE_Data_Dir, and IO Module\\SE_Data_Wr nodes. 15. On the Functions palette, choose Select a VI. 16. In the Select the VI to Open window, navigate to Program Files\\National Instruments\\ <LabVIEW x>\\examples\\FlexRIO\\IO Modules\\NI 6583\\FiniteAcqGenSimple.

  1. Select NI 6583 Voltage Level. Click OK to drag and place the file on your block diagram.
  2. Right-click the V oltage Level control and select Change to Control.
  3. Wire the V oltage Level control to the IO Module\\Voltage_Family node, as shown in Figure 14.
  4. Add a case structure around the IO Module\\SE_Data_Dir, IO Module\\SE_Data_Rd, and

and output access while the voltage is changing. Your block diagram should now resemble the block diagram in Figure 14. Figure 14. Static RW with Voltage (FPGA).vi Block Diagram

  1. Save the VI as Static RW with Voltage (FPGA).vi.
  2. In the Project Explorer window under My Computer, expand the tree view for your device,

The Generating Intermediate Files window opens and displays the compilation progress.

  1. When the compilation finishes, click the Stop Server button.
  2. Click OK in the Successful Compile Report window. Close the VI without saving changes.

© National Instruments Corporation 21 N I 6583R User Guide and Specifications Creating a Host VI 1. In the Project Explorer window, right-click My Computer and select New»VI. A blank VI opens. 2. Select Window»Show Block Diagram to open the block diagram window. 3. Place the Open FPGA VI Reference function (from the FPGA Interface palette) on the block diagram. 4. Right-click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference. 5. In the Configure Open FPGA VI Reference window, select the VI button. 6. In the Select VI window that opens, select the Static RW with Voltage (FPGA).vi under your device, and click OK. 7. Select the Run the FPGA VI checkbox if it is not already selected. 8. Click OK in the Configure Open FPGA VI Reference window. The new target name appears under the Open FPGA VI Reference function on the block diagram. 9. Add a While Loop to the block diagram, as shown in Figure 15. 10. Add the Read/Write Control function (from the FPGA Interface palette) inside the While Loop. 11. Wire the Open FPGA VI Reference function FPGA VI Reference Out indicator to the FPGA VI Reference In control on the Read/Write Control function. 12. Wire the Open FPGA VI Reference function error out indicator to the Read/Write Control function error in control. 13. Click the Unselected input of Read/Write Control function and select Voltage Level. 14. Wire a control to the Voltage Level FPGA input terminal. 15. Expand the bottom of the Read/Write Control f unction to expose five more nodes. Click the new nodes and select each of the remaining items. 16. Wire indicators from the IO Module\\SE_Data_Rd and IO Module\\Set_Voltage_Done output terminals. 17. Wire controls to the IO Module\\SE_Data_Dir, IO Module\\SE_Data_Wr, and IO Module\\Set_Voltage_Family input terminals. 18. Add the Close FPGA VI Reference function ( from the FPGA Interface palette) outside the While Loop. 19. Wire the Read/Write Control function FPGA VI Reference Out indicator to the Close FPGA VI Reference function FPGA VI Reference In control. 20. Wire the Read/Write Control error out parameter to the Close FPGA VI Reference error in parameter.

  1. Right-click the stop condition of the While Loop and add an control. Label this control Stop.

Your block diagram should now resemble the block diagram in Figure 15. Figure 15. Data RW (Host).vi Block Diagram

  1. Save the VI as Static RW with Voltage (Host).vi.
  2. Select Window»Show Front Panel to open the front panel of the VI.
  3. Click the Run button to run the VI.
  4. Enter a number in the IO Module\\SE_Data_Dir control to set the direction of the channels. A

logic 0 indicates that the channel is an input, and a logic 1 indicates that the channel is an output.

  1. Connect an output channel to an input ch annel or to a digital multimeter (DMM).
  2. Change the logic state of the output channel and ensure that the corresponding logic state on an

input channel or on the DMM also changes.

  1. Change the voltage on the output channel using the IO Module\\Voltage_Level control and ensure

IO Module\\Voltage_Level control to the desired I/O voltage.

  1. Click the Stop button on the front panel and close the VI.

Table 6. IO Module\\Set Voltage Control

NI 6583R User Guide and Specifications 24 ni.com The NI 6583 ships with socketed CLIP options that you can use to add module I/O to the LabVIEW project. The NI 6583 has the following compatible CLIP options:  NI 6583 Basic Channel CLIP—Provides read/write access to all single-ended lines on DDC A and all differential lines on DDC B using a simple channel-based interface. Each I/O line has a direction control signal. This CLIP provides a clock signal for export on each connector. The clock input data from the NI 6583 is passed to LabVIEW FPGA for use in the FPGA VI. This CLIP also allows for individual clock output inversion.  NI 6583 Basic Connector CLIP—Provides read/write access to all single-ended lines on DDC A and all differential lines on DDC B. The individual data lines for DDC A are accessed using a U32 data type and the individual data lines on DDC B are accessed using a U16 data type in LabVIEW FPGA. Each I/O line has a direction signal. This CLIP also allows for individual clock output inversion.  NI 6583 DDR Connector CLIP—Provides read/write access to all single-ended lines on DDC A and all differential lines on DDC B. The individual data lines for DDC A are accessed using a U32 data type and the individual data lines on DDC B are accessed using a U16 data type in LabVIEW FPGA. Data from each edge of the clock is presented as “rising” and “falling.” Each I/O line has a direction control signal. This CLIP also allows for individual clock output inversion. Caution All CLIP options include intellectual property for voltage and direction control. The voltage is controlled with a 10-bit DAC code or with an enumerated data type. You must use this intellectual property to prevent damage to your NI 6583 and to your system. Refer to the NI FlexRIO Help for more information about NI FlexRIO CLIP items, configuring the NI 6583 with a socketed CLIP, and a list of available socketed CLIP signals.

© National Instruments Corporation 25 N I 6583R User Guide and Specifications Specifications This section lists the specifications of the NI FlexRIO adapter module (NI 6583). Pair these specifications with the specifications listed in the NI FlexRIO FPGA Module Installation Guide and Specifications. For more information about safety and electromagnetic compatibility, refer to the Read Me First: Safety and Electromagnetic Compatibility document included in your hardware kit or available at ni.com/manuals. These specifications are nominal at 25 °C unless otherwise noted. Channel Specifications One InfiniBand (DDC B for differential I/O) (32 single-ended data, 3 single-ended PFI); 19 total on DDC B (16 differential data, 3 differential PFI) Single-ended Channels (DDC A) (Consistent with TI part number SN74A VC2T245) Note The provided CLIP items have the ability to program the voltage level by logic families (1.2V, input and output signals. V CC =3 . 6 3V Note You must set the voltage after every power cycle prior to performing any operations. Typical data rate

current not exceeding 30 mA. Note Internal diode clamps may begin conducting outside the 0 V to VCC range. Table 7. Generation Voltage Levels (100 μA load) Table 8. Acquisition Voltage Threshold

voltage between −0.5 V and 4.0 V . Note Internal diode clamps may begin conducting outside the 0 V to 3.3 V range. voltage between −0.5 V and 4.0 V . Note Internal diode clamps may begin conducting outside the 0 V to 3.3 V range. voltage between −1.4 V and 3.8 V . Table 9. Generation Voltage Levels (50 Ω total load) Table 10. Acquisition Voltage Levels Table 11. Generation Voltage Levels (50 Ω total load)

NI 6583R User Guide and Specifications 28 ni.com Acquisition (Data, STROBE, and PFI Channels) Power Maximum power requirements when toggling half of the data channels at 100% data rate and half at 50% data rate. +12 V is maximized when generating, and +3.3 V is maximized when acquiring. Physical one 73-pin InfiniBand connector Environmental The NI 6583 is intended for indoor use only. Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2. Tested in accordance with IEC 60068-2-56. Storage environment Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2. Tested in accordance with IEC 60068-2-56. Note Clean the device with a soft, non-metallic brush. Make sure that the device is completely dry and free from contaminants before returning it to service.

© National Instruments Corporation 29 N I 6583R User Guide and Specifications Glossary Maximum and minimum specifications are warranted not to exceed these values within certain operating conditions and include the effects of temperature and uncertainty unless otherwise noted. Typical specifications are unwarranted values that are representative of a majority (3σ) of units within certain operating conditions and include the effects of temperature and uncertainty unless otherwise noted. Characteristic specifications are unwarranted values that are representative of an average unit operating at room temperature. Nominal specifications are unwarranted values that are relevant to the use of the product and convey the expected performance of the product. Compliance and Certifications Safety This product meets the requirements of the following standards of safety for electrical equipment for measurement, control, and laboratory use:  IEC 61010-1, EN 61010-1  UL 61010-1, CSA 61010-1 Note For UL and other safety certifications, refer to the product label or the Online Product Certification section. Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:  EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity  EN 55011 (CISPR 11): Group 1, Class A emissions  AS/NZS CISPR 11: Group 1, Class A emissions  FCC 47 CFR Part 15B: Class A emissions  ICES-001: Class A emissions Note For the standards applied to assess the EMC of this product, refer to the Online Product Certification section. Note For EMC compliance, operate this device according to the device documentation and only with the NI SHC68-C68-D4 (1 m) shielded cable, the NI SHB12X-B12X (1 m) shielded cable, and shielded accessories. Caution To ensure the specified EMC performance, when using the MLVDS version of the NI 6583, you must attach EMI gaskets (NI part number 746228-01) to both sides of your NI 6583 before use. CE Compliance This product meets the essential requirements of applicable European Directives as follows:  2006/95/EC; Low-V oltage Directive (safety)  2004/108/EC; Electromagnetic Co mpatibility Directive (EMC)

NI 6583R User Guide and Specifications 30 ni.com Online Product Certification Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column. Environmental Management NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers. For additional environmental information, refer to the NI and the Environment Web page at ni.com/ environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document. Waste Electrical and Electronic Equipment (WEEE) EU Customers At the end of the product life cycle, all products must be sent to a WEEE recycling center. For more information about WEEE recycling centers, National Instruments WEEE initiatives, and compliance with WEEE Directive 2002/96/EC on Waste and Electronic Equipment, visit ni.com/environment/weee. Where to Go for Support The National Instruments Web site is your complete resource for technical support. At ni.com/ support you have access to everything from troubleshooting and application development self-help resources to email and phone assistance from NI Application Engineers. National Instruments corporate headquarters is located at 11500 North Mopac Expressway, Austin, Texas, 78759-3504. National Instruments also has offices located around the world to help address your support needs. For telephone support in the United States, create your service request at ni.com/ support and follow the calling instructions or dial 512 795 8248. For telephone support outside the United States, visit the Worldwide Offices section of ni.com/niglobal to access the branch office Web sites, which provide up-to-date contact information, support phone numbers, email addresses, and current events. ⊩ ˄Ё೑ RoHS˅ Ё೑ᅶ᠋ National InstrumentsՓ⫼ᶤѯ᳝ᆇ⠽䋼ᣛҸ (RoHS)DŽ Ѣ National Instruments Ё೑ RoHSᙃˈ䇋ⱏᔩ ni.com/environment/rohs_chinaDŽ (For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

LabVIEW, National Instruments, NI, ni.com, the National Instruments corporate logo, and the Eagle logo are trademarks of National Instruments Corporation. Refer to the Trademark Information at ni.com/trademarks for other National Instruments trademarks. Other product and company names mentioned herein are trademarks or trade names of their respective companies. For patents covering National Instruments products/technology, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents. Refer to the Export Compliance Information at ni.com/legal/ export-compliance for the National Instruments global trade compliance policy. © 2010–2011 National Instruments Corporation. All rights reserved. 375506C-01 Feb11