17531A | DigiCamel IC Datasheet

Online Datasheet

Read 17531A online.

MPC17531A_08 FREESCALE | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 20

Technical content

Features

Low Total RDS(ON) 0.8 W (Typ), 1.2 Ω (Max) @ 25°C Output Current 0.7 A (DC) Shoot-Through Current Protection Circuit PWM Control Input Frequency up to 200 kHz Built-In Charge Pump Circuit Low Power Consumption Undervoltage Detection and Shutdown Circuit Power Save Mode with Current Draw ≤ 2.0 µA Pb-Free Packaging Designated by Suffix Codes EV and EP Figure 1. 17531A Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MPC17531AEV/EL -20°C to 65°C 20 VMFP MPC17531AEP/R2 24 QFN QFN SUFFIX EP SUFFIX (PB-FREE) 98ARL10577D 24-TERMINAL QFN CRES C1L C1H C2L C2H IN2B PSAVE IN2A IN1A OUT2B OUT2A OUT1B OUT1A VM GND MCU IN1B 3.0 V 5.0 V 17531A Bipolar Step Motor N S VDD

2 Freescale Semiconductor

Figure 2. 17531A Simplified Internal Block Diagram

Figure 3. 17531A, 20-Terminal VMFP Connections Table 1. 17531A, 20-Terminal VMFP Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10. 1 VDD Logic Supply Control circuit power supply terminal. 2 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 6, Truth Table, page 9). 3 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 6, Truth Table, page 9). 4 PSAVE Power Save Logic input controlling power save mode. 5 OUT2A H-Bridge Output 2A Output A of H-Bridge channel 2. 6 PGND1 Power Ground 1 High-current power ground 1. 7 OUT1A H-Bridge Output 1A Output A of H-Bridge channel 1. 8 VM1 Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). 9 CRES Predriver Power Supply Internal triple charge pump output as predriver power supply. 10 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole). 11 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole). 12 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole). 13 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole). 14 OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1. 15 PGND2 Power Ground 2 High-current power ground 2. 16 OUT2B H-Bridge Output 2B Output B of H-Bridge channel 2. 17 VM2 Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). 18 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 6, Truth Table, page 9). 19 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 6, Truth Table, page 9). 20 LGND Logic Ground Low-current logic signal ground.

4 Freescale Semiconductor

Figure 4. 17531A, 24-Terminal QFN Connections Table 2. 17531A, 24-Terminal QFN Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10. 1, 6, 7, 17 NC No Connect This terminal is not used. 2 PSAVE Power Save Logic input controlling power save mode. 3 OUT2A H-Bridge Output 2A Output A of H-Bridge channel 2. 4 PGND1 Power Ground 1 High-current power ground 1. 5 OUT1A H-Bridge Output 1A Output A of H-Bridge channel 1. 8 VM1 Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). 9 CRES Predriver Power Supply Internal triple charge pump output as pre-driver power supply. 10 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole). 11 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole). 12 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole). 13 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole). 14 OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1. 15 PGND2 Power Ground 2 High-current power ground 2. 16 OUT2B H-Bridge Output 2B Output B of H-Bridge channel 2. 18 VM2 Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). 19 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 6, Truth Table, page 9). 20 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 6, Truth Table, page 9). 21 LGND Logic Ground Low-current logic signal ground. 22 VDD Logic Supply Control circuit power supply terminal. 23 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 6, Truth Table, page 9). 24 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).

Table 3. Maximum Ratings permanent damage to the device.

T A = 25°C. Pulse width = 10 ms at 200 ms intervals.
ESD1 testing is performed in accor dance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
ESD2 testing is performed in acco rdance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
For QFN only, mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits

may cause malfunction or permanent damage to the device.

6 Freescale Semiconductor

Table 4. Static Electrical Characteristics noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Gate drive voltage VCRES is applied from an external source. 2 x VDD + VM must be < VCRES max (13.5 V).
No internal charge pump used. VCRES is applied from an external source.
IQVDD includes the current to pre-driver circuit.
I VDD includes the current to predriver circuit at fIN = 100 kHz.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. VCRES is

applied from an external source. 2 x VDD + VM must be < VCRES max (13.5 V).

Table 4. Static Electrical Characteristics (continued) noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

8 Freescale Semiconductor

Table 5. Dynamic Electrical Characteristics noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
Output load is 8.0 Ω DC.