16SP100M

LM2747 NSC | Alldatasheet

Document overview

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Technical content

Features

n ±1% feedback voltage accuracy over temperature n Switching frequency from 50 kHz to 1 MHz n Switching frequency synchronize range 250 kHz to 1 MHz n Startup with a pre-biased output load n Power stage input voltage from 1V to 14V n Control stage input voltage from 3V to 6V n Output voltage adjustable down to 0.6V n Power Good flag and shutdown n Output overvoltage and undervoltage detection n Low-side adjustable current sensing n Adjustable soft-start n Tracking and sequencing with shutdown and soft start pins n TSSOP-14 package

Applications

n Down Conversion from 3.3V n Cable Modem, DSL and ADSL n Laser Jet and Ink Jet Printers n Low Voltage Power Modules n DSP, ASIC, Core and I/O Typical Application 20150901 March 2006 LM2747 Synchronous Buck Controller with Pre-bias Startup, and Optional Clock Synchronization © 2006 National Semiconductor Corporation DS201509 www.national.com

θJA = 155˚C/W

Ordering Information

94 Units on Rail

2500 Units on Tape and Reel

BOOT (Pin 1) - Bootstrap pin. This is the supply rail for the high-side gate driver. When the high-side MOSFET turns on, the voltage on this pin should be at least one gate threshold above the regulator input voltage VIN to properly turn on the MOSFET. See MOSFET Gate Drivers in the Application Information section for more details on how to select MOS- FETs. LG (Pin 2) - Low-gate drive pin. This is the gate drive for the low-side N-channel MOSFET. This signal is interlocked with the high-side gate drive HG (Pin 14), so as to avoid shoot- through. PGND (Pins 3, 13) - Power ground. This is also the ground for the low-side MOSFET driver. Both the pins must be connected together on the PCB and form a ground plane, which is usually also the system ground. SGND (Pin 4) - Signal ground. It should be connected appropriately to the ground plane with due regard to good layout practices in switching power regulator circuits. VCC (Pin 5) Supply rail for the control sections of the IC. PWGD (Pin 6) - Power Good pin. This is an open drain output, which is typically meant to be connected to VCC or any other low voltage source through a pull-up resistor. Choose the pull-up resistor so that the current going into this pin is kept below 1 mA. A recommended value for the pull-up resistor is 100 kΩfor most applications. The voltage on this pin is thus pulled low under output undervoltage or overvolt- age fault conditions and also under input UVLO. ISEN (Pin 7) - Current limit threshold setting pin. This sources a fixed 40 µA current. A resistor of appropriate value should be connected between this pin and the drain of the low-side MOSFET (switch node). The minimum value for this resistor is 1 kΩ. EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine the duty cycle. This pin is necessary for compensating the control loop. SS/TRACK (Pin 9) - Soft-start and tracking pin. This pin is internally connected to the non-inverting input of the error amplifier during soft-start, and in fact any time the SS/ TRACK pin voltage happens to be below the internal refer- ence voltage. For the basic soft-start function, a capacitor of minimum value 1 nF is connected from this pin to ground. To track the rising ramp of another power supply’s output, con- nect a resistor divider from the output of that supply to this pin as described in Application Information. FB (Pin 10) - Feedback pin. This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating the control loop. FREQ/SYNC (Pin 11) - Frequency adjust pin. The switching frequency is set by connecting a resistor of suitable value between this pin and ground. Some typical values (rounded up to the nearest standard values) are 150 kΩfor 200 kHz, 100 kΩfor 300 kHz, 51.1 kΩfor 500 kHz, 18.7 kΩfor 1 MHz. This pin is also used to synchronize to an external clock within the range of 250kHz to 1MHz. SD (Pin 12) - IC shutdown pin. Pull this pin to VCC to ensure the IC is enabled. Connect to ground to disable the IC. Under shutdown, both high-side and low-side drives are off. This pin also features a precision threshold for power supply sequencing purposes, as well as a low threshold to ensure minimal quiescent current. HG (Pin 14) - High-gate drive pin. This is the gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG (Pin 2) to avoid shoot-through. LM2747 www.national.com

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC -0.3 to 7V BOOT Voltage -0.3 to 18V ISEN -0.3 to 14V FREQ/SYNC Voltage -0.5 to VCC + 0.3V All other pins -0.3 to VCC + 0.3V Junction Temperature 150˚C Storage Temperature −65˚C to 150˚C Soldering Information Lead Temperature (soldering, 10sec) 260˚C Infrared or Convection (20sec) 235˚C ESD Rating (Note 3) 2kV Operating Ratings Supply Voltage Range, VCC (Note 2) 3V to 6V BOOT Voltage Range 1V to 17V Junction Temperature Range (TJ) −40˚C to +125˚C Thermal Resistance (θJA) 155˚C/W

Electrical Characteristics

VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25˚C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max Units VFB FB Pin Voltage VCC = 3V to 6V 0.594 0.6 0.606 V VON UVLO Thresholds VCC Rising VCC Falling 2.79 2.42 V IQ_VCC Operating VCC Current VCC = 3.3V, VSD = 3.3V fSW = 600 kHz 1.1 1.7 2.3 mA VCC = 5V, VSD = 3.3V fSW = 600 kHz 1.3 2.6 Shutdown VCC Current VCC = 3.3V, VSD = 0V µA tPWGD1 PWGD Pin Response Time VFB Rising µs tPWGD2 PWGD Pin Response Time VFB Falling µs ISS-ON SS Pin Source Current VSS = 0V µA ISS-OC SS Pin Sink Current During Over Current VSS = 2.0V µA ISEN-TH ISEN Pin Source Current Trip Point µA IFB FB Pin Current Sourcing nA ERROR AMPLIFIER GBW Error Amplifier Unity Gain Bandwidth MHz G Error Amplifier DC Gain 118 dB SR Error Amplifier Slew Rate V/µs IEAO EAO Pin Current Sourcing and Sinking Capability mA VEAO Error Amplifier Output Voltage Minimum V Maximum 2.2 V LM2747 www.national.com

(Continued) VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25˚C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max Units GATE DRIVE IQ-BOOT BOOT Pin Quiescent Current VBOOT = 12V, VSD = 0 µA RHG_UP High-Side MOSFET Driver Pull-Up ON resistance VBOOT = 5V @ 350 mA Sourcing 2.7 Ω RHG_DN High-Side MOSFET Driver Pull-Down ON resistance 350 mA Sinking 0.8 Ω RLG_UP Low-Side MOSFET Driver Pull-Up ON resistance VBOOT = 5V @ 350 mA Sourcing 2.7 Ω RLG_DN Low-Side MOSFET Driver Pull-Down ON resistance 350 mA Sinking 0.8 Ω OSCILLATOR fSW PWM Frequency RFADJ = 750 kΩ kHz RFADJ = 100 kΩ 300 RFADJ = 42.2 kΩ 475 600 725 RFADJ = 18.7 kΩ 1000 External Synchronizing Signal Frequency Voltage Swing = 0V to VCC 250 1000 SYNCL Synchronization Signal Low Threshold fSW = 250 kHz to 1 MHz V SYNCH Synchronization Signal High Threshold fSW = 250 kHz to 1 MHz V DMAX Max High-Side Duty Cycle fSW = 300 kHz fSW = 600 kHz fSW = 1 MHz LOGIC INPUTS AND OUTPUTS VSTBY-IH Standby High Trip Point VFB = 0.575V, VBOOT = 3.3V VSD Rising 1.1 V VSTBY-IL Standby Low Trip Point VFB = 0.575V, VBOOT = 3.3V VSD Falling 0.232 V VSD-IH SD Pin Logic High Trip Point VSD Rising 1.3 V VSD-IL SD Pin Logic Low Trip Point VSD Falling 0.8 V VPWGD-TH-LO PWGD Pin Trip Points VFB Falling 0.408 0.434 0.457 V VPWGD-TH-HI PWGD Pin Trip Points VFB Rising 0.677 0.710 0.742 V VPWGD-HYS PWGD Hysteresis VFB Falling VFB Rising mV Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device operates correctly. Operating Ratings do not imply guaranteed performance limits. Note 2: The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the external MOSFET. See the MOSFET GATE DRIVERS section under Application Information for further details. Note 3: ESD using the human body model which is a 100pF capacitor discharged through a 1.5 kΩresistor into each pin. LM2747 www.national.com

Typical Performance Characteristics Efficiency (VOUT = 1.2V) VCC = 3.3V, fSW = 1 MHz Internal Reference Voltage vs Temperature 20150940 20150958 Frequency vs Temperature Output Voltage vs Output Current 20150960 20150956 Switch Waveforms VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 3A, CSS = 12 nF, fSW = 1 MHz Start-Up (Full-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 3A, CSS = 12 nF, fSW = 1 MHz 20150946 20150948 LM2747 www.national.com

Typical Performance Characteristics (Continued) Start-Up (No-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V CSS = 12 nF, fSW = 1 MHz Shutdown (Full-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 3A, CSS = 12 nF, fSW = 1 MHz 20150949 20150950 Load Transient Response VCC = 3.3V, VIN = 14V, VOUT = 1.2V fSW = 1 MHz Line Transient Response (VIN = 3V to 9V) VCC = 3.3V, VOUT = 1.2V IOUT = 2A, fSW = 1 MHz 20150953 20150954 Frequency vs. Frequency Adjust Resistor Maximum Duty Cycle vs Frequency VCC = 3.3V 20150955 20150992 LM2747 www.national.com

Typical Performance Characteristics (Continued) Maximum Duty Cycle vs VCC fSW = 600 kHz Maximum Duty Cycle vs VCC fSW = 1 MHz 20150993 20150994 LM2747 www.national.com

Application Information

The LM2747 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high efficiency buck convert- ers. It has output shutdown (SD), input undervoltage lock-out (UVLO) mode and power good (PWGD) flag (based on overvoltage and undervoltage detection). The overvoltage and undervoltage signals are OR-gated to drive the power good signal and provide a logic signal to the system if the output voltage goes out of regulation. Current limit is achieved by sensing the voltage VDS across the low side MOSFET. The LM2747 is also able to start-up with the output pre-biased with a load and allows for the switching frequency to be synchronized with an external clock source. START UP/SOFT-START When VCC exceeds 2.79V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the LM2747 reference voltage of 0.6V. At this point the reference voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the length of the soft-start period, and can be approximated by: Where CSS is in µF and tSS is in ms. During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of 0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage monitoring starts. SETTING THE OUTPUT VOLTAGE The LM2747 regulates the output voltage by controlling the duty cycle of the high side and low side MOSFETs (see Typical Application Circuit).The equation governing output voltage is: SETTING THE SWITCHING FREQUENCY During fixed-frequency mode of operation the PWM fre- quency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, RFADJ, between the FREQ/SYNC pin and ground. The resistance needed for a desired frequency LM2747 www.national.com

(Continued) POWER GOOD SIGNAL The open drain output on the Power Good pin needs a pull-up resistor to a low voltage source. The pull-up resistor should be chosen so that the current going into the Power Good pin is less than 1 mA. A 100 kΩresistor is recom- mended for most applications. The Power Good signal is an OR-gated flag which takes into account both output overvoltage and undervoltage condi- tions. If the feedback pin (FB) voltage is 18% above its nominal value (118% x VFB = 0.708V) or falls 28% below that value (72% x VFB = 0.42V) the Power Good flag goes low. The Power Good flag can be used to signal other circuits that the output voltage has fallen out of regulation, however the switching of the LM2747 continues regardless of the state of the Power Good signal. The Power Good flag will return to logic high whenever the feedback pin voltage is between 72% and 118% of 0.6V. UVLO The 2.79V turn-on threshold on VCC has a built in hysteresis of about 300 mV. If VCC drops below 2.42V, the chip defi- nitely enters UVLO mode. UVLO consists of turning off the top and bottom MOSFETS and remaining in that condition until VCC rises above 2.79V. As with normal shutdown initi- ated by the SD pin, the soft-start capacitor is discharged through an internal MOSFET, ensuring that the next start-up will be controlled by the soft-start circuitry. CURRENT LIMIT Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. The RDSON of the MOSFET is a known value; hence the current through the MOSFET can be determined as: VDS = IOUT x RDSON The current through the low-side MOSFET while it is on is also the falling portion of the inductor current. The current limit threshold is determined by an external resistor, RCS, connected between the switching node and the ISEN pin. A constant current (ISEN-TH) of 40 µA typical is forced through RCS, causing a fixed voltage drop. This fixed voltage is compared against VDS and if the latter is higher, the current limit of the chip has been reached. To obtain a more accurate value for RCS you must consider the operating values of RDSON and ISEN-TH at their operating temperatures in your application and the effect of slight parameter differences from part to part. RCS can be found by using the following equation using the RDSON value of the low side MOSFET at it’s expected hot temperature and the absolute minimum value expected over the full temperature range for the for the ISEN-TH which is 25 µA: RCS = RDSON-HOT x ILIM / ISEN-TH For example, a conservative 15A current limit in a 10A design with a RDSON-HOT of 10 mΩwould require a 6 kΩ resistor. The minimum value for RCS in any application is 1 kΩ. Because current sensing is done across the low-side MOSFET, no minimum high-side on-time is necessary. The LM2747 enters current limit mode if the inductor current exceeds the current limit threshold at the point where the high-side MOSFET turns off and the low-side MOSFET turns on. (The point of peak inductor current, see Figure 12). Note that in normal operation mode the high-side MOSFET al- ways turns on at the beginning of a clock cycle. In current limit mode, by contrast, the high-side MOSFET on-pulse is skipped. This causes inductor current to fall. Unlike a normal operation switching cycle, however, in a current limit mode switching cycle the high-side MOSFET will turn on as soon as inductor current has fallen to the current limit threshold. The LM2747 will continue to skip high-side MOSFET pulses until the inductor current peak is below the current limit threshold, at which point the system resumes normal opera- tion. Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current sensing is only allowed to limit the current during the converter off-time, when inductor current is falling. Therefore in a typi- cal current limit plot the valleys are normally well defined, but the peaks are variable, according to the duty cycle. The PWM error amplifier and comparator control the off-pulse of the high-side MOSFET, even during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be calculated with the following equation: Where TSW is the inverse of switching frequency fSW. The 200 ns term represents the minimum off-time of the duty cycle, which ensures enough time for correct operation of the current sensing circuitry. In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC also dis- charges the soft-start capacitor through a fixed 90 µA sink. The output of the LM2747 internal error amplifier is limited by the voltage on the soft-start capacitor. Hence, discharging the soft-start capacitor reduces the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the output voltage if the current limit conditions last for an extended time. Output inductor current 20150988 FIGURE 12. Current Limit Threshold

(Continued) will be reduced in turn to a flat level equal to the current limit threshold. The third benefit of the soft-start capacitor dis- charge is a smooth, controlled ramp of output voltage when the current limit condition is cleared. SHUTDOWN If the shutdown pin is pulled low, (below 0.8V) the LM2747 enters shutdown mode, and discharges the soft-start capaci- tor through a MOSFET switch. The high and low-side MOS- FETs are turned off. The LM2747 remains in this state as long as VSD sees a logic low (see the Electrical Character- istics table). To assure proper IC start-up the shutdown pin should not be left floating. For normal operation this pin should be connected directly to VCC or to another voltage between 1.3V to VCC (see the Electrical Characteristics table). DESIGN CONSIDERATIONS The following is a design procedure for all the components needed to create the Typical Application Circuit shown on the front page. This design converts 3.3V (VIN) to 1.2V (VOUT) at a maximum load of 4A with an efficiency of 89% and a switching frequency of 300 kHz. The same procedures can be followed to create many other designs with varying input voltages, output voltages, and load currents. Input Capacitor The input capacitors in a Buck converter are subjected to high stress due to the input current trapezoidal waveform. Input capacitors are selected for their ripple current capabil- ity and their ability to withstand the heat generated since that ripple current passes through their ESR. Input rms ripple current is approximately: Where duty cycle D = VOUT/VIN. The power dissipated by each input capacitor is: where n is the number of paralleled capacitors, and ESR is the equivalent series resistance of each capacitor. The equa- tion above indicates that power loss in each capacitor de- creases rapidly as the number of input capacitors increases. The worst-case ripple for a Buck converter occurs during full load and when the duty cycle (D) is 0.5. For this 3.3V to 1.2V design the duty cycle is 0.364. For a 4A maximum load the ripple current is 1.92A. Output Inductor The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the square wave created by the switching action and for controlling the output current ripple (∆IOUT). The inductance is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the more quickly the con- verter can respond to transients in the load current. How- ever, as shown in the efficiency calculations, a smaller in- ductor requires a higher switching frequency to maintain the same level of output current ripple. An increase in frequency can mean increasing loss in the MOSFETs due to the charg- ing and discharging of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The equation for output inductor selection is: L = 1.6 µH Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency, and as- sumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + (0.5 x ∆IOUT)) = 4.8A, for a 4A design. The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak, and has a direct current resistance (DCR) of 12 mΩ. After selecting the Coilcraft DO3316P-222P for the output inductor, actual inductor current ripple should be re- calculated with the selected inductance value, as this infor- mation is needed to select the output capacitor. Re- arranging the equation used to select inductance yields the following: VIN(MAX) is assumed to be 10% above the steady state input voltage, or 3.6V at VIN = 3.3V. The re-calculated current ripple will then be 1.2A. This gives a peak inductor/switch current will be 4.6A. Output Capacitor The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control the output voltage ripple (∆VOUT) and to supply load current during fast load transients. In this example the output current is 4A and the expected type of capacitor is an aluminum electrolytic, as with the input capacitors. Other possibilities include ceramic, tanta- lum, and solid electrolyte capacitors, however the ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums tend to be more expensive than aluminum electrolytic. Aluminum ca- pacitors tend to have very high capacitance and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the switching frequency. The large capacitance means that at the switching fre- quency, the ESR is dominant, hence the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the maximum ESR based on the desired output voltage ripple, ∆VOUT and the designed out- put current ripple, ∆IOUT, is: LM2747 www.national.com

(Continued) In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor cur- rent ripple, the required maximum ESR is 20 mΩ. The Sanyo 4SP560M electrolytic capacitor will give an equivalent ESR of 14 mΩ. The capacitance of 560 µF is enough to supply energy even to meet severe load transient demands. MOSFETs Selection of the power MOSFETs is governed by a trade-off between cost, size, and efficiency. One method is to deter- mine the maximum cost that can be endured, and then select the most efficient device that fits that price. Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the bench result is not guaran- teed, however. Single-channel buck regulators that use a controller IC and discrete MOSFETs tend to be most efficient for output currents of 2 to 10A. Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching loss. Conduction, or I2R loss, is approximately: PC = D (IO 2 x RDSON-HI x 1.3) (High-Side MOSFET) PC = (1 - D) x (IO 2 x RDSON-LO x 1.3) (Low-Side MOSFET) In the above equations the factor 1.3 accounts for the in- crease in MOSFET RDSON due to heating. Alternatively, the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON Vs. Temperature curves in the MOSFET datasheets. Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is approximated as: PGC = n x (VDD) x QG x fSW where ‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel), VDD is the driving voltage (see MOSFET Gate Drivers section) and QGS is the gate charge of the MOSFET. If different types of MOSFETs are used, the ‘n’ term can be ignored and their gate charges simply summed to form a cumulative QG. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM2747, and not in the MOSFET itself. Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which both cur- rent and voltage are present in the channel of the MOSFET. It can be approximated as: PSW = 0.5 x VIN x IO x (tr + tf) x fSW where tr and tf are the rise and fall times of the MOSFET. Switching loss occurs in the high-side MOSFET only. For this example, the maximum drain-to-source voltage ap- plied to either MOSFET is 3.6V. The maximum drive voltage at the gate of the high-side MOSFET is 3.1V, and the maxi- mum drive voltage for the low-side MOSFET is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is needed. For designs of 5A and under, dual MOSFETs in SO-8 provide a good trade-off between size, cost, and efficiency. Support Components CIN2 - A small (0.1 to 1 µF) ceramic capacitor should be placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET (dual MOS- FETs make this easy). This capacitor should be X5R type dielectric or better. RCC, CCC- These are standard filter components designed to ensure smooth DC voltage for the chip supply. RCC should be 1 to 10Ω. CCC should 1 µF, X5R type or better. CBOOT- Bootstrap capacitor, typically 100 nF. RPULL-UP – This is a standard pull-up resistor for the open- drain power good signal (PWGD). The recommended value is 100 kΩconnected to VCC. If this feature is not necessary, the resistor can be omitted. D1 - A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and low-side drivers. The MBR0520 or BAT54 work well in most designs. RCS - Resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT + (0.5 x ∆IOUT)) of 4.8A, a safe setting would be 6A. (This is below the satura- tion current of the output inductor, which is 7A.) Following the equation from the Current Limit section, a 1.3 kΩresistor should be used. RFADJ - This resistor is used to set the switching frequency of the chip. The resistor value is approximated from the Fre- quency vs Frequency Adjust Resistor curve in the Typical Performance Characteristics section. For 300 kHz operation, a 100 kΩresistor should be used. CSS - The soft-start capacitor depends on the user require- ments and is calculated based on the equation given in the section titled START UP/SOFT-START. Therefore, for a 7 ms delay, a 12 nF capacitor is suitable. Control Loop Compensation The LM2747 uses voltage-mode (‘VM’) PWM control to cor- rect changes in output voltage due to line and load tran- sients. VM requires careful small signal compensation of the control loop for achieving high bandwidth and good phase margin. The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the LM2747 is a 9 MHz op-amp used in the classic inverting configuration. Figure 13 shows the regulator and control loop components. LM2747 www.national.com

(Continued) In practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest ±10% capacitor values above what are suggested for CC1 and CC2, the closest ±10% capacitor value below the suggestion for CC3, and the closest ±1% resistor values below the sugges- tions for RC1, RC2. Note that if the suggested value for RC2 is less than 100Ω, it should be replaced by a short circuit. Following this guideline, the compensation components will be: CC1 = 27 pF±10%, CC2 = 820 pF±10% RC2 = 2.55 kΩ±1% The transfer function of the compensation block can be derived by considering the compensation components as impedance blocks ZF and ZI around an inverting op-amp: As with the generic equation, GEA-ACTUAL must be modified to take into account the limited bandwidth of the error ampli- fier. The result is: The total control loop transfer function H is equal to the power stage transfer function multiplied by the error amplifier transfer function. H = GPS x HEA The bandwidth and phase margin can be read graphically from Bode plots of HEA as shown in Figure 16. The bandwidth of this example circuit is 59 kHz, with a phase margin of 60˚. EFFICIENCY CALCULATIONS The following is a sample calculation. A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the Output Power (POUT) loss and the Total Power (PTOTAL) loss: The Output Power (POUT) for the Typical Application Circuit design is (1.2V x 4A) = 4.8W. The Total Power (PTOTAL), with an efficiency calculation to complement the design, is shown below. The majority of the power losses are due to the low side and high side MOSFET’s losses. The losses in any MOSFET are group of switching (PSW) and conduction losses (PCND). PFET = PSW + PCND = 61.38 mW + 270.42 mW PFET = 331.8 mW FET Switching Loss (PSW) PSW = PSW(ON) + PSW(OFF) PSW = 0.5 x VIN x IOUT x (tr + tf) x fSW 20150985 20150986 FIGURE 16. Overall Loop Gain and Phase

(Continued) PSW = 0.5 x 3.3V x 4A x 300 kHz x 31 ns PSW = 61.38 mW The FDS6898A has a typical turn-on rise time tr and turn-off fall time tf of 15 ns and 16 ns, respectively. The switching losses for this type of dual N-Channel MOSFETs are 0.061W. FET Conduction Loss (PCND) PCND = PCND1 + PCND2 PCND1 = I2 OUT x RDS(ON) x k x D PCND2 = I2 OUT x RDS(ON) x k x (1-D) RDS(ON) = 13 mΩand the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to heat- ing. PCND1 = (4A)2 x 13 mΩx 1.3 x 0.364 PCND2 = (4A)2 x 13 mΩx 1.3 x (1 - 0.364) PCND = 98.42 mW + 172 mW = 270.42 mW There are few additional losses that are taken into account: IC Operating Loss (PIC) PIC = IQ_VCC x VCC, where IQ-VCC is the typical operating VCC current PIC= 1.7 mA x 3.3V = 5.61 mW FET Gate Charging Loss (PGATE) PGATE = n x VCC x QGS x fSW PGATE = 2 x 3.3V x 3 nC x 300 kHz PGATE = 5.94 mW The value n is the total number of FETs used and QGS is the typical gate-source charge value, which is 3 nC. For the FDS6898A the gate charging loss is 5.94 mW. Input Capacitor Loss (PCAP) where, Here n is the number of paralleled capacitors, ESR is the equivalent series resistance of each, and PCAP is the dissi- pation in each. So for example if we use only one input capacitor of 24 mΩ. PCAP = 88.8 mW Output Inductor Loss (PIND) PIND = I2 OUT x DCR where DCR is the DC resistance. Therefore, for example PIND = (4A)2 x 11 mΩ PIND = 176 mW Total System Efficiency PTOTAL = PFET + PIC + PGATE + PCAP + PIND LM2747 www.national.com

DESCRIPTION

20V, 10 mΩ@ 4.5V, 16nC Fairchild MBR0520LTI Schottky Diode SOD-123 DO3316P-472 Inductor 4.7 µH, 4.8Arms 18 mΩ Coilcraft CIN1 16SP100M Aluminum Electrolytic 10mm x 6mm 100 µF, 16V, 2.89Arms Sanyo CO1 6SP220M Aluminum Electrolytic 10mm x 6mm 220 µF, 6.3V 3.1Arms Sanyo CCC, CBOOT, CIN2, CO2 VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay CC3 VJ0805Y332KXXA Capacitor 0805 3300 pF, 10% Vishay CSS VJ0805A123KXAA Capacitor 0805 12 nF, 10% Vishay CC2 VJ0805A821KXAA Capacitor 0805 820 pF 10% Vishay CC1 VJ0805A220KXAA Capacitor 0805 22 pF, 10% Vishay RFB2 CRCW08051002F Resistor 0805 10.0 kΩ1% Vishay RFB1 CRCW08054991F Resistor 0805 4.99 kΩ1% Vishay RFADJ CRCW08051003F Resistor 0805 100 kΩ1% Vishay RC2 CRCW08052101F Resistor 0805 2.1 kΩ1% Vishay RCS CRCW08052101F Resistor 0805 2.1 kΩ1% Vishay RCC CRCW080510R0F Resistor 0805 10.0Ω1% Vishay RC1 CRCW08055492F Resistor 0805 54.9 kΩ1% Vishay RPULL-UP CRCW08051003J Resistor 0805 100 kΩ5% Vishay CCLK VJ0805A560KXAA Capacitor 0805 56 pF, 10% Vishay 20150932 FIGURE 17. 3.3V to 1.8V @ 2A, fSW = 300 kHz

(Continued) PART PART NUMBER TYPE PACKAGE 20V, 10 mΩ@ 4.5V, 16 nC Fairchild MBR0520LTI Schottky Diode SOD-123 DO3316P-682 Inductor 6.8 µH, 4.4Arms, 27 mΩCoilcraft CIN1 16SP100M Aluminum Electrolytic 10mm x 6mm 100 µF, 16V, 2.89Arms Sanyo CO1 10SP56M Aluminum Electrolytic 6.3mm x 6mm 56 µF, 10V 1.7Arms Sanyo CCC, CBOOT, CIN2, CO2 VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay CC3 VJ0805Y182KXXA Capacitor 0805 1800 pF, 10% Vishay CSS VJ0805A123KXAA Capacitor 0805 12 nF, 10% Vishay CC2 VJ0805A821KXAA Capacitor 0805 820 pF 10% Vishay CC1 VJ0805A330KXAA Capacitor 0805 33 pF, 10% Vishay RFB2 CRCW08051002F Resistor 0805 10.0 kΩ1% Vishay RFB1 CRCW08053161F Resistor 0805 3.16 kΩ1% Vishay RFADJ CRCW08051003F Resistor 0805 100 kΩ1% Vishay RC2 CRCW08051301F Resistor 0805 1.3 kΩ1% Vishay RCS CRCW08052101F Resistor 0805 2.1 kΩ1% Vishay RCC CRCW080510R0F Resistor 0805 10.0Ω1% Vishay RC1 CRCW08053322F Resistor 0805 33.2 kΩ1% Vishay RPULL-UP CRCW08051003J Resistor 0805 100 kΩ5% Vishay CCLK VJ0805A560KXAA Capacitor 0805 56 pF, 10% Vishay 20150933 FIGURE 18. 5V to 2.5V @ 2A, fSW = 300 kHz

(Continued) PART PART NUMBER TYPE PACKAGE 20V, 10 mΩ@ 4.5V, 16 nC Fairchild MBR0520LTI Schottky Diode SOD-123 DO3316P-332 Inductor 3.3 µH, 5.4Arms 15 mΩ Coilcraft CIN1 16SP100M Aluminum Electrolytic 10mm x 6mm 100 µF, 16V, 2.89Arms Sanyo CO1 6SP220M Aluminum Electrolytic 10mm x 6mm 220 µF, 6.3V 3.1Arms Sanyo CCC, CBOOT, CIN2, CO2 VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay CC3 VJ0805Y222KXXA Capacitor 0805 2200 pF, 10% Vishay CSS VJ0805A123KXAA Capacitor 0805 12 nF, 10% Vishay CC2 VJ0805Y332KXXA Capacitor 0805 3300 pF 10% Vishay CC1 VJ0805A820KXAA Capacitor 0805 82 pF, 10% Vishay RFB2 CRCW08051002F Resistor 0805 10.0 kΩ1% Vishay RFB1 CRCW08052211F Resistor 0805 2.21 kΩ1% Vishay RFADJ CRCW08051003F Resistor 0805 100 kΩ1% Vishay RC2 CRCW08052611F Resistor 0805 2.61 kΩ1% Vishay RCS CRCW08054121F Resistor 0805 4.12 kΩ1% Vishay RCC CRCW080510R0F Resistor 0805 10.0Ω1% Vishay RC1 CRCW08051272F Resistor 0805 12.7kΩ1% Vishay RPULL-UP CRCW08051003J Resistor 0805 100 kΩ5% Vishay CCLK VJ0805A560KXAA Capacitor 0805 56 pF, 10% Vishay 20150934 FIGURE 19. 12V to 3.3V @ 4A, fSW = 300kHz

inches (millimeters) unless otherwise noted TSSOP-14 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LM2747 Synchronous Buck Controller with Pre-bias Startup, and Optional Clock Synchronization