Microcontroller

16C62X

Microchip Technology

EPROM-Based 8-Bit CMOS Microcontroller 1998

Manufacturer: Microchip Technology

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Ó 1998 Microchip Technology Inc. Preliminary DS30235G-page 1 Devices included in this data sheet: Referred to collectively as PIC16C62X .

PIC16C620 • PIC16C620A
PIC16C621 • PIC16C621A
PIC16C622 • PIC16C622A
PIC16CR620A High Performance RISC CPU:
Only 35 instructions to learn
All single-cycle instructions (200 ns), except for program branches which are two-cycle
Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes Peripheral Features:
13 I/O pins with individual direction control
High current sink/source for direct LED drive
Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference REF ) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs can be output signals
Timer0: 8-bit timer/counter with 8-bit programmable prescaler Special Microcontroller Features:
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Brown-out Reset
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Device Program Memory Data Memory PIC16C620 512 80 PIC16C620A 512 96 PIC16CR620A 512 96 PIC16C621 1K 80 PIC16C621A 1K 96 PIC16C622 2K 128 PIC16C622A 2K 128 Pin Diagrams Special Microcontroller Features (cont’d)
Programmable code protection
Power saving SLEEP mode
Selectable oscillator options
Serial in-circuit programming (via two pins)
Four user programmable ID locations CMOS Technology:
Low-power, high-speed CMOS EPROM technol- ogy
Fully static design
Wide operating voltage range - PIC16C62X - 2.5V to 6.0V - PIC16C62XA - 2.5V to 5.5V - PIC16CR620A - 2.0V to 5.5V
Commercial, industrial and extended tempera- ture range
Low power consumption - 15 m A typical @ 3.0V, 32 kHz - < 1.0 m A typical standby current @ 3.0V RA1/AN1 RA0/AN0 OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 OSC1/CLKIN RA2/AN2/V REF RA3/AN3 MCLR/ VPP VSS RB0/INT RB1 RB2 RB3 RA4/T0CKI PIC16C62X RA1/AN1 RA0/AN0 OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 OSC1/CLKIN RA2/AN2/V REF RA3/AN3 MCLR/ VPP VSS VSS RB0/INT RB1 RB2 RA4/T0CKI RB3RB3 VDD PDIP, SOIC, Windowed CERDIP SSOP PIC16C62X EPROM-Based 8-Bit CMOS Microcontroller PIC16C62X

Ó 1998 Microchip Technology Inc. De vice Differences Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. De vice Voltage Range Oscillator Process Technology (Microns) PIC16C620 2.5 - 6.0 See Note 1 0.9 PIC16C621 2.5 - 6.0 See Note 1 0.9 PIC16C622 2.5 - 6.0 See Note 1 0.9 PIC16C620A 2.5 - 5.5 See Note 1 0.7 PIC16CR620A 2.0 - 5.5 See Note 1 0.7 PIC16C621A 2.5 - 5.5 See Note 1 0.7 PIC16C622A 2.5 - 5.5 See Note 1 0.7

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 3 PIC16C62X Table of Contents To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our W orldwide W eb site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended w orkarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

Microchip’s W orldwide W eb site; http://www.microchip.com
Your local Microchip sales ofﬁce (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales ofﬁce or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Corrections to this Data Sheet W e constantly strive to improve the quality of all our products and documentation. W e have spent a great deal of time to ensure that this document is correct. How ever, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please:
Fill out and mail in the reader response form in the back of this data sheet.
E-mail us at webmaster@microchip.com. W e appreciate your assistance in making this a better document.

Ó 1998 Microchip Technology Inc. NOTES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 5 PIC16C62X

1.0 GENERAL DESCRIPTION

The PIC16C62X are 18 and 20 Pin R OM/ EPR OM-based members of the versatile PICmi- cro™ family of low-cost, high-performance , CMOS , fully-static, 8-bit microcontrollers. All PICmicro™ m icrocontrollers employ an advanced RISC architecture. The PIC16C62X have enhanced core features, eight-level deep stack, and multiple inter- nal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program br anches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance . PIC16C62X m icrocontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C620 A, PIC16C621 A and PIC16CR620A have 96 bytes of RAM. The PIC16C622 (A) has 128 bytes of RAM. Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmab le prescaler. In addition, the PIC16C62X adds tw o analog comparators with a programmab le on-chip voltage reference mod- ule. The comparator module is ideally suited for appli- cations requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc). PIC16C62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing pow er con- sumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes pow er consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (pow er-down) mode offers pow er savings. The user can wake up the chip from SLEEP through several external and internal interrupts and reset. A highly reliable W atchdog Timer with its own on-chip RC oscillator provides protection against software lock- up. A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmab le (OTP) version is suitable for production in any volume. Table 1-1 sho ws the features of the PIC16C62X mid-range microcontroller fam ilies. A simpliﬁed block diagram of the PIC16C62X is shown in Figure 3-1. The PIC16C62X series ﬁt perfectly in applications ranging from battery chargers to low-pow er remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse gener- ation, timers, etc.) extremely fast and convenient. The small footprint packages mak e this microcontroller series perfect for all applications with space limitations. Low-cost, low-pow er, high-performance , ease of use and I/O ﬂexibility make the PIC16C62X very versatile.

1.1 Family and Upward Compatibility

Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to PIC16C62X family of devices (Appendix B). The PIC16C62X family ﬁlls the niche for users wanting to migrate up from the PIC16C5X family and not needing various peripheral features of other members of the PIC16XX mid-range microcontroller family.

1.2 De velopment Support

The PIC16C62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit em ulator, a low-cost development programmer and a full-featured programmer . A “C” compiler and fuzzy logic support tools are also available.

Ó 1998 Microchip Technology Inc. TAB LE 1-1: PIC16C62X FAMIL Y OF DEVICES PIC16C620 PIC16C620A PIC16CR620A PIC16C621 PIC16C621A PIC16C622 PIC16C622A Clock Maximum Frequency of Operation (MHz) 20 20 20 20 20 20 20 Memory EPROM Program Memory (x14 words) 512 512 512 1K 1K 2K 2K Data Memory (bytes)80 96 96 80 96 128 128 Peripherals Timer Module(s) TMR0 TMR0 TMRO TMR0 TMR0 TMR0 TMR0 Comparators(s) 2 2 2 2 2 2 2 Internal Reference Voltage Yes Yes Yes Yes Yes Yes Yes

Features

Interrupt Sources 4 4 4 4 4 4 4 I/O Pins 13 13 13 13 13 13 13 Brown-out Reset Yes Yes Yes Yes Yes Yes Yes Packages 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP All PICmicro™ Family devices have Pow er-on Reset, selectable W atchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 7 PIC16C62X

2.0 PIC16C62X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16C62X Product Identiﬁcation System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs . This v ersion can be er ased and reprogrammed to any of the oscillator modes. Microchip's PICST AR T Ò and PR O MA TE Ò programmers both suppor t programming of the PIC16C62X .

2.2 One-Time-Programmab le (OTP)

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates and small volume applications. In addition to the program memor y, the conﬁguration bits must also be programmed.

2.3 Quick-Turnaround-Production (QTP)

Microchip offers a QTP Prog ramming Ser vice for factory production orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed b y the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your Microchip Technology sales ofﬁce for more details.

2.4 Serialized

Quick-Turnaround-Production (SQTP SM ) Devices Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers ma y be r andom, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, passw ord or ID number.

Ó 1998 Microchip Technology Inc. NOTES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 9 PIC16C62X

3.0 AR C HITECTURAL OVER VIEW

The high performance of the PIC16C62X family can be attributed to a n umber of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C62X uses a Harvard architecture, in which, program and data are accessed from separate memor ies using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memor y. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memor y access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and e xecution of instructions. Consequently, all instructions (35) execute in a sin- gle-cycle (200 ns @ 20 MHz) except for program branches. The PIC16C620A and PIC16CR620A address 512 x 14 on-chip program memor y. The PIC16C621(A) addresses 1K x 14 prog ram memor y. The PIC16C622(A) addresses 2K x 14 program memor y. All program memor y is internal. The PIC16C62X can directly or indirectly address its register ﬁles or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16C62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C62X simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly. The PIC16C62X devices contain an 8-bit ALU and w orking register. The ALU is a gener al purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register ﬁle. The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the w orking register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and SUBWF instructions for examples. A simpliﬁed block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.

Ó 1998 Microchip Technology Inc. FIGURE 3-1: BLOC K DIAGRAM EPR OM Program Memor y

13 Data Bus 8

8 Level Stack

(13-bit) RAM File Registers Direct Addr 7 RAM Addr (1) 9 Addr MUX Indirect Addr FSR reg STATUS reg MUX ALU W reg Pow er-up Timer Oscillator Start-up Timer Pow er-on Reset W atchdog Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLK OUT MCLR VDD , VSS Voltage Brown-out Reset Note 1: Higher order bits are from the STATUS register. De vice Program Memor y Data Memor y (RAM) PIC16C620 PIC16C620A PIC16CR620A PIC16C621 PIC16C621A PIC16C622 PIC16C622A 512 x 14 512 x 14 512 x 14 1K x 14 1K x 14 2K x 14 2K x 14 80 x 8 96 x 8 96 x 8 80 x 8 96 x 8 128 x 8 128 x 8 TMR0 I/O Ports POR TB Compar ator RA3/AN3 RA2/AN2/VREF RA 1/AN1 RA0/AN0 Reference RA4/T0CKI

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 11 PIC16C62X TAB LE 3-1: PIC16C62X PINOUT DESCRIPTION Name DIP/ SOIC Pin # SSOP Pin # I/O/P Type Buffer Type

Description

OSC1/CLKIN 16 18 I ST/CMOS Oscillator crystal input/external clock source input. OSC2/CLK OUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLK OUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR /V PP 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. POR TA is a bi-directional I/O port. RA0/AN0 17 19 I/O ST Analog comparator input RA1/AN1 18 20 I/O ST Analog comparator input RA2/AN2/V REF 1 1 I/O ST Analog comparator input or V REF output RA3/AN3 2 2 I/O ST Analog comparator input /output RA4/T0CKI 3 3 I/O ST Can be selected to be the clock input to the Timer0 timer/counter or a comparator output. Output is open drain type. POR TB is a bi-directional I/O port. POR TB can be software programmed for internal weak pull-up on all inputs. RB0/INT 6 7 I/O TTL/ST (1) RB0/INT can also be selected as an external interrupt pin. RB1 7 8 I/O TTL RB2 8 9 I/O TTL RB3 9 10 I/O TTL RB4 10 11 I/O TTL Interrupt on change pin. RB5 11 12 I/O TTL Interrupt on change pin. RB6 12 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock. RB7 13 14 I/O TTL/ST (2) Interrupt on change pin. Serial programming data. V SS 5 5,6 P — Ground reference for logic and I/O pins. V DD 14 15,16 P — Positive supply for logic and I/O pins. Legend: O = output I/O = input/outputP = pow er — = Not used I = Input ST = Schmitt Trigger input TTL = TTL input Note 1:This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt. Note 2:This buffer is a Schmitt Trigger input when used in serial programming mode .

Ó 1998 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction Cycle

The clock input (O SC1 /CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memor y and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. How ever, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOC K /INSTRUCTION CYC LE EXAMPLE 3-1: INSTRUCTION PIPELINE FLO W Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PC OSC2/CLK OUT (RC mode) PC PC+1 PC+2 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) Internal phase clock All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed. 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 13 PIC16C62X

4.0 MEMOR Y OR GANIZATION

4.1 Program Memor y Organization

The PIC16C62X has a 13-bit program counter capable of addressing an 8K x 14 program memor y space. Only the ﬁrst 512 x 14 (0000h - 01FFh) f or the PIC16C620 (A) and PIC16CR620, 1K x 14 (0000h - 03FFh) for the PIC16C621(A) and 2K x 14 (0000h - 07FFh) for the PIC16C622(A) are physically imple- mented. Accessing a location above these boundaries will cause a wrap-around within the ﬁrst 512 x 14 space (PIC16C(R)620(A)) or 1K x 14 space (PIC16C621(A)) or 2K x 14 space (PIC16C622(A)). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3). FIGURE 4-1: PR OGRAM MEMOR Y MAP AND STAC K FOR THE PIC16C620/PIC16C620A/ PIC16CR620A PC<12:0> 000h 0004 0005 01FFh 0200h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memor y CALL, RETURN RETFIE, RETLW Stack Level 2 FIGURE 4-2: PR OGRAM MEMOR Y MAP AND STAC K FOR THE PIC16C621/PIC16C621A FIGURE 4-3: PR OGRAM MEMOR Y MAP AND STAC K FOR THE PIC16C622/PIC16C622A PC<12:0> 000h 0004 0005 03FFh 0400h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memor y CALL, RETURN RETFIE, RETLW Stack Level 2 PC<12:0> 000h 0004 0005 07FFh 0800h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memor y CALL, RETURN RETFIE, RETLW Stack Level 2

DS30235G -page 14 Preliminary Ó 1998 Microchip Technology Inc.

4.2 Data Memor y Organization

The data memory (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7) is partitioned into two Banks which contain the general purpose registers and the special function regis- ters. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATU S <5>) is set. The Special Function Registers are located in the ﬁrst 32 loca- tions of each Bank. Register locations 20-7Fh (Bank0) on the PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16C622 and PIC16C622A are general purpose registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. Addresses F0h-FFh of bank1 are implemented as common ram and mapped back to addresses 70h-7Fh in bank0 on the PIC16C620A/CR620A/621A/622A.

4.2.1 GENER AL PUR POSE REGISTER FILE

The register ﬁle is organized as 80 x 8 in the PIC16C620/621, 96 x 8 in the PIC16C620A/621A/CR620A and 128 x 8 in the PIC16C622 (A). Each is accessed either directly or indi- rectly through the File Select Re gister FSR (Section 4.4).

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 17 PIC16C62X

4.2.2 SPECIAL FUNCTION REGISTERS

The special function registers are registers used by the CPU and P eripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The special registers can be classiﬁed into two sets (core and peripheral). The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. TAB LE 4-1: SPECIAL REGISTER S FOR THE PIC16C62X Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module’s Register xxxx xxxxuuuu uuuu 02h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 00000000 0000 03h STATUS IRP(2) RP1 (2) RP0 TO PD Z DC C 0001 1xxx000q quuu 04h FSR Indirect data memory address pointer xxxx xxxxuuuu uuuu 05h POR TA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000---u 0000 06h POR TB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxxuuuu uuuu 07h Unimplemented — — 08h Unimplemented — — 09h Unimplemented — — 0Ah PCLA TH — — — Wr ite buffer for upper 5 bits of program counter ---0 0000---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x0000 000u 0Dh-1Eh Unimplemented — — 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 000000-- 0000 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 11111111 1111 82h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 00000000 0000 83h STATUS IRP(2) RP1 (2) RP0 TO PD Z DC C 0001 1xxx000q quuu 84h FSR Indirect data memory address pointer xxxx xxxxuuuu uuuu 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111---1 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 11111111 1111 87h Unimplemented — — 88h Unimplemented — — 89h Unimplemented — — 8Ah PCLA TH — — — Wr ite buffer for upper 5 bits of program counter ---0 0000---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x0000 000u 8Dh Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --0x---- --uq 8Fh-9Eh Unimplemented — — 9Fh VRCON VREN VR OE VRR — VR3 VR2 VR1 VR0 000- 0000000- 0000 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1:Other (non pow er-up) resets include MCLR reset, Brown-out Reset and W atchdog Timer Reset during normal operation. Note 2:IRP & RPI bits are reserved, always maintain these bits clear.

DS30235G -page 18 Preliminary Ó 1998 Microchip Technology Inc.

4.2.2.1 STATUS REGISTER

The STATUS register, shown in Figure 4-8, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the “Instruction Set Summary”. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C62X and should be programmed as ’0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. FIGURE 4-8: STATUS REGISTER (AD DRESS 03H OR 83H) Reserved Reserved R/W -0 R-1 R-1 R/W -x R/W -x R/W -x IRP RP1 RP0 TO PD Z DC C R = Readable bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset -x = Unknown at POR reset bit7 bit0 bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved on the PIC16C62X , always maintain this bit clear. bit 6-5: RP1:RP0 : Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X , alw ays maintain this bit clear. bit 4:T O : Time-out bit 1 = After pow er-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3:PD : Pow er-down bit 1 = After pow er-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2:Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1:DC : Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C : Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 19 PIC16C62X

4.2.2.2 OPTION REGISTER

The OPTION register is a readable and writable register which contains various control bits to conﬁgure the TMR0/WDT prescaler , the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB . Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). FIGURE 4-9: OPTION REGISTER (AD DRESS 81H) R/W -1 R/W -1 R/W -1 R/W -1 R/W -1 R/W -1 R/W -1 R/W -1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit W = Wr itable bit - n = Value at POR reset bit7 bit0 bit 7: RBPU : POR TB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG : Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS : TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE : TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA : Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0:PS2:PS0 : Prescaler Rate Select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 Bit Value TMR0 Rate WDT Rate

DS30235G -page 20 Preliminary Ó 1998 Microchip Technology Inc.

4.2.2.3 INTCON REGISTER

The INTCON register is a readable and writable register which contains the various enable and ﬂag bits for all interrupt sources except the comparator module. description of the comparator enable and ﬂag bits. Note: Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). FIGURE 4-10: INTCON REGISTER (AD DRESS 0BH OR 8BH) R/W -0 R/W -0 R/W -0 R/W -0 R/W -0 R/W -0 R/W -0 R/W -x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n= Value at POR reset -x = Unknown at POR reset bit7 bit0 bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Ov erﬂow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE : RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Ov erﬂow Interrupt Flag bit 1 = TMR0 register has overﬂow ed (must be cleared in software) 0 = TMR0 register did not overﬂow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 21 PIC16C62X

4.2.2.4 PIE1 REGISTER

This register contains the individual enable bit for the comparator interrupt. FIGURE 4-11: PIE1 REGISTER (AD DRESS 8CH)

4.2.2.5 PIR1 REGISTER

This register contains the individual ﬂag bit for the comparator interrupt. FIGURE 4-12: PIR1 REGISTER (AD DRESS 0CH) U-0 R/W -0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIE — — — — — — R = Readable bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n= Value at POR reset bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6: CMIE : Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt bit 5-0:Unimplemented : Read as '0' Note: Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt. U-0 R/W -0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIF — — — — — — R = Readable bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n= Value at POR reset bit7 bit0 bit 7: Unimplemented: Read as'0' bit 6: CMIF : Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed bit 5-0:Unimplemented : Read as '0'

DS30235G -page 22 Preliminary Ó 1998 Microchip Technology Inc.

4.2.2.6 PCON REGISTER

The PCON register contains ﬂag bits to differentiate between a Pow er-on Reset, an external MCLR reset, WDT reset or a Brown-out Reset. Note: BOR is unknown on P ow er-on Reset. It m ust then be set by the user and checked on subsequent resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BO R EN bit in the Conﬁguration word). FIGURE 4-13: PCON REGISTER (AD DRESS 8E h) U-0 U-0 U-0 U-0 U-0 U-0 R/W -0 R/W -0 — — — — — — POR BO R R = Readable bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n= Value at POR reset bit7 bit0 bit 7-2: Unimplemented: Re ad as '0' bit 1: POR : Pow er-on Reset Status bit 1 = No Pow er-on Reset occurred 0 = A Pow er-on Reset occurred (must be set in software after a Pow er-on Reset occurs) bit 0: BOR : Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 23 PIC16C62X

4.3 PCL and PCLA TH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLATH<4:0> ﬁ PCH). The lower example in the ﬁgure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> ﬁ PCH). FIGURE 4-14: LOADING OF PC IN DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GO TO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memor y boundary (each 256 byte block). Refer to the application note “Implementing a Table Read" (AN556). PC 12 8 7 0

5 PCLA TH<4:0>

GOTO, CALL Opcode <10:0> PC 12 11 10 0 11PCLA TH<4:3> PCH PCL 8 7 PCLA TH PCH PCL PCL as Destination

4.3.2 STAC K

The PIC16C62X fam ily has an 8 level deep x 13-bit wide hardware stack (Figure 4-2 and Figure 4-3). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLA TH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on). Note 1: There are no STATUS bits to indicate stack o verﬂow or stac k underﬂ ow conditions. Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.

DS30235G -page 24 Preliminary Ó 1998 Microchip Technology Inc.

4.4 Indirect Addressing, INDF and FSR

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF reg- ister. Any instruction using the INDF register actually accesses data pointed to by the ﬁle select register (FSR). Reading INDF itself indirectly will produce 00h. Wr iting to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-15. How ever, IRP is not used in the PIC16C62X . A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1. EXAMPLE 4-1: INDIRECT AD DRESSING movlw0x20;initialize pointer movwf FSR ;to RAM NEXT clrfINDF;clear INDF register incfFSR ;inc pointer btfssFSR,4;all done? gotoNEXT;no clear next ;yes continue CONTINUE: FIGURE 4-15: DIRECT/INDIRECT AD DRESSING PIC16C62X For memory map detail see (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7). Note 1:The RP1 and IRP bits are reserved, always maintain these bits clear. Data Memor y Indirect AddressingDirect Addressing bank select location select (1)RP1 RP0 6 0from opcode IRP(1) FSR register7 0 bank select location select 00 01 10 11 180h 1FFh 00h 7Fh Bank 0 Bank 1 Bank 2 Bank 3 not used

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 25 PIC16C62X

5.0 I/O POR TS

The PIC16C62X have two ports, PORTA and PORTB. Some p ins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1 POR TA and TRISA Registers

POR TA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can conﬁg- ure these pins as input or output. A '1' in the TRISA register puts the corresponding output driver in a hi- impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are ﬁrst read, then this value is modiﬁed and written to the port data latch. The POR TA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as '0's. FIGURE 5-1: BLOC K DIAGRAM OF RA1:RA0 PINS Note: I/O pins have protection diodes to VDD and VSS . Data bus QD QCK P N WR PortA WR TRISA Data Latch TRIS Latch RD TRISA RD POR TA Analog VSS VDD I/O Pin QD QCK Input Mode DQ EN To Comparator Schmitt Trigger Input Buffer TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user m ust make sure to keep the pins conﬁgured as inputs when using them as comparator inputs. The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high impedance output. The user must conﬁgure TRISA<2> bit as an input and use high impedance loads. In one of the comparator modes deﬁned by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function. EXAMPLE 5-1: INITIALIZING PORTA FIGURE 5-2: BLOC K DIAGRAM OF RA2 PIN Note: On reset, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption. CLRFPORTA ;Initialize PORTA by setting ;output data latches MOVLW0X07 ;Turn comparators off and MOVWFCMCON ;enable pins for I/O ;functions BSFSTATUS, RP0;Select Bank1 MOVLW0x1F ;Value used to initialize ;data direction MOVWFTRISA ;Set RA<4:0> as inputs ;TRISA<7:5> are always ;read as '0'. Note: I/O pins have protection diodes to VDD and VSS . Data bus QD QCK P N WR PortA WR TRISA Data Latch TRIS Latch RD TRISA RD POR TA Analog VSS VDD RA2 Pin QD QCK Input Mode DQ EN To Comparator Schmitt Trigger Input Buffer VROE VREF

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 27 PIC16C62X TAB LE 5-1: POR TA FUNCTIONS TAB LE 5-2: SUMMAR Y OF REGISTER S ASSOCIATED WITH POR TA Name Bit # Buffer Type Function RA0/AN0 bit0 ST Input/output or comparator input RA1/AN1 bit1 ST Input/output or comparator input RA2/AN2/VREF bit2 ST Input/output or comparator input or VREF output RA3/AN3 bit3 ST Input/output or comparator input/output RA4/T0CKI bit4 ST Input/output or external clock input for TMR0 or comparator output. Output is open drain type. Legend:ST = Schmitt Trigger input Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets 05h POR TA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000---u 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111---1 1111 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 000000-- 0000 9Fh VRCON VREN VR OE VRR — VR3 VR2 VR1 VR0 000- 0000000- 0000 Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown Note: Note: Shaded bits are not used by PORTA.

DS30235G -page 28 Preliminary Ó 1998 Microchip Technology Inc.

5.2 POR TB and TRISB Registers

POR TB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB . A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). R eading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are ﬁrst read, then this value is modiﬁed and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (»200 mA typical). A single control bit can turn on all the pull-ups. This is done b y clearing the RBPU (OPTION<7>) bit. The w eak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on Pow er-on Reset. Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB . The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RBIF interrupt (ﬂag latched in INTCON<0>). FIGURE 5-5: BLOC K DIAGRAM OF R B 7:RB4 PINS Data Latch From other RBPU (2) P VDD I/O QD CK QD CK Q D EN Q D EN Data bus WR P ortB WR TRISB Set RBIF TRIS Latch RD TRISB RD PortB RB 7:RB 4 pins w eak pull-up RD Port Latch TTL Input Buffer pin(1) Note 1: I/O pins have diode protection to VDD and VSS . Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>). ST Buffer RB7:RB6 in serial programming mode Q Q This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) Any read or write of POR TB . This will end the mismatch condition. b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF. Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared. This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four pins allow easy interface to a key pad and make it possible for w ake-up on k ey-depression. (See AN552 in the Microchip Embedded Control Handbook.) The interrupt on change feature is recommended for w ake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. FIGURE 5-6: BLO C K DIAGRAM OF RB3:RB0 PIN S Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF inter- rupt ﬂag may not get set. Data Latch RBPU (2) P VDD QD CK D CK Q D EN Data bus WR P ortB WR TRISB RD TRISB RD PortB w eak pull-up RD Port RB0/INT I/O pin(1) TTL Input Buffer Note 1: I/O pins have diode protection to V DD and VSS . Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>). ST Buffer Q Q Q

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 29 PIC16C62X TAB LE 5-3: POR TB FUNCTIONS TAB LE 5-4: SUMMAR Y OF REGISTER S ASSOCIATED WITH POR TB Name Bit # Buffer Type Function RB0/INT bit0 TTL/ST(1) Input/output or external interrupt input. Internal software programmab le w eak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmab le weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmab le weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmab le weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmab le weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmab le weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmab le weak pull-up. Serial programming clock pin. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmab le weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1:This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt. Note 2:This buffer is a Schmitt Trigger input when used in serial programming mode . Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets 06h POR TB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxxuuuu uuuu 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 11111111 1111 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 11111111 1111 Note: Shaded bits are not used by PORTB . u = unchanged x = unknown

DS30235G -page 30 Preliminary Ó 1998 Microchip Technology Inc.

5.3 I/O Programming Considerations

5.3.1 BI-DIRECTIONAL I/O POR TS

Any instruction which writes, operates internally as a read follow ed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU , execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. Ho w ever, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Wr iting to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-2 sho ws the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip. EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O POR T

5.3.2 SUCCESSIV E OPER ATIONS ON I/O POR TS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-7). Therefore, care must be exercised if a write follow ed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ﬁle to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. Initial PORT settings:PORTB<7:4> Inputs ; PORTB<3:0> Outputs PORTB<7:6> have external pull-up and are not connected to other circuitry ; PORTlatchPORTpins BCFPORTB, 7;01pppppp11pppppp BCFPORTB, 6;10pppppp11pppppp BSFSTATUS,RP0 ; BCFTRISB, 7;10pppppp11pppppp BCFTRISB, 6;10pppppp10pppppp ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High). FIGURE 5-7: SUCCESSIVE I/O OPERATION Note: This example shows write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD ) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RB <7:0> Port pin sampled here PC PC + 1 PC + 2 PC + 3 NOPNOPMOVF PORTB, W Read PORTB MOVWF PORTB Write to PORTB PC Instruction fetched TPD Execute MOVWF PORTB Execute MOVF PORTB, W Execute NOP RB7:RB0

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 31 PIC16C62X

6.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

8-bit timer/counter
Readab le and writable
8-bit software programmab le prescaler
Internal or external clock select
Interrupt on overﬂow from FFh to 00h
Edge select for external clock Figure 6-1 is a simpliﬁed block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to TMR0 . Counter mode is selected by setting the T0CS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 module and the W atchdog Timer. The prescaler assignment is controlled in software b y the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.

6.1 TIMER0 Interrupt

Timer0 interrupt is generated when the TMR0 register timer/counter overﬂows from FFh to 00h. This overﬂow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) m ust be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The Timer0 interrupt cannot w ake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 6-4 for Timer0 interrupt timing. FIGURE 6-1: TIMER0 BL O C K DIAGRAM FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOC K/NO PRESCALER Note 1: Bits T0SE, T0CS , PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with W atchdog Timer (Figure 6-6) RA 4/T0CKI T0SE pin T0CS FOSC /4 Programmab le Prescaler Sync with Internal clocks TMR0 PSout (2 TCY delay) PSout Data bus Set Flag bit T0IF on OverﬂowPSAPS2:PS0 PC-1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4PC (Program Counter) Instruction Fetch TMR0 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 T0 T0+1 T0+2 NT0 NT0+1 NT0+2 T0 MO VWF TMR0 MO VF TMR0,W MO VF TMR0,W MO VF TMR0,W MO VF TMR0,W MO VF TMR0,W Wr ite TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 Read TMR0 reads NT0 + 2 Instruction Executed

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 33 PIC16C62X

6.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it must meet cer tain requirements. The e xternal clock requirement is due to internal phase clock (TOSC ) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.2.1 EXTER NAL CLOC K SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the inter nal phase cloc ks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical speciﬁcation of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the e xternal clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

6.2.2 TIMER0 INCREMENT DELA Y

Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMR0 is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOC K Q 1 Q 2 Q 3 Q4 Q 1 Q 2 Q 3 Q4 Q 1 Q 2 Q 3 Q4 Q 1 Q 2 Q 3 Q4 External Clock Input or Prescaler output (2) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Small pulse misses sampling Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between tw o edges on Timer0 input = –4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. (3) (1)

DS30235G -page 34 Preliminary Ó 1998 Microchip Technology Inc.

6.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the W atchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 module and the W atchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the W atchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, assigned to WDT , a CLRWDT instruction will clear the prescaler along with the W atchdog Timer. The prescaler is not readable or writable. FIGURE 6-6: BLOC K DIAGRAM OF THE TIMER0 /WDT PRESCALER T0CKI T0SE pin M U X CLK OUT (=Fosc/4) SYNC Cycles TMR0 reg 8-bit Prescaler 8-to-1MUX M U X M U X W atchdog Timer PSA 0 1 WDT Time-out PS0 - PS2 Note: T0SE, T0CS , PSA, PS0-PS2 are bits in the OPTION register. PSA WDT Enab le bit M U X 1 0 Data Bus Set ﬂag bit T0IF on Overﬂow PSA T0CS

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 35 PIC16C62X

6.3.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control (i.e., it can be changed “on the ﬂy” during program e xecution). To avoid an unintended device RESET , the f ollowing instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to WDT . EXAMPLE 6-1: C HANGING PRESCALER (TIMER0 ﬁ WDT) 1.BCF STATUS, RP0;Skip if already in ; Bank 0 2.CLRWDT ;Clear WDT 3.CLRF TMR0 ;Clear TMR0 & Prescaler 4.BSF STATUS, RP0;Bank 1 5.MOVLW'00101111’b;;These 3 lines (5, 6, 7) 6.MOVWFOPTION ; are required only if ; desired PS<2:0> are 7.CLRWDT ; 000 or 001 8.MOVLW'00101xxx’b;Set Postscaler to 9.MOVWFOPTION ; desired WDT rate 10.BCF STATUS, RP0 ;Return to Bank 0 To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. EXAMPLE 6-2: CHANGING PRESCALER (WDT ﬁ TIMER0) CLRWDT ;Clear WDT and ;prescaler BSF STATUS, RP0 MOVLW b'xxxx0xxx';Select TMR0, new ;prescale value and ;clock source MOVWF OPTION_REG BCF STATUS, RP0 TABLE 6-1: REGISTER S ASSOCIATED WITH TIMER0 Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets 01h TMR0 Timer0 module register xxxx xxxxuuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x0000 000u 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 11111111 1111 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111---1 1111 Legend: — = Unimplemented locations, read as ‘0’. Note: Shaded bits are not used by TMR0 module . u = unchanged x = unknown

DS30235G -page 36 Preliminary Ó 1998 Microchip Technology Inc. NOTES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 37 PIC16C62X

7.0 COMPARATOR MODULE

The compar ator module contains tw o analog comparators. The inputs to the comparators are m ultiplexed with the RA0 through RA3 pins. The on-chip Voltage Reference (Section 8.0) can also be an input to the comparators. The CMCON register, shown in Figure 7-1, controls the comparator input and output multiplexers. A b lock diagram of the comparator is shown in Figure 7-2. FIGURE 7-1: CMCON REGISTER (ADDRESS 1F h) R-0 R-0 U-0 U-0 R/W -0 R/W -0 R/W -0 R/W -0 C2OUT C1OUT CIS CM2 CM1 CM0 R = Readab le bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit7 bit0 bit 7:C2OUT : Comparator 2 output 1 = C2 VIN+ > C2 VIN– 0 = C2 VIN+ < C2 VIN– bit 6:C1OUT : Comparator 1 output 1 = C1 VIN+ > C1 VIN– 0 = C1 VIN+ < C1 VIN– bit 5-4:Unimplemented : Read as '0' bit 3:CIS: Comparator Input Switch When C M <2:0>: = 001: 1 = C1 VIN– connects to RA3 0 = C1 VIN– connects to RA0 When CM <2:0> = 010: 1 = C1 VIN– connects to RA3 C2 VIN– connects to RA2 0 = C1 VIN– connects to RA0 C2 VIN– connects to RA1 bit 2-0:CM <2:0>: Comparator mode Figure 7-2.

DS30235G -page 38 Preliminary Ó 1998 Microchip Technology Inc.

7.1 Comparator Conﬁ guration

There are eight modes of oper ation for the comparators. The CMCON register is used to select the mode . Figure 7-2 shows the eight possible modes. The TRISA register controls the data direction of the com- parator pins for each mode. If the comparator mode is changed, the comparator output level may not be valid for the speciﬁed mode change dela y shown in Table 12-2. Note: Compar ator interrupts should be disabled during a comparator mode change other- wise a false interrupt may occur. FIGURE 7-2: COMPARATOR I/O OPERATING MODES VIN- VIN+ Off (Read as '0') RA0/AN0 RA3/AN3 A A CM <2:0> = 000 VIN- VIN+ Off (Read as '0') RA1/AN1 RA2/AN2 A A VIN- VIN+ Off (Read as '0') RA0/AN0 RA3/AN3 D D CM<2:0 > = 111 VIN- VIN+ Off (Read as '0') RA1/AN1 RA2/AN2 D D VIN- VIN+ C1OUTRA0/AN0 RA3/AN3 A A VIN- VIN+ C2OUTRA1/AN1 RA2/AN2 A A CM< 2:0> = 100 VIN- VIN+ C1OUT RA0/AN0 RA3/AN3 A A VIN- VIN+ C2OUT RA1/AN1 RA2/AN2 A A From VREF Module VIN- VIN+ C1OUTRA0/AN0 RA3/AN3 A D VIN- VIN+ C2OUTRA1/AN1 RA2/AN2 A A CM <2:0> = 011 RA4 Open Drain VIN- VIN+ C1OUTRA0/AN0 RA3/AN3 A D VIN- VIN+ C2OUTRA1/AN1 RA2/AN2 A A CM<2:0> = 110 VIN- VIN+ Off (Read as '0') RA0/AN0 RA3/AN3 D D CM<2 :0> = 101 VIN- VIN+ C2OUTRA1/AN1 RA2/AN2 A A VIN- VIN+ C1OUT RA0/AN0 RA3/AN3 A A VIN- VIN+ C2OUTRA1/AN1 RA2/AN2 A A CM<2:0> = 001 CIS=0 CIS=1 Compar ators Reset Tw o Independent Comparators Tw o Common Reference Comparators One Independent Comparator Three Inputs Multiplexed to Tw o Common Reference Comparators with Outputs Four Inputs Multiplexed to Compar ators Off Tw o Comparators Tw o Comparators CM<2: 0> = 010 CIS=0 CIS=1 CIS=0 CIS=1 A = Analog Input, Port Reads Zeros Always D = Digital Input CIS = CMC ON<3>, Comparator Input Switch

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 39 PIC16C62X The code example in Example 7-1 depicts the steps required to conﬁgure the comparator module. RA3 and RA4 are conﬁgured as digital output. RA0 and RA1 are conﬁgured as the V- inputs and RA2 as the V+ input to both comparators. EXAMPLE 7-1: INITIALIZING COMPARATOR MODULE

7.2 Comparator Operation

A single comparator is shown in Figure 7-3 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN–, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN–, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 7-3 represent the uncertainty due to input offsets and response time. FLAG_REGEQU 0X20 CLRF FLAG_REG;Init flag register CLRF PORTA ;Init PORTA MOVF CMCON, W;Load comparator bits ANDLW0xC0 ;Mask comparator bits IORWFFLAG_REG,F;Store bits in flag register MOVLW0x03 ;Init comparator mode MOVWFCMCON ;CM<2:0> = 011 BSF STATUS,RP0;Select Bank1 MOVLW0x07 ;Initialize data direction MOVWFTRISA ;Set RA<2:0> as inputs ;RA<4:3> as outputs ;TRISA<7:5> always read ‘0’ BCF STATUS,RP0;Select Bank 0 CALL DELAY 10;10ms delay MOVF CMCON,F;Read CMCON to end change condition BCF PIR1,CMIF;Clear pending interrupts BSF STATUS,RP0;Select Bank 1 BSF PIE1,CMIE;Enable comparator interrupts BCF STATUS,RP0;Select Bank 0 BSF INTCON,PEIE;Enable peripheral interrupts BSF INTCON,GIE;Global interrupt enable

7.3 Comparator Reference

An external or internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at VIN– is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 7-3). FIGURE 7-3: SINGLE CO MPARATOR

7.3.1 EXTERNAL REFERENCE SIGNAL

When e xternal voltage references are used, the comparator module can be conﬁgured to have the com- parators operate from the same or different reference sources. Ho w ever, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD , and can be applied to either pin of the comparator(s).

7.3.2 INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an internally generated v oltage reference for the comparators. Section 13, Instruction Sets, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the compar ators are in mode CM<2: 0>=010 (Figure 7-2). In this mode, the internal voltage reference is applied to the VIN+ pin of both com- parators. +VIN+ VIN– Output VIN– VIN+ Output

DS30235G -page 40 Preliminary Ó 1998 Microchip Technology Inc.

7.4 Comparator Response Time

Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference m ust be considered when using the comparator outputs. Otherwise the maximum delay of the comparators should be used (Table 12-2 ).

7.5 Comparator Outputs

The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the speciﬁcations. Figure 7-4 sho ws the compar ator output block diagram. The TRISA bits will still function as an output enable/disable for the RA3 and RA4 pins while in this mode . Note 1: When reading the PORT register, all pins conﬁgured as analog inputs will read as a ‘0’. Pins conﬁgured as digital inputs will convert an analog input according to the Schmitt Trigger input speciﬁcation. 2: Analog levels on any pin that is deﬁned as a digital input may cause the input buffer to consume more current than is speciﬁed. FIGURE 7-4: CO MPARATOR O U TPUT BLOC K DIAGRAM DQ EN To RA3 or RA4 Pin Bus Data RD CMCON Set MUL TIPLEX CMIF Bit DQ EN CL Port Pins RD CMCON NRESET From Other Compar ator

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 41 PIC16C62X

7.6 Comparator Interrupts

The comparator interrupt ﬂag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the comparator interrupt ﬂag. The CMIF bit must be reset by clearing ‘0’. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) m ust be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) Any read or write of CMCON. This will end the mismatch condition. b) Clear ﬂag bit CMIF. A mismatch condition will continue to set ﬂag bit CMIF. Reading CMCON will end the mismatch condition, and allow ﬂag bit CMIF to be cleared.

7.7 C omparator Operation During SLEEP

When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<6>) interrupt ﬂag may not get set. w ake up the device from SLEEP mode when enabled. While the comparator is pow ered-up, higher sleep currents than shown in the pow er down current speciﬁcation will occur. Each compar ator that is operational will consume additional current as shown in the comparator speciﬁcations. To minimize po w er consumption while in SLEEP mode , turn off the comparators, CM<2:0> = 111, before entering sleep. If the device wakes-up from sleep, the contents of the CMCON register are not affected.

7.8 Effects of a RESET

A device reset forces the CMCON register to its reset state. This forces the comparator module to be in the comparator reset mode , CM2: CM 0 = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at reset time. The compar ators will be pow ered-down during the reset interval.

7.9 Analog Input Connection

A simpliﬁed circuit for an analog input is shown in Figure 7-5. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS . The analog input therefore, must be between VSS and VDD . If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maxim um source impedance of 10 kW is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 7-5: ANA LOG INPUT MODEL VA R S < 10K AIN C PIN 5 pF VDD VT = 0.6V VT = 0.6V R IC ILEAKAGE –500 nA VSS Legend C PIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current At The Pin Due To Various Junctions R IC = Interconnect Resistance R S = Source Impedance VA = Analog Voltage

DS30235G -page 42 Preliminary Ó 1998 Microchip Technology Inc. TABLE 7-1: REGISTER S ASSOCIATED WITH COMPARATOR MODULE Legend:x = unknown u = unchanged - = unimplemented, read as "0" Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 000000-- 0000 9Fh VRCON VREN VR OE VRR — VR3 VR2 VR1 VR0 000- 0000000- 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x0000 000u 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111---1 1111

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 43 PIC16C62X

8.0 VOLTA G E REF ERENCE

The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a pow er-down function to conserve pow er when the reference is not being used. The VRCON register controls the operation of the reference as shown in Figure 8-1. The block diagram is given in Figure 8-2.

8.1 Conﬁ guring the Voltage Reference

The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows: if VRR = 1: VREF = (VR <3:0>/24) x VDD if VRR = 0: VREF = (VDD x 1/4) + (VR <3:0>/32) x VDD The setting time of the Voltage Reference must be considered when changing the VREF output (Table 12-2). Example 8-1 shows an example of how to conﬁgure the Voltage Reference for an output voltage of 1.25V with VDD = 5.0V. FIGURE 8-1: VRCON REGISTER(AD DRESS 9F h) FIGURE 8-2: VOLTA G E REF ERENCE BLOC K DIAGRAM R/W -0 R/W -0 R/W -0 U-0 R/W -0 R/W -0 R/W -0 R/W -0 VREN VR OE VRR — VR3 VR2 VR1 VR0 R = Readab le bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit7 bit0 bit 7:VREN : VREF Enable 1 = VREF circuit pow ered on 0 = VREF circuit pow ered down, no IDD drain bit 6:VR OE : VREF Output Enable 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin bit 5: VRR : VREF Range selection 1 = Low Range 0 = High Range bit 4: Unimplemented : Read as '0' bit 3-0:VR <3:0>: VREF value selection 0 £ VR [3:0] £ 15 when VRR = 1: VREF = (VR <3:0>/ 24) * VDD when VRR = 0: VREF = 1/4 * VDD + (VR <3:0>/ 32) * VDD Note: R is deﬁned in Table 12-3. VRR8R VR 3 VR 0 (From VRCON<3:0>)16-1 Analog Mux 8R R R R RVREN VREF

16 Stages

DS30235G -page 44 Preliminary Ó 1998 Microchip Technology Inc. EXAMPLE 8-1: VOLTA G E REF ERENCE CONFIGURATION

8.2 Voltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-2) keep VREF from approaching VSS or VDD . The Voltage Reference is VDD derived and therefore, the VREF output changes with ﬂuctuations in VDD . The tested absolute accuracy of the Voltage Reference can be found in Table 12-3.

8.3 Operation During Sleep

When the device wakes up from sleep through an interrupt or a W atchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode , the Voltage Reference should be disabled. MOVLW0x02 ; 4 Inputs Muxed MOVWFCMCON ; to 2 comps. BSF STATUS,RP0; go to Bank 1 MOVLW0x07 ; RA3-RA0 are MOVWFTRISA ; outputs MOVLW0xA6 ; enable VREF MOVWFVRCON ; low range ; set VR<3:0>=6 BCF STATUS,RP0; go to Bank 0 CALL DELAY10; 10ms delay

8.4 Effects of a Reset

A device reset disables the Voltage Reference by clear- ing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared.

8.5 Connection Considerations

The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the VROE bit, VRCON<6>, is set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase cur- rent consumption. Connecting RA2 as a digital output with V REF enabled will also increase current consump- tion. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference output for external connections to VREF . Figure 8-3 sho ws an e xample b uffering technique. FIGURE 8-3: VOLTA G E REF ERENCE OUTPUT BUFF ER EXAMPLE TABLE 8-1: REGISTER S ASSOCIATED WITH VOLTA G E REF ERENCE Note: - = Unimplemented, read as "0" Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On POR Value On All Other Resets 9Fh VRCON VREN VR OE VRR — VR3 VR2 VR1 VR0 000- 0000000- 0000 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 000000-- 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111---1 1111 VREF Output+ – •• VREF Module Voltage Reference Output Impedance R (1) RA2 Note 1:R is dependent upon the Voltage Reference Conﬁguration VRCON<3:0> and VRCON<5>.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 45 PIC16C62X

9.0 SPECIAL FEATURES OF THE

Special circuits to deal with the needs of real time appli- cations are what sets a microcontroller apart from other processors. The PIC16C62X family has a host of such features intended to maximize system reliability, mini- mize cost through elimination of external components, provide pow er saving operating modes and offer code protection. These are: 1. OSC selection 2. Reset Pow er-on Reset (POR) Pow er-up Timer (PWRT) Oscillator Start-Up Timer (OST) Brown-out Reset (BOR) 3. Interrupts 4. W atchdog Timer (WDT) 5. SLEEP 6. Code protection 7. ID Locations 8. In-circuit serial programming The PIC16C62X has a W atchdog Timer which is controlled by conﬁguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on po w er-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Pow er-up Timer (PWRT), which provides a ﬁxed delay of 72 ms (nominal) on pow er-up only, designed to keep the part in reset while the pow er supply stabilizes. There is also circuitry to reset the device if a brown-out occurs which provides at least a 72 ms reset. With these three functions on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current pow er-down mode. The user can wake-up from SLEEP through e xternal reset, W atchdog Timer w ake-up or through an interrupt. Several oscillator options are also made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves pow er. A set of conﬁguration bits are used to select various options.

DS30235G -page 46 Preliminary Ó 1998 Microchip Technology Inc.

9.1 Conﬁ guration Bits

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in program memor y location 2007h. The user will note that address 2007h is beyond the user program memor y space. In fact, it belongs to the special test/conﬁguration memor y space (2000h – 3FFFh), which can be accessed only during programming. FIGURE 9-1: CONFIGURATION W OR D CP1 CP0 (2) CP1 CP0 (2) CP1 CP0 (2) — BOREN (1) CP1 CP0 (2) PWR TE (1)WDTE F0SC1 F0SC0 CONFIG Address REGISTER: 2007hbit13 bit0 bit 13-8,CP<1:0>: Code protection bit pairs(2) 5-4:Code protection for 2K program memor y 11 = Program memor y code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected Code protection for 1K program memor y 11 = Program memor y code protection off 10 =Program memor y code protection on 01 = 0200h-03FFh code protected 00 = 0000h-03FFh code protected Code protection for 0.5K program memor y 11 = Program memor y code protection off 10 = Program memor y code protection off 01 = Program memor y code protection off 00 = 0000h-01FFh code protected bit 7: Unimplemented : Read as '1' bit 6: BOREN : Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWR TE : Pow er-up Timer Enable bit (1, 3) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE : W atchdog Timer Enable bit 1 = WDT enab led 0 = WDT disabled bit 1-0:FOSC1:FOSC0 : Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Pow er-up Timer (PWRT) regardless of the value of bit PWR TE . W e recommend that whenever Brown-out Reset is enabled, the Pow er-up Timer is also enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: Unprogrammed parts default the Pow er-up Timer disabled.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 47 PIC16C62X

9.2 Oscillator Conﬁgurations

9.2.1 OSCILLATOR TYPES

The PIC16C62X can be operated in four different oscillator options. The user can prog ram tw o conﬁguration bits (FOSC1 and FOSC0) to select one of these four modes:

LP Low Pow er Crystal
XT Crystal/Resonator
HS High Speed Crystal/Resonator
RC Resistor/Capacitor

9.2.2 CR YSTAL OSCILLATOR / CERAMIC

In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 9-2). The PIC16C62X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, LP or HS modes , the device can have an external clock source to drive the OSC1 pin (Figure 9-3). FIGURE 9-2: CR YS TAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) FIGURE 9-3: EXTE RNAL CLOC K INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) See Table 9-1 and Table 9-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals. XTAL OSC2 RS OSC1 RF SLEEP To internal logic PIC16C62Xsee Note C lock from ext. system PIC16C62X OSC1 OSC2O pen TABLE 9-1: CAPACITOR SELECTION FOR CERAMIC RESONATOR S TABLE 9-2: CAPACITOR SELECTION FOR CR YSTAL OSCILLATOR Rang es Characterized: Mode Freq OSC1 (C1) OSC 2(C2) XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

H igher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator man- ufacturer for appropriate values of external components. Mode Freq OSC1 (C1) OSC2 (C2) LP 32 kHz 200 kHz 68 - 100 pF 15 - 30 pF 68 - 100 pF 15 - 30 pF XT 100 kHz

2 MHz

4 MHz

8 MHz

10 MHz

20 MHz

Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as w ell as XT mode to avoid overdriving crystals with low drive level speciﬁcation. Since each cr ystal has its own characteristics, the user should consult the crystal manu- facturer for appropriate values of external components.

DS30235G -page 48 Preliminary Ó 1998 Microchip Technology Inc.

9.2.3 EXTERNAL CR YSTAL OSCILLATOR

Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be b uilt. Prepackaged oscillators provide a wide operating range and better stability. A w ell-designed crystal oscillator will provide good performance with TTL gates. Tw o types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 9-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180° phase shift that a parallel oscillator requires. The 4.7 kW resistor provides the negative f eedback f or stability. The 10 kW potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs. FIGURE 9-4: EXTERNAL P ARALLEL RESONANT CR YSTAL OSCILLATOR CIR CUIT Figure 9-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180° phase shift in a series resonant oscillator circuit. The 330 kW resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 9-5: EXTERNAL SERIES RESONANT CR YSTAL OSCI LLATOR CIR CUIT 20 pF +5V 20 pF 10k 4.7k 10k 74AS04 XTAL 10k 74AS04 PIC16C 62X CLK IN To other Devices 330 kW 74AS04 74AS04 PIC16C 62X CLK IN To other Devices XTAL 330 kW 74AS04 0.1 mF

9.2.4 RC OSCILLATOR

For timing insensitive applications the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter v ariation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-6 shows how the R/C combination is connected to the PIC16C62X. For Rext values below 2.2 kW , the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M W ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 kW and 100 kW . Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See Section 13.0 for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC fre- quency more). See Section 13.0 for variation of oscillator frequency due to VDD for given Re xt/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLK OUT pin, and can be used for test purposes or to synchronize other logic (Figure 3-2 for w aveform). FIGURE 9-6: RC OSCILLATOR MODE OSC2/CLKOUT Cext Rext VDD PIC16C 62X OSC1 Fosc/4 Internal Clock VDD

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 49 PIC16C62X

9.3 Reset

The PIC16C62X differentiates between various kinds of reset: a) Pow er-on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT reset (normal operation) e) WDT w ake-up (SLEEP ) f) Brown-out Reset (BOR) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Pow er-on reset, MCLR reset, WDT reset and MCLR reset during SLEEP. They are not affected by a WDT w ake-up, since this is view ed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in Table 9-4. These bits are used in software to determine the nature of the reset. See Table 9-7 for a full descrip- tion of reset states of all registers. A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 9-7. The MCLR reset path has a noise ﬁlter to detect and ignore small pulses. See Table 12-6 for pulse width speciﬁcation. FIGURE 9-7: SIMPLIFIED BLO C K DIAGR A M OF ON-C HIP RESET CIRCUIT S R Q External Reset MCLR / VDD OSC1/ WDT Module VDD rise detect OST/PWR T On-chip(1) RC OSC WDT Time-out Pow er-on Reset OST PWR T Chip_Reset 10-bit Ripple-counter R eset Enable OST Enable PWRT SLEEP See Table 9-3 for time-out situations. Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. Brown-out Reset BOREN CLKIN Pin VPP Pin 10-bit Ripple-counter Q

DS30235G -page 50 Preliminary Ó 1998 Microchip Technology Inc.

9.4 Power-on Reset (POR), Power-up

Timer (PWR T), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR)

9.4.1 PO W ER-ON RESET (POR)

The on-chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper opera- tion. To take advantage of the POR, just tie the MCLR pin through a resistor to VDD . This will eliminate exter- nal RC components usually needed to create Pow er-on Reset. A maximum rise time for VDD is required. See Electrical Speciﬁcations for details. The POR circuit does not produce an internal reset when VDD declines. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device m ust be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607 “Pow er-up Trouble Shooting”.

9.4.2 PO W ER-UP TIMER (PWR T)

The Pow er-up Timer provides a ﬁxed 72 ms (nominal) time-out on pow er-up only, from POR or Brown-out Reset. The Pow er-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWR T delay allows the VDD to rise to an acceptable level. A conﬁguration bit, PW RTE can disable (if set) or enable (if cleared or programmed) the Pow er-up Timer. The Pow er-up Timer should always be enabled when Brown-out Reset is enabled. The Pow er-Up Time delay will vary from chip to chip and due to VDD , temperature and process variation. See DC parameters for details.

9.4.3 OSCILLATOR STAR T-UP TIMER (OST)

The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWR T delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on pow er-on reset or wake-up from SLEEP .

9.4.4 BRO WN-OUT RESET (BOR)

The PIC16C62X members ha ve on-chip Brown-out Reset circuitry. A conﬁguration bit, BOR EN, can dis- able (if clear/programmed) or enab le (if set) the Brown-out R eset circuitry. If VDD falls below 4.0V refer to VBOR parameter D 005(VBOR ) for greater than parameter (TBOR) in Table 12-6, the brown-out situa- tion will reset the chip. A reset is not guaranteed to occur if VDD falls below 4.0V for less than parameter (TBOR ). On any reset (Pow er-on, Brown-out, W atchdog, etc.) the chip will remain in Reset until VDD rises above BV DD . The Pow er-up Timer will now be invoked and will keep the chip in reset an additional 72 ms . If VDD drops below BV DD while the Pow er-up Timer is running, the chip will go back into a Brown-out R eset and the Pow er-up Timer will be re-initialized. Once VDD rises above BVDD , the Pow er-Up Timer will execute a 72 ms reset. The Pow er-up Timer should always be enabled when Brown-out Reset is enabled. Figure 9-8 shows typical Brown-out situations. FIGURE 9-8: BR O WN-OUT SITUATIONS 72 ms BV DD Max. BV DD Min. VDD Internal Reset BV DD Max. BV DD Min. VDD Internal Reset 72 ms<72 ms 72 ms BV DD Max. BV DD Min. VDD Internal Reset

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 51 PIC16C62X

9.4.5 TIME-OUT SEQUENCE

On pow er-up the time-out sequence is as follows: First PWR T time-out is invoked after POR has expired. Then OST is activated. The total time-out will vary based on oscillator conﬁguration and PW RTE bit status. For example, in RC mode with PW RTE bit erased (PWRT disabled), there will be no time-out at all. Figure 9-9, Figure 9-10 and Figure 9-11 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 9-10). This is useful for testing purposes or to synchronize more than one PIC16C62X device oper- ating in parallel. Table 9-6 shows the reset conditions for some special registers, while Table 9-7 shows the reset conditions for all the registers.

9.4.6 PO W ER CONTROL (PCON)/

The po w er control/status register, PCON (address 8Eh) has two bits. Bit0 is BOR (Brown-out). BOR is unknown on pow er-on-reset. It must then be set by the user and checked on subsequent resets to see if BOR = 0 indicating that a brown-out has occurred. The BOR status bit is a don’t care and is not necessarily predictable if the brown-out circuit is disabled (by setting BOR EN bit = 0 in the Conﬁguration word). Bit1 is POR (P ow er-on-reset). It is a ‘0’ on pow er-on-reset and unaffected otherwise. The user m ust write a ‘1’ to this bit following a pow er-on-reset. On a subsequent reset if POR is ‘0’, it will indicate that a pow er-on-reset must have occurred (VDD may have gone too low). TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS TABLE 9-4: STATUS /PCON BITS AND THEIR SIGNIFICANCE Legend:u = unchanged, x = unknown Oscillator Conﬁguration Power-up Brown-out Reset W ake-up from SLEEPPWR TE = 0 PWR TE = 1 XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC RC 72 ms — 72 ms — POR BOR TO PD

0 X 1 1 Pow er-on-reset

0 X 0 X Illegal, TO is set on POR

0 X X 0 Illegal, PD is set on POR

1 1 u u MCLR reset during normal operation 1 1 1 0 MCLR reset during SLEEP TABLE 9-5: SUMMAR Y OF REGISTER S ASSOCIATED WITH BR O WN-OUT Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1) 83h STATUS TO PD 0001 1xxx000q quuu 8Eh PCON — — — — — — POR BOR ---- --0x---- --uq Note1: Other (non pow er-up) resets include MCLR reset, Brown-out Reset and W atchdog Timer Reset during normal operation.

DS30235G -page 52 Preliminary Ó 1998 Microchip Technology Inc. TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTER S TABLE 9-7: INITIALIZATION CONDITION FOR REGISTER S Condition Program Counter STATUS Register PCON Register Pow er-on R eset 000h 0001 1xxx---- --0x MCLR reset during normal operation 000h 000u uuuu---- --uu MCLR reset during SLEEP 000h 0001 0uuu---- --uu WDT reset 000h 0000 uuuu---- --uu WDT W ake-up PC + 1 uuu0 0uuu---- --uu Brown-out R eset 000h 000x xuuu---- --u0 Interrupt W ake-up from SLEEP PC + 1(1) uuu1 0uuu---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1. Register Ad dress Power-on Reset

MCLR Rese t during normal operation
MCLR Rese t during SLEEP
WDT Reset
Brown-out R eset (1)
W ake up from SLEEP through interrupt
W ake up from SLEEP through WDT time-out W - xxxx xxxxuuuu uuuu uuuu uuuu INDF 00h - - - TMR0 01h xxxx xxxxuuuu uuuu uuuu uuuu PCL 02h 0000 00000000 0000 PC + 1(3) STATUS 03h 0001 1xxx000q quuu(4) uuuq quuu(4) FSR 04h xxxx xxxxuuuu uuuu uuuu uuuu POR TA 05h ---x xxxx---u uuuu ---u uuuu POR TB 06h xxxx xxxxuuuu uuuu uuuu uuuu CMCON 1Fh 00-- 000000-- 0000 uu-- uuuu PCLA TH 0Ah ---0 0000---0 0000 ---u uuuu INTCON 0Bh 0000 000x0000 000u uuuu uqqq(2) OPTION 81h 1111 11111111 1111 uuuu uuuu TRISA 85h ---1 1111---1 1111 ---u uuuu TRISB 86h 1111 11111111 1111 uuuu uuuu PCON 8Eh ---- --0x---- --uq(1,6) ---- --uu VRCON 9Fh 000- 0000000- 0000 uuu- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition. Note 1: If VDD goes too low, Pow er-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 9-6 for reset value for speciﬁc condition. 5: If wake-up was due to comparator input changing, then bit 6 = 1. All other interrupts generating a wake-up will cause bit 6 = u. 6: If reset was due to brown-out, then bit 0 = 0. All other resets will cause bit 0 = u.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 55 PIC16C62X

9.5 Interrupts

The PIC16C62X has 4 sources of interrupt:

External interrupt RB0/INT
TMR0 o verﬂow interrupt
PortB change interrupts (pins RB7:RB 4)
Compar ator interrupt The interrupt control register (INTCON) records individual interrupt requests in ﬂag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset. The “return from interrupt” instruction, RETFIE, exits interrupt routine as well as sets the GIE bit, which re-enable RB0/INT interrupts. The INT pin interrupt, the RB port change interrupt and the TMR0 o verﬂow interrupt ﬂags are contained in the INTCON register. The peripheral interrupt ﬂag is contained in the special register PIR1. The corresponding interrupt enable bit is contained in special registers PIE1. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in soft- w are before re-enabling interrupts to avoid RB0/INT recursive interrupts. For external interrupt events, such as the INT pin or POR TB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 9-16). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 1: Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit. 2: Wh en an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. FIGURE 9-15: INTERRUPT LOGIC RBIF RBIE T0IF T0IE INTF INTE GIE PEIE W ake-up (If in SLEEP mode) Interrupt to CPU CMIE CMIF

DS30235G -page 56 Preliminary Ó 1998 Microchip Technology Inc.

9.5.1 RB0/INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or fall- ing, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RB0/INT interrupt can w ake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.8 for details on SLEEP and Figure 9-18 for timing of w ake-up from SLEEP through RB0/INT interrupt.

9.5.2 TMR0 INTERR UPT

An overﬂow (FFh ﬁ 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enab led/disabled b y setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0.

9.5.3 POR TB INTERR UPT

An input change on POR TB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/dis- abled by setting/clearing the RBIE (INTCON<4>) bit. For operation of POR TB (Section 5.2).

9.5.4 COMPAR ATOR INTERR UPT

See Section 7.6 for complete description of comparator interrupts. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF inter- rupt ﬂag may not get set. FIGURE 9-16: INT PIN INTERRUPT TIMING TABLE 9-8: SUMMAR Y OF INTERRUPT REGISTER S Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1) 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x0000 000u Note1: Other (non pow er-up) resets include MCLR reset, Brown-out Reset and W atchdog Timer Reset during normal operation. Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 OSC1 CLK OUT INT pin INTF ﬂag (INTCON<1>) GIE bit (INTCON<7>) INSTR UCTION FLO W PC Instruction fetched Instruction executed Interrupt Latency PC PC+1 PC+1 0004h 0005h Inst (0004h) Inst (0005h) Dumm y Cycle Inst (PC) Inst (PC+1) Inst (PC-1) Inst (0004h)Dumm y CycleInst (PC) Note 1: INTF ﬂag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 57 PIC16C62X

9.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- isters during an interrupt e.g. W register and STATUS register. This will have to be implemented in software. Example 9-1 stores and restores the STATUS and W registers. The user register, W_TEMP , must be deﬁned in both banks and must be deﬁned at the same offset from the bank base address (i.e., W_TEMP is deﬁned at 0x20 in Bank 0 and it must also be deﬁned at 0xA0 in Bank 1). The user register, STATUS_TEMP , must be deﬁned in Bank 0. The Example 9-1:

Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit register)
Restores the W register EXAMPLE 9-1: SA VING THE STATUS AND W REGISTER S IN RAM MOVWFW_TEMP ;copy W to temp register, ;could be in either bank SWAPFSTATUS,W;swap status to be saved into W BCF STATUS,RP0;change to bank 0 regardless ;of current bank MOVWFSTATUS_TEMP;save status to bank 0 ;register : (ISR) SWAPFSTATUS_TEMP,W;swap STATUS_TEMP register ;into W, sets bank to original ;state MOVWFSTATUS ;move W into STATUS register SWAPFW_TEMP,F;swap W_TEMP SWAPFW_TEMP,W;swap W_TEMP into W

9.7 W atchdog Timer (WDT)

The watchdog timer is a free running on-chip RC oscil- lator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode , a WDT time-out causes the device to w ake-up and continue with normal operation. The WDT can be permanently disabled by programming the con- ﬁguration bit WDTE as clear (Section 9.1).

9.7.1 WDT P ER IOD

The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with tempera- ture, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT , and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a W atchdog Timer time-out.

9.7.2 WDT PROG R AMMING CONSIDER ATIONS

It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs.

DS30235G -page 58 Preliminary Ó 1998 Microchip Technology Inc. FIGURE 9-17: W ATC HDOG TIMER BLOC K DIAGRAM TABLE 9-9: SUMMAR Y OF W ATC HDOG TIMER REGISTER S Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Conﬁg. bits --- BO R EN CP1 CP0 PWR TE WDTE FOSC1 FOSC0 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend:Shaded cells are not used by the W atchdog Timer. Note: _ = Unimplemented location, read as “0” + = Reserved for future use From TMR0 Clock Source (Figure 6-6) To TMR0 (Figure 6-6) PostscalerW atchdog Timer M U X PSA 8 - to -1 MUX PSA WDT Time-out WDT Enable Bit PS <2:0> Note: T0SE, T0CS , PSA, PS0-PS2 are bits in the OPTION register. MUX

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 59 PIC16C62X

9.8 Power-Down Mode (SLEEP)

The P ow er-down mode is entered by executing a SLEEP instruction. If enabled, the W atchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP w as executed (driving high, low, or hi-impedance). For low est current consumption in this mode, all I/O pins should be either at VDD , or VSS , with no external circuitry drawing current from the I/O pin and the com- parators and VREF should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low exter- nally to avoid switching currents caused by ﬂoating inputs. The T0CKI input should also be at VDD or VSS for low est current consumption. The contribution from on chip pull-ups on POR TB should be considered. The MCLR pin must be at a logic high level (VIHMC ).

9.8.1 W AK E-UP FROM SLEEP

The device can wake-up from SLEEP through one of the following events: 1. External reset input on MCLR pin 2. W atchdog Timer W ake-up (if WDT w as enabled) 3. Interrupt from RB0/INT pin, RB Port change, or the Peripheral Interrupt (Comparator). The ﬁrst event will cause a device reset. The two latter events are considered a continuation of program exe- cution. The TO and PD bits in the STATUS register can be used to determine the cause of device reset. PD bit, which is set on pow er-up is cleared when SLEEP is invoked. TO bit is cleared if WDT W ake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the correspond- ing interrupt enable bit must be set (enabled). W ake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the inter- rupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up. Note: It should be noted that a RESET generated by a WDT time-out does not drive MCLR pin low. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt ﬂag bits set, the device will immediately wakeup from sleep. The sleep instruction is completely executed. FIGURE 9-18: W AKE-UP FR OM SLEEP THR OUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLK OUT(4) INT pin INTF ﬂag (INTCON<1>) GIE bit (INTCON<7>) INSTR UCTION FLO W PC Instruction fetched Instruction executed PC PC+1 PC+2 Inst(PC) = SLEEP Inst(PC - 1) Inst(PC + 1) SLEEP Processor in SLEEP Interrupt Latency (Note 2) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h)Dumm y cycle PC + 2 0004h 0005h Dumm y cycle TOST (2) PC+2 Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLK OUT is not available in these osc modes, but shown here for timing reference.

DS30235G -page 60 Preliminary Ó 1998 Microchip Technology Inc.

9.9 Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memor y can be read out for veriﬁcation purposes.

9.10 ID Locations

Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal e xecution but are readable and writable during program/verify. Only the least signiﬁcant 4 bits of the ID locations are used. Note: Microchip does not recommend code protecting window ed devices.

9.11 In-Circuit Serial Programming

The PIC16C62X m icrocontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for pow er, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed de vices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmw are or a custom ﬁrmw are to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP ) pin from VIL to VIHH (see programming speciﬁcation). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode , the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command w as a load or a read. For complete details of serial prog ramming, please ref er to the PIC16C6X/7X/9XX Prog ramming Speciﬁ cations (#DS30228). A typical in-circuit serial programming connection is shown in Figure 9-19. FIGURE 9-19: TYPICA L IN-CIRCUIT SERIAL PR O GRAMMING CONNECTION External Connector Signals To Normal Connections To Normal Connections PIC16C 62X VDD VSS MCLR /VPP RB6 RB7 +5V VPP CLK Data I/O VDD

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 61 PIC16C62X

10.0 INSTRUCTION SET SUMMAR Y

Each PIC16C62X instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C62X instruc- tion set summary in Table 10-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 10-1 shows the opcode ﬁeld descriptions. For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction. The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the ﬁle register speciﬁed in the instruction. For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. TAB LE 10-1: OPCODE FIELD DESCRIPTIONS Field Description f Register ﬁle address (0x00 to 0x7F) W W orking register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W , d = 1: store result in ﬁle register f. Default is d = 1 labelLabel name TOSTop of Stack PCProgram Counter PCLATHProgram Counter High Latch GIEGlobal Interrupt Enable bit WDTW atchdog Timer/Counter TOTime-out bit PDPow er-down bit destDestination either the W register or the speciﬁed register ﬁle location [ ] Options ( )Contents ﬁ Assigned to < > Register bit ﬁeld ˛ In the set of italicsUser deﬁned term (font is courier) The instruction set is highly orthogonal and is grouped into three basic categories:

Byte-oriented operations
Bit-oriented operations
Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP . One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 ms. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ms. Table 10-1 lists the instructions recognized by the MP ASM assemb ler. Figure 10-1 shows the three general formats that the instructions can have. All examples use the following format to represent a hexadecimal number: 0xhh where h signiﬁes a hexadecimal digit. FIGURE 10-1: GENERAL FORMAT F OR INSTRUCTIONS Note: To maintain upward c ompatibility with future PICmicro™ products, do not use the OPTION and TRIS instructions. Byte-oriented ﬁle register operations 13 8 7 6 0 d = 0 for destination W OPCODE d f (FILE #) d = 1 for destination f f = 7-bit ﬁle register address Bit-oriented ﬁle register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit ﬁle register address Literal and control operations 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value General CALL and GOTO instructions only

DS30235G -page 62 Preliminary Ó 1998 Microchip Technology Inc. TAB LE 10-2: PIC16C62X INSTRUCTION SET Mnemonic, Operands Description Cyc les 14-Bit Opcode Status Affected Notes MS b LS b BYTE-ORIENTED FILE REGISTER OPERA TIONS ADD WF AND WF CLRF CLR W COMF DECF DECFSZ INCF INCFSZ IORWF MO VF MO VWF NOP RLF RRF SUBWF SW APF XOR WF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Mo ve f Mo ve W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Sw ap nibbles in f Exclusive OR W with f 1(2) 1(2) 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1,2 1,2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERA TIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 LITERAL AND CONTR OL OPERA TIONS ADDL W ANDL W CALL CLR WDT GO TO IORLW MO VLW RETFIE RETL W RETURN SLEEP SUBL W XORL W k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear W atchdog Timer Go to address Inclusive OR literal with W Mo ve literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z T O ,PD Z TO ,PD C,DC,Z Z Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 63 PIC16C62X

10.1 Instruction Descriptions

Syntax: [ label ] ADDL W k Operands: 0 £ k £ 255 Operation: (W) + k ﬁ (W ) Status Affected: C, DC, Z Encoding: 11 111xkkkkkkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. W ords: 1 Cycles: 1 Example ADDLW0x15 Before Instruction W = 0x10 After Instruction W = 0x25 ADD WF Ad d W and f Syntax: [ label ] ADD WF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) + (f) ﬁ (dest) Status Affected: C, DC, Z Encoding: 00 0111dfffffff Description: Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example ADDWFFSR,0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 ANDL W AND Literal with W Syntax: [ label ] ANDL W k Operands: 0 £ k £ 255 Operation: (W) .AND. (k) ﬁ (W ) Status Affected: Z Encoding: 11 1001kkkkkkkk Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example ANDLW0x5F Before Instruction W = 0xA3 After Instruction W = 0x03 AND WF AND W with f Syntax: [ label ] AND WF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) .AND. (f) ﬁ (dest) Status Affected: Z Encoding: 00 0101dfffffff Description: AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example ANDWFFSR,1 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0x17 FSR = 0x02

DS30235G -page 64 Preliminary Ó 1998 Microchip Technology Inc. BCF Bit Clear f Syntax: [ label ] BCF f,b Operands: 0 £ f £ 127 0 £ b £ 7 Operation: 0 ﬁ (f<b>) Status Affected: None Encoding: 01 00bbbfffffff Description: Bit 'b' in register 'f' is cleared. W ords: 1 Cycles: 1 Example BCF FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0 £ f £ 127 0 £ b £ 7 Operation: 1 ﬁ (f<b>) Status Affected: None Encoding: 01 01bbbfffffff Description: Bit 'b' in register 'f' is set. W ords: 1 Cycles: 1 Example BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A BTFSC B it Test, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 £ f £ 127 0 £ b £ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 01 10bb bfffffff Description: If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. W ords: 1 Cycles: 1(2) Example HERE FALSE TRUE BTFSC GOTO FLAG,1 PROCESS_CODE Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address TRUE if FLAG<1>= 1, PC = address FALSE

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 65 PIC16C62X BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 £ f £ 127 0 £ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding: 01 11bbbfffffff Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. W ords: 1 Cycles: 1(2) Example HERE FALSE TRUE BTFSS GOTO FLAG,1 PROCESS_CODE Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE CALL Call Subroutine Syntax: [ label ] CALL k Operands: 0 £ k £ 2047 Operation: (PC)+ 1ﬁ TOS , k ﬁ PC<10:0>, (PCLATH<4:3>) ﬁ PC<12:11> Status Affected: None Encoding: 10 0kkkkkkkkkkk Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. W ords: 1 Cycles: 2 Example HERECALL THERE Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1 CLRF Clear f Syntax: [ label ] CLRF f Operands: 0 £ f £ 127 Operation: 00h ﬁ (f) 1 ﬁ Z Status Affected: Z Encoding: 00 00011fffffff Description: The contents of register 'f' are cleared and the Z bit is set. W ords: 1 Cycles: 1 Example CLRF FLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 Z = 1 CLR W Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h ﬁ (W) 1 ﬁ Z Status Affected: Z Encoding: 00 000100000011 Description: W register is cleared. Zero bit (Z) is set. W ords: 1 Cycles: 1 Example CLRW Before Instruction W = 0x5A After Instruction W = 0x00 Z = 1

DS30235G -page 66 Preliminary Ó 1998 Microchip Technology Inc. CLR WDT Clear W atchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h ﬁ WDT 0 ﬁ WDT prescaler, 1 ﬁ TO 1 ﬁ PD Status Affected: TO , PD Encoding: 00 000001100100 Description: CLRWDT instruction resets the W atchdog Timer. It also resets the prescaler of the WDT . Status bits TO and PD are set. W ords: 1 Cycles: 1 Example CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler= 0 TO = 1 PD = 1 COMF Complement f Syntax: [ label ] COMF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) ﬁ (dest) Status Affected: Z Encoding: 00 1001dfffffff Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W . If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example COMF REG1,0 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W = 0xEC DECF Decrement f Syntax: [ label ] DECF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) - 1 ﬁ (dest) Status Affected: Z Encoding: 00 0011dfffffff Description: Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example DECF CNT,1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) - 1 ﬁ (dest); skip if result = 0 Status Affected: None Encoding: 00 1011dfffffff Description: The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction. W ords: 1 Cycles: 1(2) Example HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE • Before Instruction PC = address HERE After Instruction CNT = CNT - 1 if CNT= 0, PC = address CONTINUE if CNT„ 0, PC = address HERE+1

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 67 PIC16C62X GO TO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 £ k £ 2047 Operation: k ﬁ PC<10:0> PCLA TH<4:3> ﬁ PC<12:11> Status Affected: None Encoding: 10 1kkkkkkkkkkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. W ords: 1 Cycles: 2 Example GOTO THERE After Instruction PC = Address THERE INCF Increment f Syntax: [ label ] INCF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) + 1 ﬁ (dest) Status Affected: Z Encoding: 00 1010dfffffff Description: The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. W ords: 1 Cycles: 1 Example INCFCNT,1 Before Instruction CNT = 0xFF Z = 0 After Instruction CNT = 0x00 Z = 1 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) + 1 ﬁ (dest), skip if result = 0 Status Affected: None Encoding: 00 1111dfffffff Description: The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction. W ords: 1 Cycles: 1(2) Example HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE • Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT„ 0, PC = address HERE +1 IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k Operands: 0 £ k £ 255 Operation: (W) .OR. k ﬁ (W) Status Affected: Z Encoding: 11 1000kkkkkkkk Description: The contents of the W register is O R’ed with the eight bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example IORLW0x35 Before Instruction W = 0x9A After Instruction W = 0xBF Z = 1

DS30235G -page 68 Preliminary Ó 1998 Microchip Technology Inc. IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) .OR. (f) ﬁ (dest) Status Affected: Z Encoding: 00 0100dfffffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. W ords: 1 Cycles: 1 Example IORWF RESULT, 0 Before Instruction RESUL T = 0x13 W = 0x91 After Instruction RESUL T = 0x13 W = 0x93 Z = 1 MO VLW Mo ve Literal to W Syntax: [ label ] MOVLW k Operands: 0 £ k £ 255 Operation: k ﬁ (W) Status Affected: None Encoding: 11 00xx kkkkkkkk Description: The eight bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s. W ords: 1 Cycles: 1 Example MOVLW0x5A After Instruction W = 0x5A MO VF Mo ve f Syntax: [ label ] MOVF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) ﬁ (dest) Status Affected: Z Encoding: 00 1000dfffffff Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is ﬁle register f itself. d = 1 is useful to test a ﬁle register since status ﬂag Z is affected. W ords: 1 Cycles: 1 Example MOVFFSR,0 After Instruction W = value in FSR register Z = 1 MO VWF Mo ve W to f Syntax: [ label ] MOVWF f Operands: 0 £ f £ 127 Operation: (W) ﬁ (f) Status Affected: None Encoding: 00 00001fffffff Description: Mo ve data from W register to register 'f'. W ords: 1 Cycles: 1 Example MOVWF OPTION Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 69 PIC16C62X NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Encoding: 00 00000xx00000 Description: No operation. W ords: 1 Cycles: 1 Example NOP OPTION Load Option Register Syntax: [ label ] OPTION Operands: None Operation: (W ) ﬁ OPTION Status Affected:None Encoding: 00 000001100010 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. W ords: 1 Cycles: 1 Example To maintain upward compatibility with future PICmicro™ p roducts, do not use this instruction. RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None Operation: TOS ﬁ PC, 1 ﬁ GIE Status Affected: None Encoding: 00 000000001001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, G IE (INTCON<7>). This is a two-cycle instruction. W ords: 1 Cycles: 2 Example RETFIE After Interrupt PC = TOS GIE = 1 RETL W Return with Literal in W Syntax: [ label ] RETLW k Operands: 0 £ k £ 255 Operation: k ﬁ (W ); TOS ﬁ PC Status Affected: None Encoding: 11 01xxkkkkkkkk Description: The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. W ords: 1 Cycles: 2 Example TABLE CALL TABLE;W contains table ;offset value

;W now has table value ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8

DS30235G -page 70 Preliminary Ó 1998 Microchip Technology Inc. RETURN Return from Subr outine Syntax: [ label ] RETURN Operands: None Operation: TOS ﬁ PC Status Affected: None Encoding: 00 000000001000 Description: Return from subroutine. The stack is POP ed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. W ords: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: See description below Status Affected: C Encoding: 00 1101dfffffff Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 Register fC RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: See description below Status Affected: C Encoding: 00 1100dfffffff Description: The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. W ords: 1 Cycles: 1 Example RRF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0 SLEEP Syntax: [ label ] SLEEP Operands: None Operation: 00h ﬁ WDT , 0 ﬁ WDT prescaler, 1 ﬁ TO , 0 ﬁ PD Status Affected: TO , PD Encoding: 00 000001100011 Description: The pow er-down status bit, PD is cleared. Time-out status bit, TO is set. W atchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 9.8 for more details. W ords: 1 Cycles: 1 Example: SLEEP Register fC

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 71 PIC16C62X SUBL W Subtract W from Literal Syntax: [ label ] SUBL W k Operands: 0 £ k £ 255 Operation: k - (W) ﬁ (W) Status Affected: C, DC, Z Encoding: 11 110xkkkkkkkk Description: The W register is subtracted (2’s com- plement method) from the eight bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example 1: SUBLW0x02 Before Instruction W = 1 C = ? After Instruction W = 1 C = 1; result is posi- tive Example 2: Before Instruction W = 2 C = ? After Instruction W = 0 C = 1; result is zero Example 3: Before Instruction W = 3 C = ? After Instruction W = 0xFF C = 0; result is nega- tive SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f) - (W) ﬁ (dest) Status Affected: C, DC, Z Encoding: 00 0010dfffffff Description: Subtract (2’s complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example 1: SUBWFREG1,1 Before Instruction REG1 = 3 W = 2 C = ? After Instruction REG1 = 1 W = 2 C = 1; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = 0xFF W = 2 C = 0; result is negative

DS30235G -page 72 Preliminary Ó 1998 Microchip Technology Inc. SW APF Swap Nibbles in f Syntax: [ label ] SW APF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (f<3:0>) ﬁ (dest<7:4>), (f<7:4>) ﬁ (dest<3:0>) Status Affected: None Encoding: 00 1110dfffffff Description: The upper and low er nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. W ords: 1 Cycles: 1 Example SWAPFREG,0 Before Instruction REG1 = 0xA5 After Instruction REG1 = 0xA5 W = 0x5A TRIS Load TRIS Register Syntax: [ label ] TRIS f Operands: 5 £ f £ 7 Operation: (W ) ﬁ TRIS register f; Status Affected:None Encoding: 00 000001100fff Description: The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them. W ords: 1 Cycles: 1 Example To maintain upward compatibility with future PICmicro™ p roducts, do not use this instruction. XORL W Exclusive OR Literal with W Syntax: [ label ] XORL W k Operands: 0 £ k £ 255 Operation: (W) .XOR. k ﬁ (W) Status Affected: Z Encoding: 11 1010kkkkkkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example: XORLW0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A XOR WF Exclusive OR W with f Syntax: [ label ] XOR WF f,d Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) .XOR. (f) ﬁ (dest) Status Affected: Z Encoding: 00 0110dfffffff Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example XORWFREG1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 73 PIC16C62X

11.0 DE VELOPMENT SUPPOR T

11.1 De velopme nt Tools

The PICmicroä microcontrollers are supported with a full range of hardware and software development tools:

MPLAB™-ICE Real-Time In-Circuit Emulator
ICEPICä Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator
PR O MA TE â II Universal Programmer
PICSTAR Tâ Plus Entry-Level Prototype Programmer
SIMICE
PICDEM-1 Low-Cost Demonstration Board
PICDEM-2 Low-Cost Demonstration Board
PICDEM-3 Low-Cost Demonstration Board
MP ASM Assemb ler
MPLAB ä SIM Software Simulator
MPLAB-C17 (C Compiler)
Fuzzy Logic Development System (fuzzyTECH â -MP)
KEE LOQ ® Evaluation Kits and Programmer

11.2 MPLAB-ICE: High Performance

Universal In-Circuit Emulator with MPLAB IDE The MPLAB-ICE Univ ersal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is sup- plied with the MPLAB Integrated Development Environ- ment (IDE), which allows editing, “make” and download, and source debugging from a single envi- ronment. Interchangeable processor modules allow the system to be easily reconﬁgured for emulation of different pro- cessors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip micro- controllers. The MPLAB-ICE Em ulator System has been designed as a real-time emulation system with advanced fea- tures that are generally found on more e xpensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windowsâ 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is a vailable in tw o v ersions. MPLAB- ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor mod- ules with the MPLAB-ICE 2000. This is a full-featured em ulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PICmicro MCU .

11.3 ICEPIC: Low-Cost PICmicro™

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through Pentiumä based machines under Windows 3.x, Windows 95, or Win- dows NT environment. ICEPIC features real time, non- intrusive emulation.

11.4 PR O MA TE II: Universal Programmer

The PRO MA TE II Universal Programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MA TE II is CE compliant. The PR O MA TE II has programmab le VDD and VPP supplies which allows it to verify programmed memor y at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assemb ly to support various package types. In stand- alone mode the PRO MA TE II can read, verify or pro- gram PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX de vices. It can also set conﬁguration and code-protect bits in this mode.

11.5 PICSTAR T Plus Entry Level

The PICSTAR T programmer is an easy-to-use, low- cost prototype programmer . It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTAR T Plus is not recommended for production programming. PICSTAR T Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be sup- ported with an adapter socket. PICSTAR T Plus is CE compliant.

DS30235G -page 74 Preliminary Ó 1998 Microchip Technology Inc.

11.6 SIMICE Entry-Level Hardware

SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIM- ICE and MPLAB-SIM r un under Microchip Technol- ogy’s MPLAB Integrated Development Environment (IDE) software. Speciﬁcally, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro™ 8-bit microcon- trollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus ﬁles. SIMICE is a valuable debugging tool for entry- level system development.

11.7 PICDEM-1 Low-Cost PICmicro

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrol- lers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs . The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PR O MA TE II or PICST AR T-Plus programmer , and easily test ﬁrm- w are. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and down load the ﬁrmw are to the emulator for testing. Additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to POR TB .

11.8 PICDEM-2 Low-Cost PIC16CXX

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs . The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MA TE II pro- grammer or PICSTAR T-Plus, and easily test ﬁrmw are. The MPLAB-ICE em ulator may also be used with the PICDEM-2 board to test ﬁrmw are. Additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- tion to an LCD module and a keypad.

11.9 PICDEM-3 Low-Cost PIC16CXXX

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the neces- sary hardware and software is included to run the basic demonstration programs . The user can pro- gram the sample microcontrollers provided with the PICDEM-3 board, on a PRO MA TE II program- mer or PICSTAR T Plus with an adapter socket, and easily test ﬁrmw are. The MPLAB-ICE em ulator may also be used with the PICDEM-3 board to test ﬁrm- w are. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an addi- tional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A sim- ple serial interface allows the user to construct a hard- w are demultiplexer for the LCD signals.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 75 PIC16C62X

11.10 MPLAB Integrated Development

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcon- troller market. MPLAB is a windows based application which contains:

A full featured editor
Three operating modes - editor - em ulator - simulator
A project manager
Customizable tool bar and key mapping
A status bar with project information
Extensive on-line help MPLAB allows you to:
Edit your source ﬁles (either assembly or ‘C’)
One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information)
Deb ug using: - source ﬁles - absolute listing ﬁle The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured em ulator with minimal retraining due to development tools.

11.11 Assemb ler (MPASM)

The MP ASM Univ ersal Macro Assembler is a PC- hosted symbolic assembler. It supports all microcon- troller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MP ASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers . MP ASM allows full symbolic debugging from MPLAB- ICE, Microchip’s Universal Emulator System. MP ASM has the following features to assist in develop- ing software for speciﬁc use applications.

Provides translation of Assembler source code to object code for all Microchip microcontrollers.
Macro assembly capability.
Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.
Supports Hex (default), Decimal and Octal source and listing formats. MP ASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.

11.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Softw are Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MP ASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

11.13 MPLAB-C17 Compiler

The MPLAB-C17 Code De velopment System is a complete ANSI ‘C’ compiler and integrated develop- ment environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides pow erful inte- gration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler pro- vides symbol information that is compatible with the MPLAB IDE memor y display.

11.14 Fuzzy Logic Development System

(fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive w orking knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP , Edition for imple- menting more complex systems. Both versions include Microchip’s fuzzyLAB ä demon- stration board for hands-on experience with fuzzy logic systems implementation.

11.15 SEEV AL â Evaluation and

The SEEV AL SEEPR OM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs . The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsÔ and secure serials. The Total EnduranceÔ Disk is included to aid in trade- off analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

DS30235G -page 76 Preliminary Ó 1998 Microchip Technology Inc.

11.16 K EE LOQ â Evaluation and

KEE LOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 77 PIC16C62X TAB LE 11-1: DE VELOPMENT TOOLS FR OM MICR OC HIP PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 24CXX 25CXX 93CXX HCS200 HCS300 HCS301 Emulator Products MPLAB™-ICE ü ü ü ü ü ü ü ü ü ü ICEPICä Low-Cost In-Circuit Emulator ü ü ü ü ü ü Software Tools MPLAB ä Integrated Development Environment ü ü ü ü ü ü ü ü ü ü MPLAB ä C17* Compiler ü ü fuzzyTECH â -MP Explorer/Edition Fuzzy Logic Dev. Tool ü ü ü ü ü ü ü ü ü Total Enduranceä Software Model ü Programmers PICSTART â Plus Low-Cost Universal Dev. Kit ü ü ü ü ü ü ü ü ü ü PRO MATE â II Universal Programmer ü ü ü ü ü ü ü ü ü ü ü ü KEELOQ â Programmer ü Demo Boards SEEVAL â Designers Kit ü SIMICE ü ü PICDEM-14A ü PICDEM-1 ü ü ü ü PICDEM-2 ü ü PICDEM-3 ü K EE LOQ ® Evaluation Kit ü K EE LOQ Transponder Kit ü

DS30235G -page 78 Preliminary Ó 1998 Microchip Technology Inc. NOTES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 79 PIC16C62X 12.0 89ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings † Note 1:Pow er dissipation is calculated as follows: PDIS = VDD x {IDD - å IOH } + å {(VDD -VOH ) x IOH } + å (VO l x IOL ) † NO TICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS . Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS .

DS30235G -page 80 Preliminary Ó 1998 Microchip Technology Inc. TABLE 12-1: CR OSS REF ERENCE OF DE VICE SPECS F OR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMER CIAL DEVICES) OSC PIC16C62X-04 PIC16C62X A-04 PIC16C62X-20 PIC16C62X A-20 PIC16LC62X-04 PIC16C62X/JW PIC16C62XA/JW RC VDD : 3.0V to 6.0V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. VDD : 3.0V to 5.5V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. VDD : 3.0V to 6.0V IDD : 1.8 mA typ. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 4.0 MHz max. VDD : 3.0V to 5.5V IDD : 1.8 mA typ. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 4.0 MHz max. VDD : 3.0V to 6.0V IDD : 1.4 mA typ. @3.0V IPD : 0.7 mA typ. @3.0V Freq: 4.0 MHz max. VDD : 3.0V to 6.0V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. VDD : 3.0V to 5.5V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. XT VDD : 3.0V to 6.0V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. VDD : 3.0V to 5.5V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. VDD : 3.0V to 6.0V IDD : 1.8 mA typ. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 4.0 MHz max. VDD : 3.0V to 5.5V IDD : 1.8 mA typ. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 4.0 MHz max. VDD : 3.0V to 6.0V IDD : 1.4 mA typ. @3.0V IPD : 0.7 mA typ. @3.0V Freq: 4.0 MHz max. VDD : 3.0V to 6.0V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. VDD : 3.0V to 5.5V IDD : 3.3 mA max. @5.5V IPD : 20 mA max. @4.0V Freq: 4.0 MHz max. HS VDD : 4.5V to 5.5V IDD : 9.0 mA typ. @5.5V IPD : 1.0 mA typ. @4.0V Freq: 4.0 MHz max. VDD : 4.5V to 5.5V IDD : 3.5 mA typ. @5.5V IPD : 1.0 mA typ. @4.0V Freq: 4.0 MHz max. VDD : 4.5V to 5.5V IDD : 20 mA max. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 20 MHz max. VDD : 4.5V to 5.5V IDD : 7.5 mA max. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 20 MHz max. N/A VDD : 4.5V to 5.5V IDD : 20 mA max. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 20 MHz max. VDD : 4.5V to 5.5V IDD : 20 mA max. @5.5V IPD : 1.0 mA typ. @4.5V Freq: 20 MHz max. LP VDD : 3.0V to 6.0V IDD : 35 mA typ. @32 kHz, 3.0V I PD : 1.0 mA typ. @4.0 V Freq: 200 kHz max . VDD : 3.0V to 5.5V IDD : 35 mA typ. @32 kHz, 3.0V I PD : 1.0 mA typ. @4.0 V Freq: 200 kHz max . N/A N/A VDD : 2.5V to 6.0V IDD : 32 mA max. @32 kHz, 3.0V I PD : 9.0 mA max. @3.0V Freq: 200 kHz max. VDD : 2.5V to 6.0V IDD : 32 mA max. @32 kHz, 3.0V I PD : 9.0 mA Max. @3.0V Freq: 200 kHz max. VDD : 3.0V to 5.5V IDD : 32 mA max. @32 kHz, 3.0V IPD : 9.0 mA Max. @3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recom- mended that the user select the device type that the speciﬁcations required.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 81 PIC16C62X

12.1 DC CHARA CTERISTICS: PIC16C62X-04 (Commer cial, Industrial, Extended)

PIC16C62X-20 (Commer cial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature –40°C £ TA £ +85°C for industrial and 0°C £ TA £ +70°C for commercial and –40°C £ TA £ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions D001 D001A Vdd Supply Voltage 3.0 4.5 6.0 5.5 V V XT, RC and LP osc conﬁguration HS osc conﬁguration D002 Vdr RAM Data Retention Voltage (Note 1) – 1.5* – V Device in SLEEP mode D003 Vpor VDD start voltage to ensure Pow er-on Reset – Vss – V See section on pow er-on reset for details D004 Svdd VDD rise rate to ensure Pow er-on Reset 0.05* – – V/ms See section on pow er-on reset for details D005 VBOR Brown-out Detect Voltage 3.7 3.7 4.0 4.0 4.3 4.4 V BOREN conﬁ guration bit is cleared (Extended) D010 D010A D013 Idd Supply Current (Note 2) – 1.8 9.0 3.3 mA mA mA XT and RC osc conﬁguration FOSC = 4 MHz, VDD = 5.5V, WDT dis- abled (Note 4) LP osc conﬁguration, PIC16C62X-04 only F OSC = 32 kHz, VDD = 4.0V, WDT dis- abled HS osc conﬁguration FOSC = 20 MHz, VDD = 5.5V, WDT dis- abled D020 Ipd Pow er Down Current (Note 3) – 1.0 2.5 mA mA VDD =4.0V, WDT disabled (125°C) D023 DIWDT DIBOR DICOMP DIVREF WDT Current (Note 5) Brown-out Reset Current (Note 5) Compar ator Current for each Com- parator (Note 5) VREF Current (Note 5) 6.0 350 425 100 300 mA mA mA mA mA V DD =4.0V (125°C) BOR enabled, VDD = 5.0V VDD = 4.0V VDD = 4.0V * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be low ered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. The test conditions for all I DD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD , MCLR = VDD ; WDT enab led/disabled as speciﬁed. 3: The pow er down current in SLEEP mode does not depend on the oscillator type. Pow er down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS . 4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the form ula Ir = VDD /2Rext (mA) with Rext in kW . 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.

DS30235G -page 82 Preliminary Ó 1998 Microchip Technology Inc.

12.2 DC CHARA CTERISTICS: PIC16LC62X-04 (Commer cial, Industrial)

Standard Operating Conditions (unless otherwise stated) Operating temperature –40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial and –40˚C £ TA £ +125˚C for extended Operating voltage VDD range as described in DC spec Table 12-1 and Table 12-2 Param No. Sym Characteristic Min Typ† Max Units Conditions D001 VDD Supply Voltage 3.0 2.5 - 6.0 6.0 V XT and RC osc conﬁguration LP osc conﬁguration D002 VDR RAM Data Retention Voltage (Note 1) – 1.5* – V Device in SLEEP mode D003 VPOR VDD start voltage to ensure Pow er-on Reset – VSS – V See section on Pow er-on Reset for details D004 SVDD VDD rise rate to ensure Pow er-on Reset 0.05* – – V/ms See section on Pow er-on Reset for details D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.3 V BOREN conﬁ guration bit is cleared D010 D010A IDD Supply Current (Note 2) – 1.4 2.5 mA mA XT and RC osc conﬁguration FOSC = 2.0 MHz, VDD = 3.0V, WDT dis- abled (Note 4) LP osc conﬁguration FOSC = 32 kHz, VDD = 3.0V, WDT dis- abled D020 IPD Pow er Down Current (Note 3) – 0.7 2 mA VDD =3.0V, WDT disabled D023 DIWDT DIBOR DICOMP DIVREF WDT Current (Note 5) Brown-out Reset Current (Note 5) Compar ator Current for each Compar ator (Note 5) V REF Current (Note 5) 6.0 350 425 100 300 mA mA mA mA V DD =3.0V BOR enabled, VDD = 5.0V VDD = 3.0V VDD = 3.0V * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be low ered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. The test conditions for all IDD measurements in active operation mode are: OSC1=e xternal square wave, from rail to rail; all I/O pins tristated, pulled to V DD , MCLR = VDD ; WDT enab led/disabled as speciﬁed. 3: The pow er down current in SLEEP mode does not depend on the oscillator type. Pow er down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD to VSS . 4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the form ula Ir = VDD /2Rext (mA) with Rext in kW . 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 83 PIC16C62X

12.3 DC CHARA CTERISTICS: PIC16C62XA/CR62XA-04 (Commer cial, Industrial, Extended)

PIC16C62XA/CR62XA-20 (Commer cial, Industrial, Extended) PIC16LC62XA/LCR62XA-04 (Commer cial, Industrial) PIC16LC62XA/LCR62XA-20 (Commer cial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature –40°C £ TA £ +85°C for industrial and 0°C £ TA £ +70°C for commercial and –40°C £ TA £ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions D001 D001A VDD Supply Voltage 3.0 4.5 5.5 5.5 V V XT, RC and LP osc conﬁguration HS osc conﬁguration D002 VDR RAM Data Retention Voltage (Note 1) – 1.5* – V Device in SLEEP mode D003 VPOR VDD start voltage to ensure Pow er-on Reset – VSS – V See section on pow er-on reset for details D004 SVDD VDD rise rate to ensure Pow er-on Reset 0.05* – – V/ms See section on pow er-on reset for details D005 VBOR Brown-out Detect Voltage 3.7 3.7 4.0 4.0 4.3 4.4 V BOREN conﬁ guration bit is cleared (Extended) D010 D010A D013 IDD Supply Current (Note 2) – 1.2 3.0 2.0 7.5 mA mA mA XT and RC osc conﬁguration FOSC = 4 MHz, VDD = 5.5V, WDT disabled (Note 4) LP osc conﬁguration, PIC16C62XA-04 only F OSC = 32 kHz, VDD = 4.0V, WDT disabled HS osc conﬁguration FOSC = 20 MHz, VDD = 5.5V, WDT disabled D020 IPD Pow er Down Current (Note 3) – 1.0 2.5 mA mA VDD =4.0V, WDT disabled (125°C) D023 DIWDT DIBOR DICOMP DIVREF WDT Current (Note 5) Brown-out Reset Current (Note 5) Compar ator Current for each Compar ator (Note 5) V REF Current (Note 5) 6.0 150 200 mA mA mA mA mA V DD =4.0V (125°C) BOR enabled, VDD = 5.0V VDD = 4.0V VDD = 4.0V * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be low ered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. The test conditions for all I DD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD , MCLR = VDD ; WDT enab led/disabled as speciﬁed. 3: The pow er down current in SLEEP mode does not depend on the oscillator type. Pow er down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS . 4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the form ula Ir = VDD /2Rext (mA) with Rext in kW . 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.

DS30235G -page 84 Preliminary Ó 1998 Microchip Technology Inc.

12.4 DC CHARA CTERISTICS: PIC16C62X/C62X A/CR62XA (Commer cial, Industrial, Extended)

PIC16LC62X/LC62 XA/LCR62XA (Commer cial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature –40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial and –40˚C £ TA £ +125˚C for extended Operating voltage VDD range as described in DC spec Table 12-1 and Table 12-2 Param. No. Sym Characteristic Min Typ† Max Unit Conditions VIL Input Low Voltage I/O ports D030 with TTL buffer VSS - 0.8V 0.15VDD V VDD = 4.5V to 5.5V otherwise D031 with Schmitt Trigger input VSS 0.2VDD V D032 MCLR , RA4/T0CKI,OSC1 (in RC mode) Vss - 0.2VDD V Note1 D033 OSC1 (in XT and HS) Vss - 0.3VDD V OSC1 (in LP) Vss - 0.6VDD -1.0 V VIH Input High Voltage I/O ports - D040 with TTL buffer 2.0V .25VDD + 0.8V - VDD VDD V VDD = 4.5V to 5.5V otherwise D041 with Schmitt Trigger input 0.8VDD VDD D042 MCLR RA4/T0CKI 0.8VDD - VDD V D043 D043A OSC1 (XT, HS and LP) OSC1 (in RC mode) 0.7VDD 0.9VDD - VDD V Note1 D070 IPURB POR TB weak pull-up current 50 200 400 mA VDD = 5.0V, VPIN = VSS IIL Input Leakage Current (Notes 2, 3) I/O ports (Except PORTA) –1.0 mA V SS £ VPIN £ VDD , pin at hi-impedance D060 POR TA - - –0.5 mA Vss £ VPIN £ VDD , pin at hi-impedance D061 RA4/T0CKI - - –1.0 mA Vss £ VPIN £ VDD D063 OSC1, MCLR - - –5.0 mA Vss £ VPIN £ VDD , XT, HS and LP osc conﬁguration VOL Output Low Voltage D080 I/O ports - - 0.6 V IOL =8.5 mA, VDD =4.5V, -40° to +85°C - - 0.6 V IOL =7.0 mA, VDD =4.5V, +125°C D083 OSC2/CLK OUT (RC only) - - 0.6 V IOL =1.6 mA, VDD =4.5V, -40° to +85°C - - 0.6 V IOL =1.2 mA, VDD =4.5V, +125°C VOH Output High Voltage (Note 3) D090 I/O ports (Except RA4) VDD -0.7 - - V IOH =-3.0 mA, VDD =4.5V, -40° to +85°C VDD -0.7 - - V IOH =-2.5 mA, VDD =4.5V, +125°C D092 OSC2/CLK OUT (RC only) VDD -0.7 - - V IOH =-1.3 mA, VDD =4.5V, -40° to +85°C VDD -0.7 - - V IOH =-1.0 mA, VDD =4.5V, +125°C VOD Open-Drain High Voltage 10* 10* V RA4 pin PIC16C62X, PIC16LC62X RA4 pin PIC16C62XA, PICLC62XA, CR62XA, LCR62XA Capacitive Loading Specs on Output Pins D100 C OSC2 OSC2 pin 15 pF In XT, HS and LP modes when external clock used to drive OSC1. D101 Cio All I/O pins/OSC2 (in RC mode) 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C62X(A) be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The speciﬁed levels represent normal operat- ing conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is deﬁned as coming out of the pin.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 85 PIC16C62X TABLE 12-2: COMPARATOR SPECIFICATIONS Operating Conditions: Vdd range as described in Table 12-1, -40°C<TA<+125 °C. Current consumption is speciﬁed in Table 12-1. TABLE 12-3: VOLTA G E REF ERENCE SPECIFICATIONS Operating Conditions:Vdd range as described in Table 12-1, -40°C<TA<+125 °C. Current consumption is speciﬁed in Table 12-1. Characteristics Sym Min Typ Max Units Comments Input offset voltage – 5.0 – 10 mV Input common mode voltage 0 VDD - 1.5 V CMRR +55* db Response Time(1) 150* 400* 600* ns ns PIC16C62X (A) PIC16LC62 X Compar ator Mode Change to Output Valid 10* ms * These parameters are characterized but not tested. Note 1:Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD . Characteristics Sym Min Typ Max Units Comments Resolution VDD /24 VDD /32 LSB Absolute Accuracy +1/4 +1/2 LSB LSB Low Range (VRR =1) High Range (VRR =0) Unit Resistor Value (R) 2K* W Figure 8-2 Settling Time(1) 10* ms * These parameters are characterized but not tested. Note 1:Settling time measured while VRR = 1 and VR <3:0> transitions from 0000 to 1111.

DS30235G -page 86 Preliminary Ó 1998 Microchip Technology Inc.

12.5 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats: FIGURE 12-1: LOAD CONDITIONS 1. TppS2ppS 2. TppS T F Frequency T Time Low ercase subscripts (pp) and their meanings: pp ck CLK OUT osc OSC1 io I/O port t0 T0CKI mc MCLR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-Impedance VDD /2 C L R L Pin Pin VSS VSS C L R L = 464W C L = 50 pF for all pins except OSC2 15 pF for OSC2 output Load condition 1 Load condition 2

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 87 PIC16C62X

12.6 Timing Diagrams and Speciﬁcations

FIGURE 12-2: EXTERNAL CLOC K TIMING TABLE 12-4: EXTERNAL CLOC K TIMING REQUIREMENTS Parameter No. Sym Characteristic Min Typ† Max Units Conditions Fos External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode, VDD =5.0V DC — 20 MHz HS osc mode DC — 200 kHz LP osc mode Oscillator Frequency (Note 1) DC — 4 MHz RC osc mode, VDD =5.0V 0.1 — 4 MHz XT osc mode 1 — 20 MHz HS osc mode DC – 200 kHz LP osc mode

1 Tosc External CLKIN Period

(Note 1) 250 — — ns XT and RC osc mode 50 — — ns HS osc mode 5 — — ms LP osc mode Oscillator Period (Note 1) 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 50 — 1,000 ns HS osc mode 5 — — ms LP osc mode 2 TCY Instruction Cycle Time (Note 1) 1.0 Fosc/4 DC ms TCYS =FOSC /4 3* TosL, TosH External Clock in (OSC1) High or Low Time 100* — — ns XT oscillator, TOSC L/H duty cycle 2* — — ms LP oscillator, TOSC L/H duty cycle 20* — — ns HS oscillator, TOSC L/H duty cycle 4* TosR, TosF External Clock in (OSC1) Rise or Fall Time 25* — — ns XT oscillator 50* — — ns LP oscillator 15* — — ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1:Instruction cycle period (TCY ) equals four times the input oscillator time-base period. All speciﬁed values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC1 CLK OUT Q4 Q1 Q2 Q3 Q4 Q1 1 3 3 4 4

DS30235G -page 88 Preliminary Ó 1998 Microchip Technology Inc. FIGURE 12-3: CLK OUT AND I/O TIMING Note: All tests must be do with speciﬁed capacitance loads (Figure 12-1) 50 pF on I/O pins and CLKOUT OSC1 CLK OUT I/O Pin (input) I/O Pin (output) Q4 Q1 Q2 Q3 20, 21 19 18 old value new value

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 89 PIC16C62X TABLE 12-5: CLK OUT AND I/O TIMING REQUIREMENTS Parameter #Sym Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 › to CLKOUT ﬂ (1) — 200 400 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 11* TosH2ckH OSC1 › to CLKOUT › (1) — 200 400 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 12* TckR CLK OUT rise time (1) — 100 200 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 13* TckF CLK OUT fall time (1) — 100 200 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 14* TckL2ioV CLK OUT ﬂ to Port out valid (1) — — 20 ns 15* TioV2ckH Port in valid before CLKOUT › (1) Tosc +200 ns Tosc +400 ns ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 16* TckH2ioI Port in hold after CLKOUT › (1) 0 — — ns 17* TosH2ioV OSC1 › (Q1 cycle) to Port out valid — 50 150 300 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 18* TosH2ioI OSC1 › (Q2 cycle) to Port input invalid (I/O in hold time) 100 200 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 19* TioV2osH Port input valid to OSC1› (I/O in setup time) 0 — — ns 20* TioR Port output rise time — ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 21* TioF Port output fall time — ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA 22* Tinp RB0/INT pin high or low time 25 ns ns PIC16C62X (A) PIC16LC62X (A) PIC16CR62XA PIC16LCR62XA

23 Trbp RB<7:4> change interrupt high or low time TCY — — ns

These parameters are characterized but not tested † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1:Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC

DS30235G -page 90 Preliminary Ó 1998 Microchip Technology Inc. FIGURE 12-4: RESET, W ATC HDOG TIMER , OSCILLATOR STAR T-UP TIMER AND P O WER -UP TIMER TIMING FIGURE 12-5: BR O WN-OUT RESET TIMING TABLE 12-6: RESET, W ATC HDOG TIMER , OSCILLATOR STAR T-UP TIMER AND P O WER -UP TIMER REQUIREMENTS Parameter No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2000 — — ns -40° to +85°C

31 Twdt W atchdog Timer Time-out Period

(No Prescaler) 7* 18 33* ms VDD = 5.0V, -40° to +85°C

32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period

33 Tpwrt Pow er-up Timer Period 28* 72 132* ms VDD = 5.0V, -40° to +85°C 34 TIOZ I/O hi-impedance from MCLR low — 2.0 ms 35 TBOR Brown-out Reset Pulse Width 100* — — ms 3.7V £ VDD £ 4.3V * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. VDD MCLR Internal POR PWR T Timeout OSC Timeout Internal RESET W atchdog Timer RESET I/O Pins VDD BV DD

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 91 PIC16C62X FIGURE 12-6: TIMER0 CLOC K TIMING TABLE 12-7: TIMER0 CLOC K REQUIREMENTS FIGURE 12-7: LOAD CONDITIONS Parameter No. Sym Characteristic Min Typ† Max Units Conditions 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns

42 Tt0P T0CKI Period TCY + 40*

N — — ns N = prescale value * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. RA4/T0CKI TMR0 VDD /2 C L R L Pin Pin VSS VSS C L R L = 464W C L = 50 pF for all pins except OSC2 15 pF for OSC2 output Load condition 1 Load condition 2

DS30235G -page 92 Preliminary Ó 1998 Microchip Technology Inc. NO TES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 93 PIC16C62X

13.0 DE VICE CHARACTERIZATION

Not Available at this time.

DS30235G -page 94 Preliminary Ó 1998 Microchip Technology Inc. NOTES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 95 PIC16C62X

14.0 PAC KA GING INFORMATION

Package Type: K04-010 18-Lead Ceramic Dual In-line with Windo w (JW) – 300 mil * Controlling Parameter. n R MIN Window Length Window Width Ov erall Row Spacing Radius to Radius Width Package Width Package Length Tip to Seating Plane Base to Seating Plane Top of Lead to Seating Plane Top to Seating Plane Lead Thickness Shoulder Radius Upper Lead Width Low er Lead Width Number of Pins PCB Ro w Spacing Dimension Limits Pitch Units eB L E D A B c R n p 0.15 7.24 7.87 0.76 3.33 4.83 0.30 0.38 1.52 0.53 2.59 0.200 0.140 0.385 0.270 0.298 0.900 0.138 0.023 0.111 0.183 0.190 0.130 0.345 0.125 0.255 0.285 0.880 0.015 0.091 0.175 0.210 0.150 0.425 0.150 0.285 0.310 0.920 0.030 0.131 0.190 0.010 0.013 0.055 0.019 0.100 0.300 NOM 0.016 0.008 0.010 0.050 0.098 INCHES* MAX 0.021 0.012 0.015 0.060 0.102 22.86 0.19 0.13 8.76 6.48 7.24 22.35 3.18 0.00 2.31 4.45 0.2 0.14 9.78 10.80 0.21 3.49 6.86 7.56 0.57 2.82 4.64 3.81 23.37 NOM MILLIMETERS MIN 0.20 0.25 1.27 0.41 2.49 MAX 0.47 0.25 0.32 1.40 2.54 7.62 DW2 E c eB p L B A

DS30235G -page 96 Preliminary Ó 1998 Microchip Technology Inc. Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Ro w Spacing 0.300 7.62 Number of Pins n 18 18 Pitch p 0.100 2.54 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom b 5 10 15 5 10 15 R n D E c eB b a p L B A

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 97 PIC16C62X Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide , 300 mil 0.014 0.009 0.010 0.011 0.005 0.005 0.010 0.394 0.292 0.450 0.004 0.048 0.093 MIN nNumber of Pins Mold Draft Angle Bottom Mold Draft Angle Top Low er Lead Width Chamfer Distance Outside Dimension Molded Package Width Molded Package Length Ov erall Pack. Height Lead Thickness Radius Centerline Foot Angle Foot Length Gull Wing Radius Shoulder Radius Standoff Shoulder Height b a X f B c L D ‡ A Dimension Limits Pitch Units p 1818 0.020 0.017 0.011 0.015 0.016 0.005 0.005 0.407 0.296 0.456 0.008 0.058 0.099 0.029 0.019 0.012 0.020 0.021 0.010 0.010 0.419 0.299 0.462 0.011 0.068 0.104 0.42 0.27 0.38 0.41 0.13 0.13 0.50 10.33 7.51 11.58 0.19 1.47 2.50 0.25 0.36 0.23 0.25 0.28 0.13 0.13 10.01 7.42 11.43 0.10 1.22 2.36 0.74 4 8 0.48 0.30 0.51 0.53 0.25 0.25 10.64 7.59 11.73 0.28 1.73 2.64 INCHES* 0.050 NOM MAX 1.27 MILLIMETERS MIN NOM MAX n L b c f X 45° D p B E a A * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

DS30235G -page 98 Preliminary Ó 1998 Microchip Technology Inc. Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm MIN pPitch Mold Draft Angle Bottom Mold Draft Angle Top Low er Lead Width Radius Centerline Gull Wing Radius Shoulder Radius Outside Dimension Molded Package Width Molded Package Length Shoulder Height Ov erall Pack. Height Lead Thickness Foot Angle Foot Length Standoff Number of Pins b a c f A n B L E D ‡ Dimension Limits Units 0.650.026 5 10 0.012 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.283 0.005 0.036 0.073 0.301 0.010 0.005 0.000 0.015 0.005 0.005 0.205 0.278 0.002 0.026 0.068 0.311 0.015 0.009 0.010 0.025 0.010 0.010 4 8 0.212 0.289 0.008 0.046 0.078 0 5 5 10 7.65 0.25 0.13 0.00 0.38 0.13 0.13 5.20 7.07 0.05 0.66 1.73 7.907.78 0.32 0.18 0.13 0.13 0.51 0.13 0.38 0.22 0.25 0.25 0.64 0.25 5.29 7.20 0.13 1.86 0.91 5.38 7.33 0.21 1.99 1.17 NOM INCHES MAX NOM MILLIMETERS* MIN MAX n 1 D p B E L c b f a A * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 99 PIC16C62X

14.1 Package Marking Information

18-Lead SOIC (.300") XXXXXXX XXXXX AABBCDE XXXXXXX XXXXX XXXXXXX XXXXX XXXXXXXXXX XXXXXXX XXXXXXXXX XXXXXXX X AABBCDE 18-Lead PDIP Example -04I / 218

9851 CBP

/JW

9801 CBA

-04I / S0218

9818 CDK

-04I / P456

9823 CBA

Legend: MM...M Microchip part number information XX...X Customer speciﬁc information* AA Year code (last 2 digits of calendar year) BB W eek code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5” Line S = 6” Line H = 8” Line D Mask revision number E Assemb ly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speciﬁc information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

DS30235G -page 100 Preliminary Ó 1998 Microchip Technology Inc. NO TES:

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 101 PIC16C62X APPENDIX A: ENHANCEMENTS The following are the list of enhancements over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memor y (4K now as opposed to 512 before) and register ﬁle (up to 128 bytes now versus 32 bytes before). 2. A PC high latch register (PCLATH) is added to handle program memor y paging. PA2, PA1, PA0 bits are removed from STATUS register. 3. Data memor y paging is slightly redeﬁned. STATUS register is modiﬁed. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Tw o instructions TRIS and OPTION are being phased out although the y are k ept for compatibility with PIC16C5X. 5. OPTION and TRIS registers are made addressable. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. 10. W ake up from SLEEP through interrupt is added. 11. Tw o separate timers, Oscillator Start-up Timer (OST) and P ow er-up Timer (PWR T) are included for more reliable pow er-up. These timers are invoked selectively to a void unnecessary delays on pow er-up and wake-up. 12. POR TB has w eak pull-ups and interrupt on change feature. 13. Timer0 clock input, T0CKI pin is also a port pin (RA4/T0CKI) and has a TRIS bit. 14. FSR is made a full 8-bit register. 15. “In-circuit programming” is made possible. The user can program PIC16CXX devices using only ﬁve pins: VDD , VSS , /VPP , RB6 (clock) and RB7 (data in/out). 16. PCON status register is added with a Pow er-on-Reset (POR ) status bit and a Brown-out Reset status bit (BOR ). 17. Code protection scheme is enhanced such that portions of the program memor y can be protected, while the remainder is unprotected. 18. POR TA inputs are now Schmitt Trigger inputs. 19. Brown-out Reset reset has been added. 20. Common RAM registers F0h-FFh implemented in bank1. APPENDIX B: COMPATIBILITY To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. Remo ve any program memor y page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. 2. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. 3. Eliminate any data memor y page switching. Redeﬁne data variables to reallocate them. 4. Verify all writes to STATUS , OPTION, and FSR registers since these have changed. 5. Change reset vector to 0000h.

DS30235G -page 102 Preliminary Ó 1998 Microchip Technology Inc. APPENDIX C: WHAT’ S NEW The format of certain sections of this data sheet have been changed to be consistent with other product families. 1. POR TB input buffers have changed to TTL from Schmitt Trigger. APPENDIX D: WHAT’ S CHANG ED 1. Table 3-1 was changed to reﬂect the TTL input buffers on PORTB . 2. Figure 5-5 and Figure 5-6 w ere updated to reﬂect the TTL input buffers on PORTB . 3. Figure 9-7 was updated. 4. The orientation of the diode in Figure 9-19 was changed. 5. A device speciﬁcation for JW devices was added to Table 12-1. 6. Max spec for Brown-out Reset current was changed to 15 mA in Section 12.1 and Section 12.2. 7. Information added to support the 2.5V "LC" devices. 8. Information added to support the "A" version of the devices.

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 103 PIC16C62X INDE X A Assembler B Block Diagram C D E F G I Instruction Set K M MPLAB Integrated Development Environment N O

DS30235G -page 104 Preliminary Ó 1998 Microchip Technology Inc. P Q R S Serialized Quick-Turnaround-Production T Timer0 Timer1 V W X

Ó 1998 Microchip Technology Inc. DS30235G -page 105 PIC16C62X Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. Trademarks: The Microchip name, logo, PIC, PICSTAR T, PICMASTER and PRO MA TE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexR OM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Micro- chip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. ON-LINE SUPPOR T Microchip provides on-line support on the Microchip W orld Wide W eb (WWW) site. The web site is used by Microchip as a means to make ﬁles and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet W eb Site The Microchip web site is available by using your favorite Internet browser to attach to: www .microchip.com The ﬁle transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip The web site and ﬁle transfer site provide a variety of services. Users ma y download ﬁles for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs . A vari- ety of Microchip speciﬁc business information is also available, including listings of Microchip sales ofﬁces, distributors and factory representatives. Other data available for consideration is:

Latest Microchip Press Releases
Technical Support Section with Frequently Asked Questions
Design Tips
Device Errata
Job Postings
Microchip Consultant Program Member Listing
Links to other useful web sites related to Microchip Products
Conferences for products, Development Systems, technical information and more
Listing of seminars and events 980106

DS30235G -page 106 Ó 1998 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. 1. What are the best features of this document? 2. Ho w does this document meet your hardware and software development needs? 3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. Ho w would you improve this document? 8. Ho w would you improve our software, systems, and silicon products? To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Compan y Address City / State / ZIP / Country Application (optional): W ould you like a reply? Y N Device: Literature Number: Questions: DS30235GPIC16C62X

Ó 1998 Microchip Technology Inc. Preliminary DS30235G -page 107 PIC16C62X PIC16C62X PRODUCT IDENTIFICATION SYSTEM To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales ofﬁces. * JW Devices are UV erasable and can be programmed to any device conﬁguration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended w orkarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales ofﬁce. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. Pattern: 3-Digit Pattern Code for QTP (blank otherwise) Package: P = PDIP SO = SOIC (Gull Wing, 300 mil body) SS = SSOP (209 mil) JW* = Window ed CERDIP Temperature - = 0˚C to +70˚C Rang e: I = –40˚C to +85˚C E = –40˚C to +125˚C Frequency 04 = 200kHz (LP osc) Rang e: 04 = 4 MHz (XT and RC osc) 20 = 20 MHz (HS osc) De vice: PIC16C62X :VDD range 3.0V to 6.0V PIC16C62XT :VDD range 3.0V to 6.0V (Tape and Reel) PIC16C62XA: VDD range 3.0V to 5.5V PIC16C62XA T: VDD range 3.0V to 5.5V (Tape and Reel) PIC16LC62X :VDD range 2.5V to 6.0V PIC16LC62XT :VDD range 2.5V to 6.0V (Tape and Reel) PIC16LC62XA :VDD range 2.5V to 5.5V PIC16LC62XA T:VDD range 2.5V to 5.5V (Tape and Reel) PIC16CR620A: VDD range 2.5V to 5.5V PIC16CR620A T: VDD range 2.5V to 5.5V (Tape and Reel) PIC16LCR620A: VDD range 2.0V to 5.5V PIC16LCR620A T: Vdd range 2.0V to 5.5V (Tape and Reel) PIC16CR620T : VDD range 3.0V to 5.5V (Tape and Reel) Examples: g) PIC16C621A - 04/P 301 = Commercial temp., PDIP pack- age, 4 MHz, normal VDD limits, QTP pattern #301. h) PIC16LC62 2- 04I/SO = Industrial temp., SOIC pack- age, 200kHz, extended VDD limits. PAR T NO. -XX X /XX XXX

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or trademarks mentioned herein are the property of their respective companies. DS30235G -page 108 ª 1998 Microchip Technology Inc. All rights reserved. © 1998, Microchip Technology Incorporated, USA. 8/98 Printed on recycled paper. M AMERICAS Corporate Ofﬁce Microchip Technology Inc. 2355 W est Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 W eb: http://www.microchip.com Atlanta Microchip Technology Inc.

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Product Information

16C62X specifications and overview.

Summary

EPROM-Based 8-Bit CMOS Microcontroller 1998

Description

EPROM-Based 8-Bit CMOS Microcontroller 1998

Source title 16C62X Datasheet(PDF) - Microchip Technology

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