16C505

PIC16C505 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 80

Technical content

Ó 1998 Microchip Technology Inc. Preliminary DS40192A-page 1 Device included in this Data Sheet: PIC16C505 High-Performance RISC CPU:

• Only 33 instructions to learn
• Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle
• Direct, indirect and relative addressing modes for data and instructions
• 12 bit wide instructions
• 8 bit wide data path
• 2-level deep hardware stack
• Eight special function hardware registers
• Direct, indirect and relative addressing modes for data and instructions
• All single cycle instructions (200 ns) except for program branches which are two-cycle Peripheral Features:
• 11 I/O pins with individual direction control
• 1 input pin
• High current sink/source for direct LED drive
• Timer0: 8-bit timer/counter with 8-bit programmable prescaler FIGURE 1: PIN DIAGRAM: Device Memory Program Data PIC16C505 1024 x 12 72 x 8 PDIP, SOIC, Ceramic Side Brazed PIC16C505VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/V PP RC5/T0CKI RC4 RC3 VSS RB0 RB1 RB2 RC0 RC1 RC2 Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™)
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation
• Programmable Code Protection
• Internal weak pull-ups on I/O pins
• Wake-up from Sleep on pin change
• Power-saving Sleep mode
• Selectable oscillator options: - INTRC: Precision internal 4 MHz oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - HS: High speed crystal/resonator - LP: Power saving, low frequency crystal CMOS Technology:
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range (2.5V to 5.5V)
• Wide temperature ranges - Commercial: 0˚C to +70˚C - Industrial: -40˚C to +85˚C - Extended: -40˚C to +125˚C - < 1.0 m A typical standby current @ 5V
• Low power consumption - < 2.0 mA @ 5V, 4 MHz - 15 m A typical @ 3.0V, 32 kHz for TMR0 run- ning in SLEEP mode - < 1.0 m A typical standby current @ 5V PIC16C505 14-Pin, 8-Bit CMOS Microcontroller

Ó 1998 Microchip Technology Inc. TABLE OF CONTENTS To Our Valued Customers W e constantly strive to improve the quality of all our products and documentation. W e have spent an exceptional amount of time to ensure that these documents are correct. How ever, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. W e appreciate your assistance in making this a better document.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 3 PIC16C505

1.0 G ENERAL DESCRIPTION

The PIC16C505 from Microchip Technology is a low- cost, high performance , 8-bit, fully static, EPROM/ R OM-based CMOS microcontroller. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 m except for program branches which take two cycles. The PIC16C505 delivers performance an order of mag- nitude higher than its competitors in the same price cat- egory. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instr uction set reduces development time significantly. The PIC16C505 product is equipped with special fea- tures that reduce system cost and pow er requirements. The Pow er-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are five oscillator configurations to choose from, including INTRC internal oscillator mode and the pow er-saving LP (Low Pow er) oscillator. Pow er saving SLEEP mode , W atchdog Timer and code protection features improve system cost, pow er and reliability. The PIC16C505 is available in the cost-effective One- Time-Programmab le (OTP) version, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers while benefiting from the OTP’s flexibility. The PIC16C505 product is supported by a full-featured macro assembler, a software simulator, an in-circuit em ulator, a ‘C’ compiler, a low-cost development pro- grammer , and a full featured programmer . All the tools are supported on IBM Ò PC and compatible machines.

1.1 Applications

The PIC16C505 fits perfectly in applications ranging from personal care appliances and security systems to low-pow er remote transmitters/receivers. The EPR OM technology makes customizing application programs (transmitter codes, appliance settings, receiver fre- quencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller perfect for applica- tions with space limitations. Low-cost, low-pow er, high performance , ease of use and I/O flexibility make the PIC16C505 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of “glue” logic and PLD’s in larger systems, coprocessor applications).

Ó 1998 Microchip Technology Inc. TAB LE 1-1: PIC16C505 DEVICE PIC16C505 Clock Maximum Frequency of Operation (MHz) Memory EPROM Program Memory 1024 Data Memory (bytes) 72 Peripherals Timer Module(s) TMR0 Wake-up from SLEEP on pin change Yes

Features

In-Circuit Serial Programming Yes Number of Instructions 33 Packages 14-pin DIP, SOIC, JW The PIC16C505 device has Pow er-on Reset, selectable W atchdog Timer, selectable code protect, high I/O current capability and precision internal oscillator. The PIC16C505 device uses serial programming with data pin RB0 and clock pin RB1.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 5 PIC16C505

2.0 PIC16C505 DE VICE VARIETIES

A v ariety of p ackaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C505 Product Identification System at the back of this data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV er asable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs . The UV er asable version can be er ased and reprogrammed to any of the configuration modes. Microchip's PICSTAR T â PLUS and PRO MA TE â pro- grammers all support programming of the PIC16C505 . Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources.

2.2 One-Time-Programmab le (OTP)

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once . In addition to the program memor y, the configuration bits must also be programmed. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.

2.3 Quick-Turnaround-Production (QTP)

Microchip offers a QTP Prog ramming Ser vice for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed b y the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please con- tact your local Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround

Production (SQTP SM ) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers ma y be r andom, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, passw ord or ID number.

Ó 1998 Microchip Technology Inc. NO TES:

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 7 PIC16C505

3.0 AR C HITECTURAL OVER VIEW

The high performance of the PIC16C505 can be attributed to a n umber of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C505 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide, making it possible to have all single word instructions. A 12-bit wide program memor y access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MH z) except for program branches. The PIC1 6C505 a ddresses 1K x 12 of prog ram memor y. All program memor y is internal. The PIC16C505 can directly or indirectly address its register files and data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C505 has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ mak e programming with the PIC16C505 simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16C505 device contains an 8-bit ALU and w orking register. The ALU is a gener al purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

Ó 1998 Microchip Technology Inc. FIGURE 3-1: PIC16C505 BLOC K DIAGRAM Device Reset Timer Pow er-on Reset W atchdog Timer EPR OM Program Memor y

12 Data Bus 8

Decode & Control Timing GenerationOSC1/CLKIN OSC2 MCLR Vdd, Vss Timer0 POR TB RB4/OSC2/CLK OUT RB3/MCLR/Vpp RB2 RB1 RB0 5-7 RB5/OSC1/CLKIN STACK1 STACK2 1K x 12 72 bytes Internal RC OSC POR TC RC4 RC3 RC2 RC1 RC0 RC5/T0CKI

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 9 PIC16C505 TAB LE 3-1: PIC16C505 PINOUT DESCRIPTION Name DIP Pin # SOIC Pin # I/O/P Type Buffer Type Description RB0 13 13 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and w ake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode . RB1 12 12 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and w ake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode . RB2 11 11 I/O TTL Bi-directional I/O port. RC0 10 10 I/O TTL Bi-directional I/O port. RC1 9 9 I/O TTL Bi-directional I/O port. RC2 8 8 I/O TTL Bi-directional I/O port. RC3 7 7 I/O TTL Bi-directional I/O port. RC4 6 6 I/O TTL Bi-directional I/O port. RC5/T0CKI 5 5 I/O ST Bi-directional I/O port. Can be configured as T0CKI. RB3/MCLR /V PP 4 4 I TTL Input port/master clear (reset) input/programming volt- age input. When configured as MCLR , this pin is an active low reset to the device. Voltage on MCLR /V PP m ust not exceed V DD during normal device operation. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. W eak pull- up only when configured as RB3. RB4/OSC2/CLK OUT 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con- nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, RB4 in other modes). Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. In EXTRC and INTRC modes, the pin output can be configured to CLK OUT , which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RB5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external clock source input (RB5 in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when RB5, ST input in external RC oscillator mode. V DD 1 1 P — Positive supply for logic and I/O pins V SS 14 14 P — Ground reference for logic and I/O pins Legend: I = input, O = output, I/O = input/output, P = pow er, — = not used, TTL = TTL input, ST = Schmitt Trigger input

Ó 1998 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memor y and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.

3.2 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. How ever, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memor y is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOC K/INSTRUCTION CYC LE EXAMPLE 3-1: INSTRUCTION PIPELINE FLO W Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PC PC PC+1 PC+2 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) Internal phase clock All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTB, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 11 PIC16C505

4.0 M EMOR Y OR GANIZATIO N

PIC16C5 05 memor y is organized into program mem- ory and data memory. For the PIC16C505, a paging scheme is used. Program memor y pages are accessed using one STATUS register bit. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memor y Organization

The PIC16 C5 05 devices ha ve a 12-bit Program Counter (PC). The 1K x 12 (0000h-03FFh) for the PIC16C50 5 are physically implemented. Refer to Figure 4-1. Accessing a location above this boundary will cause a wrap-around within the first 1K x 12 space. The effective reset vector is at 0000h, (see Figure 4-1). Location 03FFh (PIC16C50 5) contains the internal clock oscillator calibration value. This value should never be overwritten. FIGURE 4-1: PR OGRAM MEMOR Y MAP AND STAC K FOR THE PIC16C505 CALL, RETLW PC<11:0> Stack Level 1 Stack Level 2 User Memory Space 0000h 7FFh 01FFh 0200h Reset Vector (note 1) Note 1:Address 0000h becomes the effective reset vector. Location 03FFh (PIC16C50 5) contains the MOVLW XX INTERNAL R C oscillator calibration value.

1024 W ord 03FFh

Ó 1998 Microchip Technology Inc.

4.2 Data Memor y Organization

Data memor y is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the PIC16C50 5, the register file is composed of 8 special function registers, 24 g eneral purpose registers, and 48 general purpose registers that may be addressed using a banking scheme (Figure 4-2).

4.2.1 GENER AL PUR POSE REGISTER FILE

The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8). FIGURE 4-2: PIC16C505 REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 1Fh INDF (1) TMR0 PCL STATUS FSR OSCCAL POR TB 0Fh 10h Bank 0 Bank 1 3Fh 30h 20h 2Fh General Purpose Registers General Purpose Registers General Purpose Registers Addresses map back to addresses in Bank 0. Note 1: Not a physical register. FSR<6:5> 00 01 Bank 3 7Fh 70h 60h 6Fh General Purpose Registers Bank 2 5Fh 50h 40h 4Fh General Purpose Registers 08h POR TC

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 13 PIC16C505

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The special registers can be classified into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TAB LE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMAR Y Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On R eset Value on M CLR and W DT Reset Value on W ake-up on Pin Chang e 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxxuuuu uuuuuuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxxuuuu uuuuuuuu uuuu 02h (1) PCL Low order 8 bits of PC 1111 11111111 11111111 1111 03h STATUS RBWUF — PAO TO PD Z DC C 0001 1xxx000q quuu100q quuu 04h FSR Indirect data memory address pointer 110x xxxx11uu uuuu11uu uuuu 05h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00--uuuu uu--uuuu uu-- N/A TRISB — — I/O control registers --11 1111--11 1111--11 1111 N/A TRISC — — I/O control registers --11 1111--11 1111--11 1111 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 11111111 11111111 1111 06h POR TB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu--uu uuuu 07h POR TC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx--uu uuuu--uu uuuu Legend: Shaded cellls not used by Port Registers, read as ‘0’, = unimplemented, read as ‘0’, x = unknown, u = unchanged.

Ó 1998 Microchip Technology Inc.

4.3 STATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF , BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary. FIGURE 4-3: STATUS REGISTER (AD DRESS:03 h) R/W -0 R/W -0 R/W -0 R-1 R-1 R/W -x R/W -x R/W -x RB WUF — PA0 TO PD Z DC C R = Readable bit W = Wr itable bit - n = Value at POR reset bit7 6 5 4 3 2 1 bit0 bit 7: RB WUF : IO reset bit 1 = Reset due to w ake-up from SLEEP o n pin change 0 = After pow er up or other reset bit 6: Unimplemented bit 5: PA0 : Program page preselect bits 1 = Page 1 (200h - 3FFh) 0 = Page 0 (000h - 1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: TO : Time-out bit 1 = After pow er-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD : Pow er-down bit 1 = After pow er-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC : Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADD WF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C : Carry/borro w bit (for ADDWF, SUBWF and RRF, RLF instructions) ADD WF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 15 PIC16C505

4.4 O PTION Register

The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits. Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of RBPU and RBWU . FIGURE 4-4: OPTION REGISTER W -1 W -1 W -1 W -1 W -1 W -1 W -1 W -1 RB WU RB PU T0CS T0SE PSA PS2 PS1 PS0 W = Wr itable bit U = Unimplemented bit - n= Value at POR reset Reference Table 4-1 for other resets. bit7 6 5 4 3 2 1 bit0 bit 7: RBWU : Enable w ake-up on pin change (RB 0, RB 1, RB 3, RB4) 1 = Disabled 0 = Enabled bit 6: RBPU : Enable weak pull-ups (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5: T0CS : Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4 bit 4: T0SE : Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin bit 3: PSA : Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS2:PS0 : Prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 Bit Value Timer0 Rate WDT Rate

DS40192A -page 16 Preliminary Ó 1998 Microchip Technology Inc.

4.5 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for fine calibration. FIGURE 4-5: OSCCAL REGI STER (AD DRESS 05 h)PIC16C505 R/W -1 R/W -0 R/W -0 R/W -0 R/W -0 R/W -0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — R = Readable bit W = Wr itable bit U = Unimplemented bit, read as ‘0’ - n= Value at POR reset bit7 bit0 bit 7-4:CAL<5:0>: Fine calibration

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 17 PIC16C505

4.6 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4- 6). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. Ho w ever, PC<8> does not come from the instruction word, but is always cleared (Figure 4-6). Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5. FIGURE 4-6: LOADING OF PC BRANC H INSTRUCTIONS - PIC16C505 Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memor y page (512 words long). PA0 STATUS PC 8 7 0 PCL 910 Instruction W ord 7 0 GOTO Instruction CALL or Modify PCL Instruction PA0 STATUS PC 8 7 0 PCL 910 Instruction W ord 7 0 Reset to ‘0’

4.6.1 EFF ECTS OF RESET

The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing M O VLW XX, the PC w ill roll over to location 00h, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET , which means that page 0 is pre- selected. Therefore, upon a RESET , a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.

4.7 Stack

PIC16C5 05 devices have a 1 2-bit wide hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL’s are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memor y.

DS40192A -page 18 Preliminary Ó 1998 Microchip Technology Inc.

4.8 Indirect Data Addressing; INDF and

The INDF register is not a ph ysical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. EXAMPLE 4-1: INDIRECT AD DRESSING

• Register file 07 contains the value 10h
• Register file 08 contains the value 0Ah
• Load the value 07 into the FSR register
• A read of the INDF register will return the value of 10h
• Increment the value of the FSR register by one (FSR = 08)
• A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Wr iting to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2. EXAMPLE 4-2: HO W TO CLEAR RAM USING INDIRECT AD DRESSING movlw0x10;initialize pointer movwfFSR ; to RAM NEXT clrfINDF;clear INDF register incfFSR,F;inc pointer btfscFSR,4;all done? gotoNEXT;NO, clear next CONTINUE : ;YES, continue The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. The device uses FSR6:5 to select between banks 0:3. FIGURE 4-7: DIRECT/INDIRECT AD DRESSING Note 1:For register map detail see Section 4.2. Direct Addressing (FSR) 6 5 4 (opcode) 0 bank select location select 00 01 10 11 00h 0Fh 10h Data Memor y(1) 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Addressesmap back toaddresses in Bank 0. Indirect Addressing 6 5 4 (FSR) 0 bank location select

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 19 PIC16C505

5.0 I/O POR T

As with any other register, the I/O register can be written and read under program control. Ho w ever, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s input/output modes . On RESET , all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set.

5.1 POR TB

POR TB is an 8-bit I/O register. Only the low order 6 bits are used (RB 5:RB 0). Bits 7 and 6 are unimplemented and read as '0's. Please note that RB 3 is an input only pin. The configuration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ during port read. Pins RB0, RB1, RB3 and RB4 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR , w eak pull-up is always off and wake-up on change for this pin is not enabled.

5.2 POR TC

POR TC is an 8-bit I/O register. Only the low order 6 bits are used (RC5:RC0). Bits 7 and 6 are unimple- mented and read as ‘0’s.

5.3 TRIS Registers

The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are RB 3 which is input only and RC5 which ma y be controlled by the option register, see Figure 4- The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except RB 3 which is input only, m ay be used f or both input and output operations. For input operations these ports are non- latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS m ust be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB 3) can be programmed individually as input or output. FIGURE 5-1: EQUIV ALENT CIR CUIT FOR A SINGLE I/O PIN Note 1: I/O pins have protection diodes to VDD and VSS . Data Bus QD QCK QD QCK P N WR Port TRIS ‘f’ Data TRIS RD Port VSS VDD I/O pin(1) W Reg Latch Latch Reset

DS40192A -page 20 Preliminary Ó 1998 Microchip Technology Inc. TAB LE 5-1: SUMMAR Y OF POR T REGISTER S Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on MCLR and WDT Reset Value on W ake-up on Pin Change N/A TRISB — — I/O control registers --11 1111--11 1111--11 1111 N/A TRISC — — I/O control registers --11 1111--11 1111--11 1111 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 11111111 11111111 1111 03h STATUS RBWUF — PAO TO PD Z DC C 0001 1xxx000q quuu100q quuu 06h POR TB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu--uu uuuu 07h POR TC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx--uu uuuu--uu uuuu Legend: Shaded cellls not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged.

5.5 I/O Programming Considerations

5.5.1 BI-DIRECTIONAL I/O POR TS

Some instructions operate internally as read follow ed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of POR TB will cause all eight bits of POR TB to be read into the CPU, bit5 to be set and the POR TB value to be written to the output latches. If another bit of POR TB is used as a bi- directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode , no problem occurs. How ever, if bit0 is switched into output mode later on, the content of the data latch ma y now be unknown. Example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., BCF, BSF, etc.) on an I/ O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired- and”). The resulting high output currents may damage the chip. EXAMPLE 5-1: READ- MODIFY-WRITE INSTRUCTIONS ON AN I/O POR T ;Initial PORTB Settings ; PORTB<5:3> Inputs ; PORTB<2:0> Outputs ; PORTB latch PORTB pins BCF PORTB, 5 ;--01 -ppp --11 pppp BCF PORTB, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS PORTB ;--10 -ppp --11 pppp ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;RB5 to be latched as the pin value (High).

5.5.2 SUCCESSIV E OPER ATIONS ON I/O

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data m ust be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write follow ed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 21 PIC16C505 FIGURE 5-2: SUCCESSIVE I/O OPERATION PC PC + 1 PC + 2 PC + 3 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction fetched RB5:RB0 MO VWF POR TB NOP Port pin sampled here NOPMO VF POR TB ,W Instruction executed MO VWF POR TB (Write to POR TB) NOPMO VF POR TB ,W This example shows a wr ite to PORTB follow ed by a read from PORTB . Data setup time = (0.25 TCY – TPD ) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write follow ed by a read may be problematic. (Read POR TB) Port pin written here

DS40192A -page 22 Preliminary Ó 1998 Microchip Technology Inc. NO TES:

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 23 PIC16C505

6.0 TIMER0 MODULE AND

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0 - Readab le and writable
• 8-bit software programmab le prescaler
• Internal or external clock select - Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0C S b it (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The prescaler ma y be used by either the Timer0 module or the W atchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. W hen the prescaler is assigned to the Timer0 module, prescale values of 1:2, operation of the prescaler. A summar y of registers associated with the Timer0 module is found in Table 6-1. FIGURE 6-1: TIMER0 BLOC K DIAGRAM Note 1: Bits T0CS , T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the W atchdog Timer (Figure 6-5). T0CS (1) FOSC /4 Programmab le Prescaler(2) Sync with Internal Clocks TMR0 reg PSout (2 cycle delay) PSout Data bus PSA (1)PS2, PS1, PS0(1) SyncT0SE RC5 /T0CKI Pin

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 25 PIC16C505

6.1 Using Timer0 with an External Clock

When an e xternal clock input is used for Timer0, it m ust meet certain requirements. The external clock requirement is due to internal phase clock (TOSC ) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1 EXTER NAL CLOC K SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase cloc ks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). R efer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the e xternal clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELA Y

Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOC K Increment Timer0 (Q4) External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Timer0 T0 T0 + 1 T0 + 2 Small pulse misses sampling External Clock/Prescaler Output After Sampling (3) Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = – 4Tosc max. External clock if no prescaler selected, Prescaler output otherwise. The arrows indicate the points in time where sampling occurs. Prescaler Output (2) (1)

DS40192A -page 26 Preliminary Ó 1998 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the W atchdog Timer (WDT), respectively (Section 7.6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler ma y be used by either the Timer0 module or the WDT , but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT , and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT , a CLRWDT instruction will clear the prescaler along with the WDT . The prescaler is neither readable nor writable. On a RESET , the prescaler contains all '0's.

6.2.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT . EXAMPLE 6-1: CHANGING PRESCALER (TIMER0 fi WDT) 1.CLRWDT ;Clear WDT 2.CLRF TMR0 ;Clear TMR0 & Prescaler 3.MOVLW'00xx1111’b;;These 3 lines (5, 6, 7) 4.OPTION ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 6.MOVLW'00xx1xxx’b;Set Postscaler to 7.OPTION ; desired WDT rate To change prescaler from the WDT to the Timer0 m odule, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. EXAMPLE 6-2: CHANGING PRESCALER (WDT fi TIMER0 ) CLRWDT ;Clear WDT and ;prescaler MOVLW'xxxx0xxx';Select TMR0, new ;prescale value and ;clock source OPTION FIGURE 6-5: BLOC K DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Sync Cycles TMR0 reg 8-bit Prescaler 8 - to - 1MUX M M UX W atchdog Timer PSA 0 1 WDT Time-Ou t PS2:PS0 Note: T0CS , T0SE, PSA, PS2:PS0 are bits in the OPTION register. PSA WDT Enab le bit Data Bus PSA T0CS M U X M U X U X T0SE RC5 /T0CKI Pin

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 27 PIC16C505

7.0 SPECIAL FEATURES OF THE

What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16C505 family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide pow er saving operating modes and offer code protection. These features are:

• Oscillator selection
• Reset - Pow er-On Reset (POR) - Device Reset Timer (DRT) - W ake-up from SLEEP on pin change
• W atchdog Timer (WDT)
• SLEE P
• C ode protection
• ID locations
• In-circuit Serial Programming
• Clock Out The PIC16C505 has a W atchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS , XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on V DD pow er-up. With this timer on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current pow er-down mode . The user can wake-up from SLEEP through a change on input pins or through a W atchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz oscillator. The EXTR C oscillator option saves system cost while the LP cr ystal option saves po w er. A set of configuration bits are used to select various options.

7.1 Confi guration Bits

The PIC16C5 05 configuration word consists of 6 bits. C onfiguration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type, one bit is the W atchdog Timer enable bit, and one bit is the MCLR enable bit. O ne bit is the code protection bit (Figure 7-1). FIGURE 7-1: CONFIGURATION W OR D FOR PIC16C505 CP CP CP CP CP CP MCLRE CP WDTE FOSC2 FOS C1 FOS C0 Reg ister: CONFIG Address(2): 0FFFhbit11 10 9 8 7 6 5 4 3 2 1 bit0 bit 11-6, 4: CP Code Protection bits (1)(2) bit 5: MCLRE: RB3/MCLR pin function select 1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3: WDTE : W atchdog timer enable bit 1 = WDT enab led 0 = WDT disabled bit 2-0:FOSC1:FOSC0: Oscillator Selection bits 111 = external RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 110 = external RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 101 = internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 100 = internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Note 1: 03FFh is always uncodeprtotected on the PIC16C505. This location contains the MO VLWxx calibration instruction for the INTRC. Note 2: Refer to the PIC16C505 Programming Specifications to determine how to access the con- figuration word. This register is not user addressable during device operation.

DS40192A -page 28 Preliminary Ó 1998 Microchip Technology Inc.

7.2 Oscillator Configurations

7.2.1 OSCILLATOR TYPES

The PIC16C505 can be operated in four different oscillator modes. The user can prog ram t hree configuration bits (FOSC2:FOSC0) to select one of these four modes:

• LP: Low Pow er Crystal
• XT : Crystal/Resonator
• HS: High Speed Crystal/Resonator
• INTRC: Internal 4 MHz Oscillator
• EXTR C: External Resistor/Capacitor

7.2.2 CR YSTAL OSCILLATOR / CER AMIC

In HS , XT or LP modes, a crystal or ceramic resonator is connected to the RB 5/OSC1/CLKIN and RB 4/ OSC2 /CLKOUT pins to establish oscillation (Figure 7- 2). The PIC16C505 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS , XT or LP modes , the device can have an external clock source drive the RB 5/OSC1/CLKIN pin (Figure 7-3). FIGURE 7-2: CR YSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) FIGURE 7-3: EXTERNAL CLOC K INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) ma y be required for AT strip cut crystals. 3: RF varies with the crystal chosen (approx. value = 10 MW ). C1 (1) C2 (1) XTAL OSC2 OSC1 RF (3) SLEEP To internallogic RS (2) PIC16C505 Clock from ext. system OSC1 OSC2 PIC16C 505 Open TAB LE 7-1: C APACITOR SELECTION FOR CERAMIC RESONATOR S - PIC16C5 05 TAB LE 7-2: C APACITOR SELECTION FOR CR YSTAL OSCILLATOR - PIC16C5 05 Osc Type Resonator Freq Cap. Range Cap. Range XT 4.0 MHz 30 pF 30 pF HS 16 MHz 10-47 pF 10-47 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. Osc Type Resonator Freq Cap.Rang e Cap. Range LP 32 kHz(1) 15 pF 15 pF XT 200 kHz

1 MHz

4 MHz

HS 20 MHz 15-47 pF 15-47 pF Note 1: For V DD > 4.5V, C1 = C2 » 30 pF is recommended. These values are for design guidance only. Rs may be required in XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 29 PIC16C505

7.2.3 EXTER NAL CR YSTAL OSCILLATOR

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepac kaged oscillators provide a wide operating range and better stability. A w ell-designed crystal oscillator will provide good performance with TTL gates. Tw o types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 7-4 sho ws implementation of a par allel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kW resistor provides the negative feedback for stability. The 10 kW potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. FIGURE 7-4: EXTERNAL P ARALLEL RESONANT CR YSTAL OSCILLATOR CIR CUIT Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180- degree phase shift in a series resonant oscillator circuit. The 330 W resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 7-5: EXTERNAL SERIES RESONANT CR YSTAL OSCILLATOR CIR CUIT 20 pF +5V 20 pF 10k 4.7k 10k 74AS04 XTAL 10k 74AS04 PIC16C505 CLKIN To Other Devices 330 74AS04 74AS04 PIC16C505 CLKIN To Other Devices XTAL 330 74AS04 0.1 mF

7.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter v ariation. Fur thermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-6 sho ws ho w the R/C combination is connected to the PIC16C505 . For Rext values below 2.2 kW , the oscillator operation may become unstable, or stop completely. F or very high Re xt values (e.g., 1 M W ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kW and 100 kW . Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. FIGURE 7-6: EXTERNAL RC OSCILLATOR MODE VDD Rext Cext VSS OSC1 Internal clock PIC16C505 N FOSC/4 OSC2/CLK OUT

DS40192A -page 30 Preliminary Ó 1998 Microchip Technology Inc.

7.2.5 INTER NAL 4 MH z RC OSCILLATOR

The internal RC oscillator provides a fixed 4 MHz (nom- inal) system clock at VDD = 5V and 25°C, see “Electri- cal Specifications” section for information on variation over voltage and temperature.. In addition, a calibration instruction is programmed into the last address of memory which contains the calibra- tion value for the internal RC oscillator. This location is always uncode protected regardless of the code pro- tect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. . For the PIC16C505, only bits <7:2> of OSCCAL are implemented.

7.3 RESET

The device differentiates between various kinds of reset: a) Pow er on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) W ake-up from SLEEP on pin change Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. Most other registers are reset to “reset state” on pow er- on reset (POR), on MCLR , WDT or wake-up on pin change reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP, since these resets are view ed as resumption of normal operation. The exceptions to this are TO , PD , and RBWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of reset. See Table 7-3 for a full description of reset states of all registers. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part. so it can be repro- grammed correctly later.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 31 PIC16C505 TABLE 7-3: R ESET CONDITIONS F OR REGISTER S TABLE 7-4: R ESET CONDITION F OR SPECIAL REGISTER S Register Ad dress Power-on Reset MCLR Reset WDT time-out W ake-up on Pin Change W — qqqq xxxx (1)qqqq uuuu (1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx ?00? ?uuu (2) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1000 00-- uuuu uu-- POR TB 06h --xx xxxxx --uu uuuu POR TC 07h --xx xxxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111 Legend:u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, ? = value depends on condition. Note 1: Bits <7:4> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. Note 2: See Table 7-7 for reset value for specific conditions STATUS Ad dr: 03h PCL Ad dr: 02h Pow er on reset 0001 1xxx 1111 1111 MCLR reset during normal operation 000u uuuu 1111 1111 MCLR reset during SLEEP 0001 0uuuu 1111 1111 WDT reset during SLEEP 0000 0uuu 1111 1111 WDT reset normal operation 0000 1uuu 1111 1111 W ake-up from SLEEP on pin change 1001 0uuu 1111 1111 Legend:u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.

DS40192A -page 32 Preliminary Ó 1998 Microchip Technology Inc.

7.3.1 MCLR ENABLE

This configuration bit when unprogrammed (left in the ‘1’ state) enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD , and the pin is assigned to be a I/O. See Figure 7- FIGURE 7-7: MCLR SELECT

7.4 Power-On Reset (POR)

The PIC16C505 family incorporates on-chip Pow er-On Reset (POR) circuitry which provides an internal chip reset for most pow er-up situations. A Pow er-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 2.3V - 2.8V). To take advantage of the internal POR, program the RB3/ MCLR /VPP pin as MCLR and tie directly to VDD or pro- gram the pin as RB3. An internal weak pull-up resistor is implemented using a transistor. Refer to Table 10-6 for the pull-up resistor ranges. This will eliminate exter- nal RC components usually needed to create a Pow er- on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device m ust be held in reset until the operating parameters are met. A simplified block diagram of the on-chip Pow er-On Reset circuit is shown in Figure 7-8. RB3/MCLR /VPP MCLRE INTERNAL MCLR WEAK PULL-UP RBWU The Pow er-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On pow er-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- chip reset signal. A po w er-up example where MCLR is held low is shown in Figure 7-9. VDD is allow ed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 7-10, the on-chip Pow er-On Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be RB3. ). The VDD is stable before the start-up timer times out and there is no problem in getting a proper reset. How ever, Figure 7- 11 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when M CLR (and VDD ) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, w e recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-10). For additional information refer to Application Notes “Pow er-Up Considerations” - AN522 and “Pow er-up Trouble Shooting” - AN607. Note: When the device starts normal operation (exits the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

DS40192A -page 34 Preliminary Ó 1998 Microchip Technology Inc. FIGURE 7-11: TIME-OUT SEQUENCE ON P O WER -UP (MCLR TIED TO VDD ): SLOW VDD RISE TIME VDD MCLR INTERNAL POR DR T TIME-OUT INTERNAL RESET TDR T When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ‡ VDD min.

7.5 De vice Reset Timer (DRT)

In the PIC16C505, the DRT runs any time the device is pow ered up. DRT runs from RESET and varies based on oscillator selection (see Table 7-5.) The Device Reset Timer (DRT) provides a fixed 18 ms nominal time-out on reset. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DR T delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after pow er-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high (VIHMCLR ) level. Thus, programming RB3/ MCLR /VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the RB3/ MCLR /VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip due to VDD , temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a W atchdog Timer time-out (only in HS, XT and LP modes). This is particularly important for applications using the WDT to wake from SLEEP mode automatically.

7.6 W atchdog Timer (WDT)

The W atchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external RC oscillator of the RB5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or w ake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a W atchdog Timer reset. The WDT can be per manently disabled b y programming the configuration bit WDTE as a '0' (Section 7.1). Refer to the PIC16C5 05 Programming Specifications to determine ho w to access the configuration word. TABLE 7-5: DR T (DEVICE RESET TIMER PERIOD) Oscillator Confi guration POR Reset Subsequent Resets IntRC & ExtRC 18 ms (typical)300 ms (typi- cal) HS , XT & LP 18 ms (typical)18 ms (typical)

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 35 PIC16C505

7.6.1 WDT P ER IOD

The WDT has a nominal time-out period of 18 ms , (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to- part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.

7.6.2 W DT PROG R AMMING CONSIDER ATIONS

The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT , and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT . This gives the maxim um SLEEP time before a WDT w ake-up reset. FIGURE 7-12: W ATC HDOG TIMER BLOC K DIAGRAM TAB LE 7-6: SUMMAR Y OF REGISTER S ASSOCIATED WITH THE W ATC HDOG TIMER Ad dress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On R eset Value on M CLR and W DT Reset Value on W ake-up on Pin Chang e N/A OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 11111111 11111111 1111 Legend: Shaded boxes = Not used by W atchdog Timer, — = unimplemented, read as '0', u = unchanged From Timer0 Clock Source (Figure 6-5) To Timer0 (Figure 6-4) Postscaler WDT Enab le Configuration Bit PSA WDT Time-out PS2:PS0 PSAMUX 8 - to - 1 MUX PostscalerM U X W atchdog Timer Note: T0CS , T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40192A -page 36 Preliminary Ó 1998 Microchip Technology Inc.

7.7 Time-Out Sequence, Power Down ,

and W ake-up from SLEEP S tatus Bits (TO /PD /RB WU F) The TO , PD, and RBWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a pow er-up condition, a MCLR or W atchdog Timer (WDT) reset, or a MCLR or WDT reset. These STATUS bits are only affected by events listed in Table 7-8. Table 7-4 lists the reset conditions for the special function registers, while Table 7-3 lists the reset conditions for all the registers. TAB LE 7-7: TO /PD /RBWUF STATUS AFTER RESE T RB WUF TO PD RESET caused by 0 0 0 WDT w ake-up from SLEEP 0 0 1 WDT time-out (not from SLEEP) 0 1 0 MCLR wake-up from SLEEP 0 1 1 Pow er-up 0 u u MCLR not during SLEEP 1 1 0 W ake-up from SLEEP on pin change Legend: Legend: u = unchanged Note 1: The TO , PD, and RB WUF b its main- tain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO , PD , and RB WUF s tatus bits. TAB LE 7-8: EVENTS AFF ECTING TO /PD STATUS BITS Event RB WUF TO PD Remarks Pow er-up 0 1 1 WDT Time-out 0 0 u No effect on PD SLEEP instruction u 1 0 CLR WD T instruction u 1 1 W ake-up from SLEEP on pin change 1 1 0 Legend: u = unchanged A WDT time-out will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit. Table 7-7 reflects the status of TO and PD after the corresponding event.

7.8 Reset on Brown-Out

A brown-out is a condition where device pow er (VDD ) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC16C5 05 de vices when a bro wn-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-13 and Figure 7-14. FIGURE 7-13: BR O WN-OUT PR OTECTION CIRCUIT 1 FIGURE 7-14: BR O WN-OUT PR OTECTION CIRCUIT 2 This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). *Refer to Figure 7-7 and Table 10-6 for internal weak pull- up on MCLR. 33k 10k 40k* VDD MCLR PIC16C5 05 VDD This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: *Refer to Figure 7-7 and Table 10-6 for internal weak pull-up on MCLR. VDD • R1 + R2 = 0.7V R2 40k VDD MCLR PIC16C 505 VDD

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 37 PIC16C505

7.9 Power-Down Mode (SLEEP)

A device may be pow ered down (SLEEP) and later pow ered up (Wake-up from SLEEP).

7.9.1 SLEEP

The P ow er-Down mode is entered by executing a SLEEP instruction. If enabled, the W atchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. For low est current consumption while pow ered down, the T0CKI input should be at VDD or VSS and the RB 3/ MCLR /VPP pin must be at a logic high level (VIHMC ) if MCLR is enabled.

7.9.2 W AK E-UP FROM SLEEP

The device can wake-up from SLEEP through one of the following events: 1. An external reset input on RB 3/MCLR /VPP pin, when configured as MCLR . 2. A W atchdog Timer time-out reset (if WDT w as enabled). 3. A change on input pin RB 0, RB 1, RB 3 or RB4 when wake-up on change is enabled. These events cause a device reset. The TO , PD, and RB WUF b its can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on pow er-up, is cleared when SLEEP is invoked. The RB WUF bit indicates a change in state while in SLEEP at pins RB 0, RB 1, RB 3 or RB4 (since the last file or bit operation on RB port). The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. Caution: Right before entering SLEEP, read the input pins. When in SLEEP , wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read bef ore reentering SLEEP, a wake up will occur immediately even if no pins change while in SLEEP mode.

7.10 Program Verification/Code Protection

If the code protection bit has not been programmed, the on-chip program memor y can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read regardless of the code protection bit setting.

7.11 ID Locations

Four memory locations are designated as ID locations where the user can store checksum or other code- identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the low er 4 bits of the ID locations and always program the upper 8 bits as '0's.

DS40192A -page 38 Preliminary Ó 1998 Microchip Technology Inc.

7.12 In-Circuit Serial Programming

The PIC1 6C5 05 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for pow er, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed de vices, and then program the microcontroller just before shipping the product. This also allows the most recent firmw are or a custom firmw are to be programmed. The device is placed into a program/verify mode by holding the RB 1 and RB 0 pins low while raising the MCLR (VPP ) pin from VIL to VIHH (see programming specification). RB 1 becomes the programming clock and RB 0 becomes the programming data. Both RB 1 and RB 0 are Schmitt Trigger inputs in this mode. After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of pro- gram data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C5 05 Programming Specifications. A typical in-circuit serial programming connection is shown in Figure 7-15. FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL PR OGRAMMING CONNECTION External Connector Signals To Normal Connections To Normal Connections PIC16C 505 VDD VSS MCLR /VPP RB 1 RB 0 +5V VPP CLK Data I/O VDD

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 39 PIC16C505

8.0 INSTRUCTION SET SUMMAR Y

Each PIC16C505 instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16C505 instruction set summary in Table 8-2 g roups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator is used to specify which one of the 32 file registers is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. TAB LE 8-1: OPCODE FIELD DESCRIPTIONS Field Description f Register file address (0x00 to 0x7F) W W orking register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0 (store result in W) d = 1 (store result in file register 'f') D efault is d = 1 labelLabel name TOSTop of Stack PC Program Counter WDTW atchdog Timer Counter TO Time-Out bit PD Pow er-Down bit destDestination, either the W register or the specified register file location [ ] Options ( ) Contents fi Assigned to < > Register bit field ˛ In the set of italics User defined term (font is courier) All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 ms. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ms. Figure 8-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit. FIGURE 8-1: G ENERAL FORMAT F OR INSTRUCTIONS Byte-oriented file register operations 11 6 5 4 0 d = 0 for destination W OPCODE d f (FILE #) d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 8 7 5 4 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 8 7 0 OPCODE k (literal) k = 8-bit immediate value Literal and control operations - GOTO instruction 11 9 8 0 OPCODE k (literal) k = 9-bit immediate value

DS40192A -page 40 Preliminary Ó 1998 Microchip Technology Inc. TAB LE 8-2: INSTRUCTION SET SUMMAR Y Mnemonic, Operands Description Cyc les 12-Bit Opcode Status Affected NotesMSb LSb ADD WF AND WF CLRF CLR W COMF DECF DECFSZ INCF INCFSZ IORWF MO VF MO VWF NOP RLF RRF SUBWF SW APF XOR WF f,d f,d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Mo ve f Mo ve W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Sw ap f Exclusive OR W with f 1(2) 1(2) 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z 1,2,4 2,4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 BIT-ORIENTED FILE REGISTER OPERA TIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff None None None None 2,4 2,4 LITERAL AND CONTR OL OPERA TIONS ANDL W CALL CLR WDT GO TO IORLW MO VLW OPTION RETL W SLEEP TRIS XORL W k k k k k k k f k AND literal with W Call subroutine Clear W atchdog Timer Unconditional branch Inclusive OR Literal with W Mo ve Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk Z None T O , PD None Z None None None T O , PD None Z Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO. (Section 4.6) 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of POR TB. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 41 PIC16C505 ADD WF Ad d W and f Syntax: [ label ] ADDWF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (W) + (f) fi (dest) Status Affected: C, DC, Z Encoding: 000111dfffff Description: Add the contents of the W register and register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example: ADDWFFSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 ANDL W And literal with W Syntax: [ label ] ANDLW k Operands: 0 £ k £ 255 Operation: (W).AND . (k) fi (W) Status Affected: Z Encoding: 1110kkkkkkkk Description: The contents of the W register are AND’ed with the eight-bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example: ANDLW0x5F Before Instruction W = 0xA3 After Instruction W = 0x03 AND WF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (W) .AND. (f) fi (dest) Status Affected: Z Encoding: 000101dfffff Description: The contents of the W register are AND’ed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example: ANDWFFSR,1 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0x17 FSR = 0x02 BCF Bit Clear f Syntax: [ label ] BCF f,b Operands: 0 £ f £ 31 0 £ b £ 7 Operation: 0 fi (f<b>) Status Affected: None Encoding: 0100bbbfffff Description: Bit 'b' in register 'f' is cleared. W ords: 1 Cycles: 1 Example: BCF FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47

DS40192A -page 42 Preliminary Ó 1998 Microchip Technology Inc. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0 £ f £ 31 0 £ b £ 7 Operation: 1 fi (f<b>) Status Affected: None Encoding: 0101bbbfffff Description: Bit 'b' in register 'f' is set. W ords: 1 Cycles: 1 Example: BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A BTFSC B it Test f, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 £ f £ 31 0 £ b £ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 0110bbbfffff Description: If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an NOP is executed instead, making this a 2 cycle instruction. W ords: 1 Cycles: 1(2) Example: HERE FALSE TRUE BTFSC GOTO FLAG,1 PROCESS_CODE Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE) BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 £ f £ 31 0 £ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding: 0111bbbfffff Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a 2 cycle instruction. W ords: 1 Cycles: 1(2) Example: HERE BTFSS FLAG,1 FALSE GOTO PROCESS_CODE TRUE • Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0, PC = address (FALSE); if FLAG<1> = 1, PC = address (TRUE)

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 43 PIC16C505 CALL Subroutine Call Syntax: [ label ] CALL k Operands: 0 £ k £ 255 Operation: (PC) + 1fi Top of Stack; k fi PC<7:0>; (STATUS<6:5>) fi PC<10:9>; 0 fi PC<8> Status Affected: None Encoding: 1001kkkkkkkk Description: Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC <10:9> are loaded from STA- TUS<6:5>, PC<8> is cleared. CALL is a two cycle instruction. W ords: 1 Cycles: 2 Example: HERECALL THERE Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 1) CLRF Clear f Syntax: [ label ] CLRF f Operands: 0 £ f £ 31 Operation: 00h fi (f); 1 fi Z Status Affected: Z Encoding: 0000011fffff Description: The contents of register 'f' are cleared and the Z bit is set. W ords: 1 Cycles: 1 Example: CLRFFLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 Z = 1 CLR W Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h fi (W); 1 fi Z Status Affected: Z Encoding: 000001000000 Description: The W register is cleared. Zero bit (Z) is set. W ords: 1 Cycles: 1 Example: CLRW Before Instruction W = 0x5A After Instruction W = 0x00 Z = 1 CLR WDT Clear W atchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h fi WDT ; 0 fi WDT prescaler (if assigned); 1 fi TO; 1 fi PD Status Affected: TO , PD Encoding: 000000000100 Description: The CLRWDT instruction resets the WDT . It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. W ords: 1 Cycles: 1 Example: CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescale= 0 TO = 1 PD = 1

DS40192A -page 44 Preliminary Ó 1998 Microchip Technology Inc. COMF Complement f Syntax: [ label ] COMF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) fi (dest) Status Affected: Z Encoding: 001001dfffff Description: The contents of register 'f' are comple- mented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example: COMFREG1,0 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W = 0xEC DECF Decrement f Syntax: [ label ] DECF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) – 1 fi (dest) Status Affected: Z Encoding: 000011dfffff Description: Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example: DECF CNT,1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) – 1 fi d; skip if result = 0 Status Affected: None Encoding: 001011dfffff Description: The contents of register 'f' are decre- mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded and an NOP is executed instead mak- ing it a two cycle instruction. W ords: 1 Cycles: 1(2) Example: HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE • Before Instruction PC = address (HERE) After Instruction CNT = CNT - 1; if CNT = 0, PC = address (CONTINUE); if CNT „ 0, PC = address (HERE+1) GO TO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 £ k £ 511 Operation: k fi PC<8:0>; STATUS<6:5> fi PC<10:9> Status Affected: None Encoding: 101kkkkkkkkk Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS <6:5>. GOTO is a two cycle instruction. W ords: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE)

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 45 PIC16C505 INCF Increment f Syntax: [ label ] INCF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) + 1 fi (dest) Status Affected: Z Encoding: 001010dfffff Description: The contents of register 'f' are incre- mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. W ords: 1 Cycles: 1 Example: INCFCNT,1 Before Instruction CNT = 0xFF Z = 0 After Instruction CNT = 0x00 Z = 1 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) + 1 fi (dest), skip if result = 0 Status Affected: None Encoding: 001111dfffff Description: The contents of register 'f' are incre- mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and an NOP is executed instead making it a two cycle instruc- tion. W ords: 1 Cycles: 1(2) Example: HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE • Before Instruction PC = address (HERE) After Instruction CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT „ 0, PC = address (HERE +1) IORLW Inclusive OR literal with W Syntax: [ label ] IORLW k Operands: 0 £ k £ 255 Operation: (W) .OR. (k) fi (W) Status Affected: Z Encoding: 1101kkkkkkkk Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example: IORLW0x35 Before Instruction W = 0x9A After Instruction W = 0xBF Z = 0 IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (W).OR. (f) fi (dest) Status Affected: Z Encoding: 000100dfffff Description: Inclusive OR the W register with regis- ter 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. W ords: 1 Cycles: 1 Example: IORWF RESULT, 0 Before Instruction RESUL T = 0x13 W = 0x91 After Instruction RESUL T = 0x13 W = 0x93 Z = 0

DS40192A -page 46 Preliminary Ó 1998 Microchip Technology Inc. MO VF Mo ve f Syntax: [ label ] MOVF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) fi (dest) Status Affected: Z Encoding: 001000dfffff Description: The contents of register 'f' is moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag Z is affected. W ords: 1 Cycles: 1 Example: MOVFFSR,0 After Instruction W = value in FSR register MO VLW Mo ve Literal to W Syntax: [ label ] MOVLW k Operands: 0 £ k £ 255 Operation: k fi (W) Status Affected: None Encoding: 1100kkkkkkkk Description: The eight bit literal 'k' is loaded into the W register. The don’t cares will assem- ble as 0s. W ords: 1 Cycles: 1 Example: MOVLW0x5A After Instruction W = 0x5A MO VWF Mo ve W to f Syntax: [ label ] MOVWF f Operands: 0 £ f £ 31 Operation: (W) fi (f) Status Affected: None Encoding: 0000001fffff Description: Mo ve data from the W register to regis- ter 'f'. W ords: 1 Cycles: 1 Example: MOVWFTEMP_REG Before Instruction TEMP_REG = 0xFF W = 0x4F After Instruction TEMP_REG = 0x4F W = 0x4F NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Encoding: 000000000000 Description: No operation. W ords: 1 Cycles: 1 Example: NOP

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 47 PIC16C505 OPTION Load OPTION Register Syntax: [ label ] OPTION Operands: None Operation: (W ) fi OPTION Status Affected: None Encoding: 000000000010 Description: The content of the W register is loaded into the OPTION register. W ords: 1 Cycles: 1 Example OPTION Before Instruction W = 0x07 After Instruction OPTION = 0x07 RETL W Return with Literal in W Syntax: [ label ] RETLW k Operands: 0 £ k £ 255 Operation: k fi (W ); TOS fi PC Status Affected: None Encoding: 1000kkkkkkkk Description: The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. W ords: 1 Cycles: 2 Example: TABLE CALL TABLE ;W contains ;table offset ;value.

• ;W now has table
• ;value. ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: See description below Status Affected: C Encoding: 001101dfffff Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: See description below Status Affected: C Encoding: 001100dfffff Description: The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. W ords: 1 Cycles: 1 Example: RRF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0 C register 'f' C register 'f'

DS40192A -page 48 Preliminary Ó 1998 Microchip Technology Inc. SLEEP Enter SLEEP Mode Syntax: [label] SLEEP Operands: None Operation: 00h fi WDT ; 0 fi WDT prescaler; 1 fi TO ; 0 fi PD Status Affected: TO , PD , RB WUF Encoding: 000000000011 Description: Time-out status bit (TO ) is set. The pow er down status bit (PD ) is cleared. RB WUF is unaffected. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See sec- tion on SLEEP for more details. W ords: 1 Cycles: 1 Example: SLEEP SUBWF Subtract W from f Syntax: [label] SUBWF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f) – (W) fi (dest) Status Affected: C, DC, Z Encoding: 000010dfffff Description: Subtract (2’s complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example 1: SUBWF REG1, 1 Before Instruction REG1 = 3 W = 2 C = ? After Instruction REG1 = 1 W = 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = FF W = 2 C = 0 ; result is negative

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 49 PIC16C505 SW APF Swap Nibbles in f Syntax: [ label ] SW APF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (f<3:0>) fi (dest<7:4>); (f<7:4>) fi (dest<3:0>) Status Affected: None Encoding: 001110dfffff Description: The upper and low er nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. W ords: 1 Cycles: 1 Example SWAPFREG1,0 Before Instruction REG 1 = 0xA5 After Instruction REG 1 = 0xA5 W = 0X5A TRIS Load TRIS Register Syntax: [ label ] TRIS f Operands: f = 6 Operation: (W ) fi TRIS register f Status Affected: None Encoding: 000000000fff Description: TRIS register 'f' (f = 6 or 7) is loaded with the contents of the W register W ords: 1 Cycles: 1 Example TRISPORTB Before Instruction W = 0XA5 After Instruction TRIS = 0XA5 XORL W Exclusive OR literal with W Syntax: [label] XORL W k Operands: 0 £ k £ 255 Operation: (W) .XOR. k fi (W) Status Affected: Z Encoding: 1111kkkkkkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register. W ords: 1 Cycles: 1 Example: XORLW0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A XOR WF Exclusive OR W with f Syntax: [ label ] XOR WF f,d Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (W) .XOR. (f) fi (dest) Status Affected: Z Encoding: 000110dfffff Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. W ords: 1 Cycles: 1 Example XORWFREG,1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5

DS40192A -page 50 Preliminary Ó 1998 Microchip Technology Inc. NO TES:

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 51 PIC16C505

9.0 DE VELOPMENT SUPPOR T

9.1 De velopme nt Tools

The PICmicroä microcontrollers are supported with a full range of hardware and software development tools:

• PICMASTER â /PICMASTER CE Real-Time In-Circuit Emulator
• ICEPICä Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator
• PR O MA TE â II Universal Programmer
• PICSTAR Tâ Plus Entry-Level Prototype Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MP ASM Assemb ler
• MPLAB ä SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System (fuzzyTECH â -MP)

9.2 PICMASTER: High Performance

Universal In-Circuit Emulator with MPLAB IDE The PICMASTER Univ ersal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, PIC16C5X, PIC16CXXX and PIC17CXX f amilies. PICMASTER is supplied with the MPLABä Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different proces- sors. The universal architecture of the PICMASTER allows expansion to support all new Microchip micro- controllers. The PICMASTER Em ulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows â 3.x environment were chosen to best make these fea- tures available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.

9.3 ICEPIC: Low-Cost PICmicro™

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT â through Pentiumä based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.

9.4 PR O MA TE II: Universal Programmer

The PRO MA TE II Universal Programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MA TE II is CE compliant. The PR O MA TE II has programmab le VDD and VPP supplies which allows it to verify programmed memor y at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assemb ly to support various package types. In stand- alone mode the PRO MA TE II can read, verify or pro- gram PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX de vices. It can also set configuration and code-protect bits in this mode.

9.5 PICSTAR T Plus Entry Level

The PICSTAR T programmer is an easy-to-use, low- cost prototype programmer . It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTAR T Plus is not recommended for production programming. PICSTAR T Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be sup- ported with an adapter socket. PICSTAR T Plus is CE compliant.

DS40192A -page 52 Preliminary Ó 1998 Microchip Technology Inc.

9.6 PICDEM-1 Low-Cost PICmicro

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrol- lers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs . The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PR O MA TE II or PICST AR T-Plus programmer , and easily test firm- w are. The user can also connect the PICDEM-1 board to the PICMASTER em ulator and down load the firmw are to the emulator for testing. Additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to POR TB .

9.7 PICDEM-2 Low-Cost PIC16CXX

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs . The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MA TE II pro- grammer or PICSTAR T-Plus, and easily test firmw are. The PICMASTER em ulator may also be used with the PICDEM-2 board to test firmw are. Additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- tion to an LCD module and a keypad.

9.8 PICDEM-3 Low-Cost PIC16CXXX

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the neces- sary hardware and software is included to run the basic demonstration programs . The user can pro- gram the sample microcontrollers provided with the PICDEM-3 board, on a PRO MA TE II program- mer or PICSTAR T Plus with an adapter socket, and easily test firmw are. The PICMASTER em ulator may also be used with the PICDEM-3 board to test firm- w are. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an addi- tional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A sim- ple serial interface allows the user to construct a hard- w are demultiplexer for the LCD signals.

9.9 MPLAB™ Integrated Development

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcon- troller market. MPLAB is a windows based application which contains:

• A full featured editor
• Three operating modes - editor - em ulator - simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information)
• Deb ug using: - source files - absolute listing file
• Transfer data dynamically via DDE (soon to be replaced by OLE)
• Run up to four emulators on the same PC The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured em ulator with minimal retraining due to development tools.

9.10 Assemb ler (MPASM)

The MP ASM Univ ersal Macro Assembler is a PC- hosted symbolic assembler. It supports all microcon- troller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MP ASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers . MP ASM allo ws full symbolic deb ugging from PICMASTER, Microchip’s Universal Emulator System.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 53 PIC16C505 MP ASM has the following features to assist in develop- ing software for specific use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source and listing formats. MP ASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.

9.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Softw are Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MP ASM. The Software Simulator offers the low cost flexibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool.

9.12 C Compiler (MPLAB-C17)

The MPLAB-C Code De velopment System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX f amily of microcontrollers. The compiler provides pow erful inte- gration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler pro- vides symbol information that is compatible with the MPLAB IDE memor y display.

9.13 Fuzzy Logic Development System

(fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive w orking knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP , Edition for imple- menting more complex systems. Both versions include Microchip’s fuzzyLAB ä demon- stration board for hands-on experience with fuzzy logic systems implementation.

9.14 MP-DriveW ayä – Application Code

MP-DriveW ay is an easy-to-use Windows-based Appli- cation Code Generator. With MP-DriveW ay you can visually configure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Micro- chip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveW ay is intelligent enough to maintain your code through subsequent code generation.

9.15 SEEV AL â Evaluation and

The SEEV AL SEEPR OM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs . The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsÔ and secure serials. The Total EnduranceÔ Disk is included to aid in trade- off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.

9.16 K EE LOQ â Evaluation and

KEE LOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.

DS40192A -page 54 Preliminary Ó 1998 Microchip Technology Inc. TAB LE 9-1: DE VELOPMENT TOOLS FR OM MICR OC HIP PIC12C5XX PIC16C505 PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X 24CXX 25CXX 93CXX HCS200 HCS300 HCS301 EMULATOR PRODUCTS PICMASTER â / PICMASTER-CE In-Circuit Emulator ü ü ü ü ü ü ü ü ü ü ICEPICä Low-Cost In-Circuit Emulator ü ü ü ü ü ü ü SOFTWARE PRODUCTS MPLAB ä Integrated Development Environment ü ü ü ü ü ü ü ü ü ü MPLAB ä C17 Compiler ü ü fuzzyTECH â -MP Explorer/Edition Fuzzy Logic Dev. Tool ü ü ü ü ü ü ü ü ü MP-DriveWay ä

Applications

ü ü ü ü ü ü ü Total Enduranceä Software Model ü PROGRAMMERS PICSTART â Plus Low-Cost Universal Dev. Kit ü ü ü ü ü ü ü ü ü ü PRO MATE â II Universal Programmer ü ü ü ü ü ü ü ü ü ü ü ü KEELOQ â Programmer ü DEMO BOARDS SEEVAL â Designers Kit ü PICDEM-1 ü ü ü ü PICDEM-2 ü ü PICDEM-3 ü KEELOQ â Evaluation Kit ü

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 55 PIC16C505

10.0 ELECTRICAL CHARACTERISTICS - PIC16C505

Absolute Maximum Ratings† Note 1:Pow er Dissipation is calculated as follows: PDIS = VDD x {IDD - å IOH } + å {(VDD -VOH ) x IOH } + å (VOL x IOL ) †NO TICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

DS40192A -page 56 Preliminary Ó 1998 Microchip Technology Inc.

10.1 DC CHARA CTERISTICS: PIC16C5 05-04 (Commercial, Industrial, Extended)

PIC16C505-20(Commer cial, Industrial, Extended) DC Characteristics Power Supply Pins Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) –40°C £ TA £ +125°C (extended) Characteristic Sym Min Typ(1) Max Units Conditions Supply Voltage VDD 3.0 4.5 5.5 5.5 V V XT, EXTRC, INTRC and LP OSC configura- tion H S OSC configuration RAM Data Retention Voltage (2) VDR 1.5* V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR VSS V See section on Pow er-on Reset for details VDD Rise Rate to ensure Power-on Reset SVDD 0.05* V/ms See section on Pow er-on Reset for details Supply Current(3) IDD — 1.8 1.8 4.5 2.4 2.4 m A mA mA mA mA m A XT and EXTRC options (Note 4) F OSC = 4 MHz, VDD = 5.5V INTRC Option F OSC = 4 MHz, VDD = 5.5V LP OPTION , Commercial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION , Industrial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION , Extended Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled HS O PTION , Industrial Temperature FOSC = 20 MHz, VDD = 5.5V Power-Down Current (5) WDT Enab led WDT Disab led IPD 0.25 0.25 mA mA mA mA mA mA V DD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 3.0V, Extended VDD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 3.0V, Extended * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid- ance only and is not tested. 2: This is the limit to which VDD can be low ered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD , MCLR = VDD ; WDT enab led/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the form ula: IR = VDD /2Rext (mA) with Rext in kOhm. 5: The pow er down current in SLEEP mode does not depend on the oscillator type. Pow er down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS .

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 57 PIC16C505

10.2 DC CHARA CTERISTICS: PIC16LC5 05-04 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) –40°C £ TA £ +125°C (extended) Characteristic Sym Min Typ(1) Max Units Conditions Supply Voltage VDD 3.0 2.5 5.5 5.5 V V XT, EXTRC, INTRC OSC configuration LP OSC configuration RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR VSS V See section on Pow er-on Reset for details VDD Rise Rate to ensure Power-on Reset SVDD 0.05* V/ms See section on Pow er-on Reset for details Supply Current(3) IDD — 1.8 1.8 4.5 2.4 2.4 m A mA mA mA mA m A XT and EXTRC options (Note 4) F OSC = 4 MHz, VDD = 5.5V INTRC Option F OSC = 4 MHz, VDD = 5.5V LP OPTION , Commercial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION , Industrial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION , Extended Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled HS O PTION , Industrial Temperature FOSC = 20 MHz, VDD = 5.5V Power-Down Current (5) WDT Enab led WDT Disab led IPD 0.25 0.25 mA mA mA mA mA mA V DD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 3.0V, Extended VDD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 3.0V, Extended * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid- ance only and is not tested. 2: This is the limit to which VDD can be low ered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD , MCLR = VDD ; WDT enab led/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the form ula: IR = VDD /2Rext (mA) with Rext in kOhm. 5: The pow er down current in SLEEP mode does not depend on the oscillator type. Pow er down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS .

DS40192A -page 58 Preliminary Ó 1998 Microchip Technology Inc.

10.3 DC CHARA CTERISTICS: PIC16C505-04 (Commer cial, Industrial, Extended)

PIC16C505-20(Commer cial, Industrial, Extended) PIC16LC505-04 (Commer cial, Industrial, Extended) DC Characteristics All Pins Except Power Supply Pins Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) –40°C £ TA £ +125°C (extended) Operating Voltage VDD range is described in Section 10.1. Characteristic Sym Min Typ(1) Max Units Conditions Input Low Voltage I/O ports MCLR and RC5 (Schmitt Trigger) OSC1 OSC1 OSC1 V IL VSS VSS VSS VSS VSS VSS 0.8

0.15 VDD

0.20 VDD

0.3 VDD

0.6 VDD -1.0 V V V V V V Pin at hi-impedance 4.5V < V DD £ 5.5V Pin at hi-impedance 3.0V < V DD £ 4.5V EXTRC option only(4) XT and HS options LP option Input High Voltage I/O ports MCLR and RC5 (Schmitt Trigger) OSC1 (Schmitt Trigger) IPUR VIH 0.25VDD +0.8V 2.0 0.2VDD +1V

0.8 VDD

0.9 VDD

0.7 VDD

V V V V V V 2.5V < V DD £ 4.5V 4.5V < VDD £ 5.5V(5) Full VDD range(5) Full VDD range EXTRC option only(4) HS , XT and LP options Input Leakage Current(2,3) I/O ports MCLR OSC1 IIL 0.5 130 0.5 0.5 250 mA mA mA mA For V DD £ 5.5V VSS £ VPIN £ VDD , Pin at hi-impedance V PIN = VSS + 0.25V(2) VPIN = VDD VSS £ VPIN £ VDD , XT and LP options Output Low Voltage I/O ports Vol 0.6 V IOL = 8.7 mA, VDD = 4.5V Output High Voltage(3,4) I/O ports VoH VDD –0.7 V IOH = –5.4 mA, VDD = 4.5V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid- ance only and is not tested. 2: The leakage current on the MCLR /VPP /RB3 pin is strongly dependent on the applied voltage level. The spec- ified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C505 devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505 be driven with external clock in RC mode. 5: The user may use the better of the two specifications.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 59 PIC16C505

10.4 Timing Parameter Symbology and Load Conditions - PIC16C505

The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Low ercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLK OUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt w atchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 10-1: LOAD CONDITIONS - PIC16C505 C L VSS Pin C L = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1

DS40192A -page 60 Preliminary Ó 1998 Microchip Technology Inc.

10.5 Timing Diagrams and Specifications

FIGURE 10-2: EXTERNAL CLOC K TIMING - PIC16C505 TAB LE 10-1: EXTERNAL CLOC K TIMING REQUIREMENTS - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial), –40°C £ TA £ +85°C (industrial), –40°C £ TA £ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions FOSC External CLKIN Frequency(2) DC — 4 MHz XT osc mode DC — 4 MHz HS osc mode (PIC16C505-04) DC — 200 kHz LP osc mode Oscillator Frequency(2) DC — 4 MHz EXTRC osc mode 0.1 — 4 MHz XT osc mode 4 — 4 MHz HS osc mode (PIC16C505-04) 4 — 20 MHz HS osc mode (PIC16C505-20) DC — 200 kHz LP osc mode

1 TOSC External CLKIN Period(2) 250 — — ns XT osc mode

5 — — ms LP osc mode Oscillator Period(2) 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS ocs mode (PIC16C505-04) 50 — 250 ns HS ocs mode (PIC16C505-20) 5 — — ms LP osc mode

2 Tcy Instruction Cycle Time(3) — 4/FOSC DC ns

200 — ns TC4 = 4/FOSC * These parameters are characterized but not tested. Note 1:Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (TCY ) equals four times the input oscillator time base period. OSC1 Q4 Q1 Q2 Q3 Q4 Q1 1 3 3 4 4

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 61 PIC16C505

3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator

2* — — ms LP oscillator 10 ns HS oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator

— — 50* ns LP oscillator — — 15 ns HS oscillator TAB LE 10-1: EXTERNAL CLOC K TIMING REQUIREMENTS - PIC16C505 (CONTINUED) AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial), –40°C £ TA £ +85°C (industrial), –40°C £ TA £ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions * These parameters are characterized but not tested. Note 1:Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (TCY ) equals four times the input oscillator time base period.

DS40192A -page 62 Preliminary Ó 1998 Microchip Technology Inc. FIGURE 10-3: I/O TIMING - PIC16C505 TAB LE 10-2: TIMING REQUIREMENTS - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) –40°C £ TA £ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym Characteristic Min Typ(1) Max Units

17 TosH2ioV OSC1 › (Q1 cycle) to Port out valid(3) — — 100* ns

18 TosH2ioI OSC1 › (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 TioV2osH Port input valid to OSC1›

(I/O in setup time) TBD — — ns

20 TioR Port output rise time(3) — 10 25** ns

21 TioF Port output fall time(3) — 10 25** ns

• These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 10-1 for loading conditions. OSC1 I/O Pin (input) I/O Pin (output) Q4 Q1 Q2 Q3 20, 21 Old Value Ne w Value Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT .

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 63 PIC16C505 FIGURE 10-4: RESET, W ATC HDOG TIMER , AND DE VICE RESET TIMER TIMING - PIC16C505 TAB LE 10-3: RESET, W ATC HDOG TIMER , AND DE VICE RESET TIMER - PIC16C505 TAB LE 10-4: DR T (DEVICE RESET TIMER PERIOD - PIC16C505 AC CharacteristicsStandard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) –40°C £ TA £ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V

31 Twdt W atchdog Timer Time-out Period

(No Prescaler) 9* 18* 30* ms VDD = 5 V (Commercial)

32 TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5 V (Commercial)

34 TioZ I/O Hi-impedance from MCLR Low — — 2000* ns

• These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Oscillator Configuration POR Reset Subsequent Resets IntRC & ExtRC 18 ms (typical) 300 ms (typical) XT, HS & LP 18 ms (typical) 18 ms (typical) VDD MCLR Internal POR DR TTimeout Internal RESET W atchdog Timer RESET I/O pin 32 32 (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. (Note 2) 2: Runs in MCLR or WDT reset only in XT, LP and HS modes.

DS40192A -page 64 Preliminary Ó 1998 Microchip Technology Inc. FIGURE 10-5: TIMER0 CLOC K TIMINGS - PIC16C505 TAB LE 10-5: TIMER0 CLOC K REQUIREMENTS - PIC16C505 TAB LE 10-6: PULL-UP RESISTOR RANG ES - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) –40°C £ TA £ +125°C (extended) Operating Voltage VDD range is described in Section 10.1. Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions 40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N — — ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. VDD (Volts) Temperature (°C) Min Typ Max Units RB0/RB1/RB4 3.0 -40 27K 32K 35K W 25 33K 38K 43K W 85 33K 39K 43K W 125 37K 42K 60K W 5.5 -40 15K 17K 20K W 25 18K 20K 23K W 85 19K 22K 25K W 125 22K 24K 28K W RB3 3.0 -40 271K 326K 395K W 25 327K 390K 492K W 85 348K 427K 500K W 125 400K 472K 567K W 5.5 -40 247K 292K 360K W 25 288K 341K 437K W 85 306K 371K 448K W 125 351K 407K 500K W * These parameters are characterized but not tested. T0CKI 40 41

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 65 PIC16C505

11.0 DC AND A C CHARACTERISTICS - PIC16C505

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3s) and (mean – 3s) respectively, where s is standard deviation. FIGURE 11-1: CALIBRATED INTERNAL RC FREQUENC Y RANG E VS. TEMPERATURE (V DD = 5.0V) (INTERNAL RC IS CALIBRATED TO 25 °C, 5.0V) FIGURE 11-2: CALIBRATED INTERNAL RC FREQUENC Y RANG E VS. TEMPERATURE (V DD = 3.0V) (INTERNAL RC IS CALIBRATED TO 25 °C, 5.0V) Not available at this time. Not available at this time.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 69 PIC16C505

12.0 PAC KA GING INFORMATION

12.1 Package Marking Information

Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB W eek code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5” Line S = 6” Line H = 8” Line D Mask revision number E Assemb ly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. MMMMMMMMMMMMMM XXXXXXXXXXXXXX AABBCDE 14-Lead PDIP (300 mil) Example 14-Lead SOIC (150 mil) MMMMMMMMMM AABBCDE 14-Lead Window ed Ceramic Side Brazed (300 mil) MMMMMMM MM Example Example 16C505-04I/P BUILT 4 SPEED 9804SAZ 16C505-04I 9804SAZ 16C505 JW

DS40192A -page 70 Preliminary Ó 1998 Microchip Technology Inc. Package Type: K04-005 14-Lead Plastic Dual In-line (P) – 300 mil n 1 R Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Ro w Spacing 0.300 7.62 Number of Pins n 14 14 Pitch p 0.100 2.54 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom b 5 10 15 5 10 15 a p L B A c b eB D E * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 71 PIC16C505 Package Type: K04-065 14-Lead Plastic Small Outline (SL) – Narrow , 150 mil MINDimension Limits Mold Draft Angle Bottom Mold Draft Angle Top Low er Lead Width Radius Centerline Gull Wing Radius Shoulder Radius Chamfer Distance Outside Dimension Molded Package Width Molded Package Length Shoulder Height Ov erall Pack. Height Lead Thickness Foot Angle Foot Length Standoff Number of Pins Pitch b a c B f X A n p E L D Units MAXNOMMINMAXNOM 0.017 0.009 0.014 0.008 0.019 0.010 0.005 0.016 0.005 0.005 0.014 0.236 0.153 0.341 0.006 0.036 0.063 0.050 0.150 0.005 0.000 0.011 0.005 0.010 0.230 0.338 0.004 0.027 0.058 0.156 0.010 0.021 0.010 0.010 0.018 0.242 4 8 0.344 0.008 0.044 0.068 0.36 0.19 0.42 0.22 0.48 0.25 3.81 0.00 0.28 0.13 0.13 0.25 5.84 8.59 0.10 0.69 1.47 3.963.89 0.13 0.13 0.41 0.36 0.13 5.99 0.25 0.25 0.53 0.46 0.25 6.15 0.15 8.66 0.90 1.60 1.27 0.20 8.74 1.12 1.73 INCHES* MILLIMETERS n 1 D p B E X L c b 45° f a A1A * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

DS40192A -page 72 Preliminary Ó 1998 Microchip Technology Inc. Package Type: 14-Lead Ceramic Side Brazed Dual In-line with Windo w (JW) – 300 mil n 1 0.260 0.440 0.161 0.310 0.280 0.680 0.130 0.025 0.103 0.145 0.008 0.050 0.016 0.098 MIN Window Diameter Ov erall Row Spacing Package Length Tip to Seating Plane Base to Seating Plane Top of Body to Seating Plane Top to Seating Plane Upper Lead Width Low er Lead Width PCB Ro w Spacing Dimension Limits Lid Length Lid Width Package Width Lead Thickness Number of Pins Pitch Units T U D W eB E L B A c p n 0.450 0.270 0.700 0.166 0.338 0.290 0.140 0.035 0.123 0.460 0.280 0.171 0.365 0.300 0.720 0.150 0.045 0.143 NOM 0.018 0.165 0.010 0.055 0.100 0.300 MAX 0.185 0.012 0.060 0.020 0.102 6.86 11.43 4.22 8.57 7.37 17.78 3.56 0.89 3.12 11.18 6.60 17.27 4.09 7.87 7.11 3.30 0.64 2.62 11.68 7.11 18.29 4.34 9.27 7.62 3.81 1.14 3.63 4.19 0.25 1.40 0.46 2.54 7.62 NOM MILLIMETERS MIN 0.41 3.68 0.20 1.27 2.49 MAX 0.51 4.70 0.30 1.52 2.59 DT E U W c eB L B A p INCHES* * Controlling Parameter.

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 73 PIC16C505 INDEX A Assembler B Block Diagram C D F Family of Devices I K L M MPLAB Integrated Development Environment Software....52 O Oscillator Types P POR Q R Registers S T Timer0 W Z

DS40192A -page 74 Preliminary Ó 1998 Microchip Technology Inc. NOTES:

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 75 PIC16C505 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. Trademarks: The Microchip name, logo, PIC, PICSTAR T, PICMASTER and PRO MA TE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexR OM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Micro- chip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. ON-LINE SUPPOR T Microchip provides on-line support on the Microchip W orld Wide W eb (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet W eb Site The Microchip web site is available by using your favorite Internet browser to attach to: www .microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users ma y download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs . A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is:

• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to Microchip Products
• Conferences for products, Development Systems, technical information and more
• Listing of seminars and events 980106

DS40192A -page 76 Preliminary Ó 1998 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. 1. What are the best features of this document? 2. Ho w does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. Ho w would you improve this document? 8. Ho w would you improve our software, systems, and silicon products? To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Compan y Address City / State / ZIP / Country Application (optional): W ould you like a reply? Y N Device: Literature Number: Questions: DS40192APIC16C505

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 77 PIC16C505 PIC16C505 Product Identification System Please contact your local sales office for exact ordering procedures. Pattern: Special Requirements Package: SL = 150 mil SOIC P = 300 mil PDIP JW = 300 mil Window ed Ceramic Side Brazed Temperature Rang e: - = 0°C to +70°C I = -40°C to +85°C E = -40°C to +125°C Frequency Rang e: 04 = 4 MH z (XT, INTRC, EXTRC OSC) 04 = 200 KHz (LP OSC) 20 = 20 MHz (HS OSC) De vice PIC16C505 PIC16LC505 PIC16C505T (Tape & reel for SOIC only) PIC16LC505T (Tape & reel for SOIC only) PAR T NO. -XX X /XX XXX Examples a) PIC16C50 5-04/P Commercial Temp ., normal VDD limits b) PIC16C50 5-04I/SL Industrial Temp ., SOIC package, 4 MHz, normal VDD limits c) PIC16C50 5-04I/P Industrial Temp ., PDIP package, 4 M Hz, normal VDD limits Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended w orkarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: Your local Microchip sales office (see below) The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

DS40192A -page 78 Preliminary Ó 1998 Microchip Technology Inc. NO TES:

Ó 1998 Microchip Technology Inc. Preliminary DS40192A -page 79 PIC16C505 NO TES:

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or trademarks mentioned herein are the property of their respective companies. DS40192A -page 80 ª 1998 Microchip Technology Inc. All rights reserved. © 1998, Microchip Technology Incorporated, USA. 4/98 Printed on recycled paper. M AMERICAS Corporate Office Microchip Technology Inc. 2355 W est Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 W eb: http://www.microchip.com Atlanta Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Da yton Microchip Technology Inc. Tw o Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Los Angeles Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338 Ne w York Microchip Technology Inc.

150 Motor Parkway, Suite 202

Hauppauge , NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto Microchip Technology Inc.

5925 Airport Road, Suite 200

Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 ASIA/PACIFIC Hong K ong Microchip Asia Pacific RM 3801B , Tow er Tw o Metroplaza

223 Hing Fong Road

Kw ai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 India Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Japan Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagaw a 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg.

2077 Yan’an Road W est, Hong Qiao District

Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Singapore Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 ASIA/PACIFIC (continued) Taiwan, R.O.C Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUR OPE United Kingdom Arizona Microchip Technology Ltd.

505 Eskdale Road

Berkshire, England RG41 5TU Tel: 44-1189-21-5858Fax: 44-1189-21-5835 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde

2 Rue du Buisson aux Fraises

91300 Massy, France

Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Müchen, German y Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 4/3/98 W ORLDWIDE SALES AND SERVICE Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmab le PICmicro™ 8-bit MCUs, Serial EEPROMs , related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).