16C2850 EXAR | Alldatasheet
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EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XR16C2850 Rev. 1.00P DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX CONTROL
DESCRIPTION
The XR16C2850 (2850) is a dual universal asynchronous receiver and transmitter (UART). The 2850 provides enhanced UART functions with 128 byte FIFO, automatic RS-485 half duplex control, a modem control interface, and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generators are provided to select transmit and receive clock rates up to 1.5 Mbps. The baud rate generator can be configured for either crystal or external clock input. The 2850 is available in a 40-pin PDIP, 44-pin PLCC, and 48-pin TQFP packages. The 40 pin package does not offer TXRDY and RXRDY pins (DMA Signal monitoring). Otherwise the three package versions are the same. The 2850 is functionally compatible with the ST16C2550. The 2850 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.
FEATURES
- Pin and functionally compatible to ST16C2550, software compatible with INS8250, NS16C550
- 1.5 Mbps transmit/receive operation (24 MHz Max.).
- 128 byte transmit FIFO to reduce bandwidth re- quirement of the external CPU.
- 128 byte receive FIFO with error flags to reduce bandwidth requirement of the external CPU.
- Independent transmit and receive UART control.
- RS-485 half duplex control.
- Programmable transmit/receive FIFO trigger lev- els.
- Hardware / software flow control.
- Selectable RTS flow control hysterisis.
- Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break).
- Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity.
- Infrared receive and transmit encoder/decoder.
- Device identification.
- Crystal or external clock input.
- 460.8 Kbps transmit/receive operation with 7.3728 MHz crystal or external clock source.
ORDERING INFORMATION
Part number Pins Package O perating temperature XR16C2850CP 40 PDIP 0° C to + 70° C XR16C2850CJ 44 PLCC 0° C to + 70° C XR16C2850CM 48 TQFP 0° C to + 70° C Part number Pins Package Operating temperature XR16C2850IP 40 PDIP -40° C to + 85° C XR16C2850IJ 44 PLCC -40° C to + 85° C XR16C2850IM 48 TQFP -40° C to + 85° C RXB RXA -TXRDYB TXA TXB -OPB -CSA -CSB RESET -DTRB -DTRA -RTSA -OPA -RXRDYA INTA INTB XTAL1 XTAL2 -IOW -CDB GND -RXRDYB -IOR -DSRB -RIB -RTSB -CTSB -TXRDYA VCC -RIA -CDA -DSRA -CTSA XR16C2850CJ Preliminary Information
Rev. 1.00P
48 Pin TQFP Package 40 Pin DIP Package
Figure 1, Package Descriptions, 40 pin, 48 pin XR16C2850 RXB RXA N.C. TXA TXB -OPB -CSA -CSB N.C. XTAL1 XTAL2 -IOW -CDB GND N.C. -IOR -DSRB -RIB -RTSB -CTSB N.C. RESET -DTRB -DTRA -RTSA -OPA N.C. INTA INTB N.C. N.C. VCC -RIA -CDA -DSRA -CTSA -RSCTL XR16C2850CM RXB RXA TXA TXB -OPB -CSA -CSB XTAL1 XTAL2 -IOW -CDB GND VCC -RIA -CDA -DSRA -CTSA RESET -DTRB -DTRA -RTSA -OPA INTA INTB -CTSB -RTSB -RIB -DSRB -IOR XR16C2850CP
Rev. 1.00P Figure 2, Block Diagram D0-D7 -IOR -IOW RESET A0-A2 -CS A/B -RSCTL INT A/B -RXRDY A/B -TXRDY A/B -DTR A/B -RTS A/B -CTS A/B -RI A/B -CD A/B -DSR A/B TX A/B TXIR A/B RX A/B RXIR A/B XTAL1 XTAL2 Data bus Control Logic Register Select Logic Modem Control Logic Interrupt Control Logic Transmit FIFO Registers Flow Control Logic Transmit Shift Register Receive FIFO Registers Flow Control Logic Receive Shift Register Inter Connect Bus Lines Control signals Clock Baud Rate Generator Ir Encoder Ir Decoder
Rev. 1.00P SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type A0 28 31 28 I Address-0 Select Bit. - Internal register address selection. A1 27 30 27 I Address-1 Select Bit. - Internal register address selection. A2 26 29 26 I Address-2 Select Bit. - Internal register address selection. -CS A-B 14,15 16,17 10,11 I Chip Select A, B (active low) - This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the 2850 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective -CS A- B pin. D0-D7 1-8 2-9 44-48 I/O 1-3 Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. GND 20 22 17 Pwr Signal and power ground. INT A-B 30,29 33,32 30,29 O Interrupt A, B (three state) - This function is associated with individual channel interrupts, INT A-B. INT A-B are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver er- rors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. -IOR 21 24 19 I Read strobe (active low strobe) - A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the 2850 data bus (D0-D7) for access by an external CPU. -IOW 18 20 15 I W rite strobe (active low strobe) - A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2.
Rev. 1.00P SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type -OP2 A-B 31,13 35,15 32,9 O Output -2 (User Defined) - This function is associated with individual channels, A through B. The state at these pin(s) are defined by the user and through the software setting of MCR register bit-3. INT A-B are set to the active mode and OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are set to the three state mode and OP2 to a logic 1 when MCR- 3 is set to a logic 0. See bit-3, Modem Control Register (MCR bit-3). RESET 35 39 36 I Reset (active high) - A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time (see XR16C2850 External Reset Conditions for initial- ization details). -RXRDY A-B - 34,23 31,18 O Receive Ready A-B (active low) - This function is associ- ated with 44 pin PLCC and 48 pin TQFP packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-B). RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is receive data to read/ unload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0). -TXRDY A-B - 1,12 43,6 O Transmit Ready A-B (active low) - This function is associ- ated with 44 pin PLCC and 48 pin TQFP packages only. These outputs provide the TX FIFO/THR status for indi- vidual transmit channels (A-B). TXRDY is primarily in- tended for monitoring DMA mode 1 transfers for the trans- mit data FIFOs. An individual channels -TXRDY A-B buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the FIFO or THR. This pin goes to a logic 1 when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode 0). VCC 40 44 42 Pwr Power supply input.
Rev. 1.00P SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type XTAL1 16 18 13 I Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. This configuration requires an external 1 MW resis- tor between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Program- ming). XTAL2 17 19 14 O Output of the Crystal Oscillator or Buffered Clock - (see also XTAL1). Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. -CD A-B 38,19 42,21 40,16 I Carrier Detect (active low) - These inputs are associated with individual UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -CTS A-B 36,25 40,28 38,23 I Clear to Send (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on the - CTS pin indicates the modem or data set is ready to accept transmit data from the 2850. Status can be tested by reading MSR bit-4. This pin has no effect on the UARTs transmit or receive operation. -DSR A-B 37,22 41,25 39,20 I Data Set Ready (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation. -DTR A-B 33,34 37,38 34,35 O Data Terminal Ready (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the 2850 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This
Rev. 1.00P SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type pin has no effect on the UARTs transmit or receive opera- tion. -RI A-B 39,23 43,26 41,21 I Ring Indicator (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. -RTS A-B 32,24 36,27 33,22 O Request to Send (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UARTs transmit or receive operation. RX A-B 10,9 11,10 5,4 I Receive Data (A-B) - These inputs are associated with individual serial channel data to the 2850 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the RX input pin is disabled and TX data is connected to the UART RX Input, internally. TX A-B 11,12 13,14 7,8 O Transmit Data (A-B) - These outputs are associated with individual serial transmit channel data from the 2850. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TX output pin is disabled and TX data is internally connected to the UART RX Input. -RSCTL - - 37 I RS-485 function select. When this pin is pulled high, normal -RTS function is selected. RS-485 direction control can be activated by connecting this pin to GND. This pin is wired Or-ed with FCTR Bit-3.
Rev. 1.00P GENERAL DESCRIPTION The XR16C2850 provides serial asynchronous re- ceive data synchronization, parallel-to-serial and se- rial-to-parallel data conversions for both the transmit- ter and receiver sections. These functions are neces- sary for converting the serial data stream into parallel data that is required with digital data systems. Syn- chronization for the serial data stream is accom- plished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The elec- tronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The XR16C2850 represents such an integration with greatly enhanced features. The 2850 is fabricated with an advanced CMOS process. The 2850 is an upward solution that provides 128 bytes of transmit and receive FIFO memory, instead of 16 bytes provided in the 16C2550. The 2850 is designed to work with high speed modems and shared network environments, that require fast data process- ing time. Increased performance is realized in the 2850 by the larger transmit and receive FIFO. This allows the external processor to handle more network- ing tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. How- ever with the 128 byte FIFO in the 2850, the data buffer will not require unloading/loading for 12.2 ms. This increases the service interval giving the external CPU additional time for other applications and reduc- ing the overall UART interrupt servicing time. In addition, the programmable levels of FIFO trigger interrupt and automatic hardware/software flow con- trol is uniquely provided for maximum data throughput performance especially when operating in a multi- channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The 2850 provides RS-485 half dulpex control signal to select the external transceiver direction. Auto RS- 485 control pin (-RTS) is not activated after reset. To activate the direction control function, user has to set EFR Bit-4, and FCTR Bit-3 to 1. The -RTS pin is normally high for receive mode and it will go low when transmitter starts transmitting data. FUNCTIONAL DESCRIPTIONS UART A-B Functions The UART provides the user with the capability to Bi- directionally transfer information between an external CPU and an external serial communication device. A logic 0 on chip select pins -CSA and/or -CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 2 below. Table 2, SERIAL PORT SELECTION GUIDE CHIP SELECT Function -CS A-B = 1s None -CS A = 0 UART CHANNEL A -CS B = 0 UART CHANNEL B Internal Registers The 2850 provides 15 internal registers for monitoring and control. These resisters are shown in Table 3. Twelve registers are similar to those already available in the standard 16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control regis- ter (FCR), line status and control registers, (LCR/ LSR), modem status and control registers (MCR/ MSR), programmable data rate (clock) control regis- ters (DLL/DLM), and a user accessible scratchpad register (SPR). Beyond the general 16C2550 features and capabilities, the 2850 offers an enhanced feature register set (EFR, Xon/Xoff 1-2) that provides on board hardware/software flow control. Register func- tions are more fully described in the following para- graphs.
Rev. 1.00P Table 3, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register 1 1 0 Modem Status Register 1 1 1 Scratchpad Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *3 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch Enhanced Register Set (EFR, Xon/off 1-2): Note *4 0 0 0 FIFO Trigger Register FIFO trigger counter 0 0 1 Feature Control Register 0 1 0 Enhanced Feature Register Enhanced Feature Register 1 0 0 Xon-1 Word Xon-1 Word 1 0 1 Xon-2 Word Xon-2 Word 1 1 0 Xoff-1 Word Xoff-1 Word 1 1 1 Xoff-2 Word Xoff-2 Word 1 1 1 Enhanced Mode Select Register Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1. Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to BF (HEX).
Rev. 1.00P FIFO Operation The 128 byte transmit and receive data FIFO are enabled by the FIFO Control Register (FCR) bit-0. With 16C2550 devices, the user can set the receive trigger level but not the transmit trigger level. The 2850 provides independent trigger levels for both receiver and transmitter. To remain compatible with ST16C2550, the transmit interrupt trigger level is set to 16 following a reset. It should be noted that the user can set the transmit trigger levels by writing to the FCR register, but activation will not take place until EFR bit- 4 is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (see hardware flow control for a description of this timing). Hardware Flow Control When automatic hardware flow control is enabled, the 2850 monitors the -CTS pin for a remote buffer overflow indication and controls the -RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to a logic 1. If -CTS transitions from a logic 0 to a logic 1 indicating a flow control request, ISR bit-5 will be set to a logic 1 (if enabled via IER bit 6-7), and the 2850 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the -CTS input returns to a logic 0, indicating more data may be sent. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the pro- grammed trigger level. The -RTS pin will not be forced to a logic 1 (RTS Off), until the receive FIFO reaches the next trigger level. The -RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger level. Under the above described conditions the 2850 will continue to accept data until the receive FIFO is full. Example of 650 trigger level selection Selected INT -RTS -RTS Trigger Pin Logic 1 Logic 0 Level Activation (characters) (characters) (characters) 88 1 6 0 16 16 24 8 24 24 28 16 28 28 28 24
Rev. 1.00P Software Flow Control When software flow control is enabled, the 2850 compares one or two sequential receive data charac- ters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the pro- grammed values, the 2850 will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER bit-5) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters values, the 2850 will monitor the receive data stream for a match to the Xon-1,2 character value(s). If a match is found, the 2850 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmis- sions. When double 8-bit Xon/Xoff characters are selected, the 2850 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmis- sions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the 2850 automati- cally sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 2850 sends the Xoff-1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the 2850 will transmit the programmed Xon-1,2 characters as soon as receive data drops below the programmed trigger level. Special Feature Software Flow Control A special feature is provided to detect an 8-bit charac- ter when bit-5 is set in the Enhanced Feature Register (EFR). When this character is detected, it will be placed on the user accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR bits 0-3. Note that software flow control should be turned off when using this special mode by setting EFR bit 0-3 to a logic 0. The 2850 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character (see Figure 9). Although the Internal Register Table shows each X- Register with eight bits of character information, the actual number of bits is dependent on the pro- grammed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. Time-out Interrupts Three special interrupts have been added to monitor the hardware and software flow control. The interrupts are enabled by IER bits 5-7. Care must be taken when handling these interrupts. Following a reset the trans- mitter interrupt is enabled, the 2850 will issue an interrupt to indicate that transmit holding register is empty. This interrupt must be serviced prior to con- tinuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/ RTS interrupt(s). Only after servicing the higher pend- ing interrupt will the lower priority CTS/ RTS interrupt(s) be reflected in the status register. Servic- ing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-0). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the 2850 FIFO may hold more characters than the programmed trigger level. Follow-
Rev. 1.00P ing the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time out value is T (Time out length in bits) = 4 X P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, includ- ing data information length, start bit, parity bit, and the size of stop bit, i.e., 1X, 1.5X, or 2X bit times. Example -A: If the user programs a word length of 7, with no parity and one stop bit, the time out will be: T = 4 X 7( programmed word length) +12 = 40 bit times. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out ex- ample: T = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. Example -B: If the user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bit times. Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1)] = 4 characters. Programmable Baud Rate Generator The 2850 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 2850 can support a standard data rate of 921.6Kbps. A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 2850 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crys- tal (parallel resonant 22-33 pF load) is connected externally between the XTAL1 and XTAL2 pins, with an external 1 MW resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. The generator divides the input 16X clock by any divisor from 1 to 2 16 -1. The 2850 divides the basic crystal or external clock by 16. Further division of this 16X clock provides two table rates to support low and high data rate applications using the same system design. The two rate tables are selectable through the internal register, MCR bit-7. Setting MCR bit-7 to a logic 1 provides an additional divide by 4 whereas, setting MCR bit-7 to a logic 0 only divides by 1 (see Table 4 and Figure 11). The frequency of the - BAUDOUT output pin is exactly 16X (16 times) of the selected baud rate (-BAUDOUT =16 x Baud Rate). Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sec- tions of baud rate generator. 22pF 33pF
1.8432 MHz
Crystal oscillator connection
Rev. 1.00P Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 4 below, shows the two selectable baud rate tables available when using a 7.3728 MHz crystal. Divide by 1 logic XTAL1 XTAL2 Divide by 4 logic Clock Oscillator Logic Baudrate Generator Logic -BAUDOUT MCR Bit-7=0 MCR Bit-7=1 Table 4, BAUD RATE GENERATOR PROGRAMMING TABLE (7.3728 MHz CLOCK): Output Output User User DLM DLL Baud Rate Baud Rate 16 x Clock 16 x Clock Program Program MCR MCR Divisor Divisor Value Value BIT-7=1 Bit-7=0 (Decimal) (HEX) (HEX) (HEX) 50 200 2304 900 09 00 75 300 1536 600 06 00 150 600 768 300 03 00 300 1200 384 180 01 80 600 2400 192 C0 00 C0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2K 24 18 00 18 7200 28.8K 16 10 00 10 9600 38.4k 12 0C 00 0C 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01 Figure 11, Baud Rate Generator Circuitry
Rev. 1.00P DMA Operation The 2850 FIFO trigger level provides additional flex- ibility to the user for block mode operation. LSR bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3). When the transmit and receive FIFO are enabled and the DMA mode is deactivated (DMA Mode 0), the 2850 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the 2850 sets the interrupt output pin when characters in the transmit FIFO are below the transmit trigger level, or the characters in the receive FIFO are above the receive trigger level. Sleep Mode The 2850 is designed to operate with low power consumption. A special sleep mode is included to further reduce power consumption when the chip is not being used. With EFR bit-4 and IER bit-4 enabled (set to a logic 1), the 2850 enters the sleep mode but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins RX, -RI, -CTS, -DSR, -CD, or transmit data is provided by the user. If the sleep mode is enabled and the 2850 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. In any case, the sleep mode will not be entered while an interrupt(s) is pending. The 2850 will stay in the sleep mode of operation until it is disabled by setting IER bit- 4 to a logic 0. Loopback Mode The internal loopback capability allows onboard diag- nostics. In the loopback mode the normal modem interface pins are disconnected and reconfigured for loopback internally. In this mode MSR bits 4-7 are also disconnected. However, MCR register bits 0-3 can be used for controlling loopback diagnostic testing. In the loopback mode, OP1 and OP2 in the MCR register (bits 0-1) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their asso- ciated interface pins, and instead are connected to- gether internally (see Figure 12). The -CTS, -DSR, - CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, -OP1 and -OP2. Loopback test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connec- tion. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally com- pares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. In this mode , the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using the lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still con- trolled by the IER.
Rev. 1.00P Figure 12, Internal Loopback Mode Diagram D0-D7 -IOR,-IOW RESET A0-A2 -CS A/B INT A/B -RXRDY -TXRDY TX A/B RX A/B Data bus Control Logic Register Select Logic Modem Control Logic Interrupt Control Logic Transmit FIFO Registers Flow Control Logic Transmit Shift Register Receive FIFO Registers Flow Control Logic Receive Shift Register Inter Connect Bus Lines Control signals Clock Baud Rate Generator XTAL1 XTAL2 Ir Encoder Ir Decoder -CTS A/B -RTS A/B -DTR A-D -DSR A/B -RI A/B -CD A/B -OP2 A/B MCR Bit-4=1 (-OP1 A/B)
Rev. 1.00P REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 2850 internal registers. The assigned bit functions are more fully defined in the following paragraphs. XR16C2850 ACCESSIBLE REGISTERS A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 [Default] Note *5 General Register Set 0 0 0 RHR [XX] b it-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR [XX] b it-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER [00] 0/ 0/ 0/ 0/ m odem receive transmit receive -CTS -RTS Xoff Sleep status line holding holding interrupt interrupt interrupt mode interrupt status register register interrupt 0 1 0 FCR [00] RCVR RCVR 0/TX 0/TX DMA XMIT RCVR FIFO trigger trigger trigger trigger mode FIFO FIFO enable (MSB) (LSB) (MSB) (LSB) select reset r eset 0 1 0 ISR [01] 0/ 0/ 0/ 0/ int int int int FIFOs FIFOs -RTS, Xoff priority priority priority status enabled enabled -CTS b it-2 bit-1 bit-0 0 1 1 LCR [00] d ivisor set set even parity stop word word latch break parity parity enable bits l ength length enable b it-1 bit-0 1 0 0 MCR [00] Clock 0/ 0/ loop INT -OP1 -RTS -DTR select IRRT Xon back Enable enable Any 1 0 1 LSR [60] 0/ THR & THR break framing parity overrun receive FIFO TSR empty interrupt error error error data error empty ready 1 1 0 MSR [00] -CD -RI -DSR -CTS delta delta delta delta -CD -RI -DSR -CTS 1 1 1 SCPAD [FF] b it-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Special Register Set: Note *3 0 0 0 DLL [00] b it-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM [00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
Rev. 1.00P A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 [Default] Note *5 Enhanced Register Set: Note *4 1 0 0 Xon-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 Xon-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 1 1 0 Xoff-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 Xoff-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 0 0 0 TRG [00] Trig/ Trig/ Trig/ Trig/ Trig Trig/ Trig/ Trig/ FC FC FC FC FC FC FC FC 0 0 1 FCTR [00] Rx/Tx SCPAD Trig Trig RS485 IrRx -RTS -RTS Mode Swap Bit-1 Bit-0 Auto Inv. Delay Delay control Bit-1 Bit-0 0 1 0 EFR [00] Auto Auto Special Enable Cont-3 Cont-2 Cont-1 Cont-0 -CTS -RTS Char. IER Tx,Rx Tx,Rx Tx,Rx Tx,Rx select Bits 4-7, Control Control Control Control ISR, FCR Bits 4-5, MCR Bits 5-7 1 1 1 EMSR [00] Not Not Not Not Not Not ALT. Rx/-Tx Used Used Used Used Used Used Rx/Tx FIFO FIFO Count Count Note *3: The Special Register Set is accessible only when LCR bit-7 is set to a logic 1. Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when LCR is set to BF Hex. Note *5: The value represents the registers initialized HEX value. An X signifies a 4-bit un-initialized nibble.
Rev. 1.00P Transmit and Receive Holding Register The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the 2850 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time, the start bit is sampled, and if it is still a logic 0, it is validated. Evaluating the start bit in this manner prevents the receiver from assem- bling a false character. Receiver status codes will be posted in the LSR. DEVICE IDENTIFICATION The XR16C2850 provides a Device Identification and Device Revision code to distinguish the part from others. To read the identification number from the part, its is required to set the baud rate generator divisor latch to 1 and then set the content of the baud rate generator DLL and DLM registers to 0. Reading the content of the DLM will provide 12 hex for XR16C2850 part and reading the content of the DLL will provide the revision of the part. Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the 2850 INT output pin. IER Vs Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: A) The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B) FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C) The data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. IER Vs Receive/Transmit FIFO Polled Mode Op- eration When FCR BIT-0 equals a logic 1, resetting IER bits 0-3 enables the 2850 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A) LSR BIT-0 will be a logic 1 as long as there is one byte in the receive FIFO. B) LSR BIT 1-4 will indicate if an overrun error occurred. C) LSR BIT-5 will indicate when the transmit FIFO is empty. D) LSR BIT-6 will indicate when both the transmit FIFO and transmit shift register are empty. E) LSR BIT-7 will indicate any FIFO data errors.
Rev. 1.00P IER BIT-0: Logic 0 = Disable the receiver ready interrupt (normal default condition). Logic 1 = Enable the receiver ready interrupt. IER BIT-1: Logic 0 = Disable the transmitter empty interrupt (normal default condition). Logic 1 = Enable the transmitter empty interrupt. IER BIT-2: Logic 0 = Disable the receiver line status interrupt (normal default condition). Logic 1 = Enable the receiver line status interrupt. IER BIT-3: Logic 0 = Disable the modem status register interrupt (normal default condition). Logic 1 = Enable the modem status register interrupt. IER BIT -4: Logic 0 = Disable sleep mode (normal default condi- tion). Logic 1 = Enable sleep mode. See Sleep Mode section for details. IER BIT-5: Logic 0 = Disable the software flow control, receive Xoff interrupt (normal default condition). Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details. IER BIT-6: Logic 0 = Disable the RTS interrupt (normal default condition). Logic 1 = Enable the RTS interrupt. The 2850 issues an interrupt when the RTS pin transitions from a logic 0 to a logic 1. IER BIT-7: Logic 0 = Disable the CTS interrupt (normal default condition). Logic 1 = Enable the CTS interrupt. The 2850 issues an interrupt when CTS pin transitions from a logic 0 to a logic 1. FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: DMA MODE Mode 0 Set and enable the interrupt for each single transmit or receive operation, and is similar to the ST16C450 mode. Transmit Ready (-TXRDY) will go to a logic 0 whenever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (-RXRDY) will go to a logic 0 when- ever the Receive Holding Register (RHR) is loaded with a character. Mode 1 Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. -TXRDY remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However the FIFO continues to fill regardless of the programmed level until the FIFO is full. -RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. FCR BIT-0: Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. This bit must be a 1 when other FCR bits are written to or they will not be programmed. FCR BIT-1: Logic 0 = No FIFO receive reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift regis- ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT-2: Logic 0 = No FIFO transmit reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift regis-
Rev. 1.00P ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT-3: Logic 0 = Set DMA mode 0 (normal default condi- tion). Logic 1 = Set DMA mode 1. Transmit operation in mode 0: When the 2850 is in the ST16C450 mode (FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and when there are no characters in the transmit FIFO or transmit holding register, the -TXRDY pin will be a logic 0. Once active the -TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode 0: When the 2850 is in mode 0 (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 0) and there is at least one character in the receive FIFO, the -RXRDY pin will be a logic 0. Once active the -RXRDY pin will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode 1: When the 2850 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode 1: When the 2850 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the - RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. FCR BIT 4-5: (logic 0 or cleared is the default condi- tion, TX trigger level = none) The XR16C2850 provide 4 user selectable trigger levels. The FCTR Bits 4-5 selects one of the following tables. These bits are used to set the trigger level for the transmit FIFO interrupt. The XR16C2850 will issue a transmit empty interrupt when the number of char- acters in FIFO drops below the selected trigger level. TRIGGER TABLE-A (Transmit) Default setting after reset ST16C550 mode BIT-5 BIT-4 FIFO trigger level X X None TRIGGER TABLE-B (Transmit) BIT-5 BIT-4 FIFO trigger level 00 1 6 01 8 10 2 4 11 3 0 TRIGGER TABLE-C (Transmit) BIT-5 BIT-4 FIFO trigger level 00 8 01 1 6 10 3 2 11 5 6 TRIGGER TABLE-D (Transmit) BIT-5 BIT-4 FIFO trigger level X X User programmable Trigger levels FCR BIT 6-7: (logic 0 or cleared is the default condi- tion, RX trigger level =8) These bits are used to set the trigger level for the receiver FIFO interrupt. The FCTR Bits 4-5 selects one of the following table.
Rev. 1.00P TRIGGER TABLE-A (Receive) Default setting after reset ST16C550 mode BIT-7 BIT-6 FIFO trigger level 00 1 01 4 10 8 11 1 4 TRIGGER TABLE-B (Receive) BIT-7 BIT-6 FIFO trigger level 00 8 01 1 6 10 2 4 11 2 8 TRIGGER TABLE-C (Receive) BIT-7 BIT-6 FIFO trigger level 00 8 01 1 6 10 5 6 11 6 0 TRIGGER TABLE-D (Receive) BIT-7 BIT-6 FIFO trigger level X X User programmable Trigger levels Interrupt Status Register (ISR) The 2850 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six inter- rupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowl- edged until the pending interrupt is serviced. When- ever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table. Table 6, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels:
Rev. 1.00P Table 6, INTERRUPT SOURCE TABLE Priority [ ISR BITS ] Level Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt 1 000110 L S R ( R eceiver Line Status Register) 2 000100 RXRDY (Received Data Ready) 2 001100 RXRDY (Receive Data time out) 3 000010 TXRDY ( Transmitter Holding Register Empty) 4 000000 M S R ( M odem Status Register) 5 010000 RXRDY (Received Xoff signal)/ Special character 6 100000 CTS, RTS change of state ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending (normal default condi- tion). ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Interrupt Source Table). ISR BIT 4-5: (logic 0 or cleared is the default condition) These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that matching Xoff character(s) have been detected. ISR bit-5 indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until Xon character(s) are received. ISR BIT 6-7: (logic 0 or cleared is the default condition) These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR BIT 0-1: (logic 0 or cleared is the default condi- tion) These two bits specify the word length to be transmit- ted or received. BIT-1 BIT-0 Word length 00 5 01 6 10 7 11 8 LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 Word l ength Stop bit length (Bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2
Rev. 1.00P LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity (normal default condition) Logic 1 = A parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- sion errors. LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1s in the transmitted. The receiver must be programmed to check the same format. LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced (normal default condition). LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR LCR LCR Parity selection Bit-3 Bit-4 Bit-5
0 X X No parity
1 0 1 Force parity 1 1 1 1 Forced parity 0 LCR BIT-6: When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition (normal default condition). Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. LCR BIT-7: The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled (normal default con- dition). Logic 1 = Divisor latch and enhanced feature register enabled. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. MCR BIT-0: Logic 0 = Force -DTR output to a logic 1 (normal default condition). Logic 1 = Force -DTR output to a logic 0. MCR BIT-1: Logic 0 = Force -RTS output to a logic 1 (normal default condition). Logic 1 = Force -RTS output to a logic 0. Automatic RTS may be used for hardware flow control by enabling EFR bit-6 (see EFR bit-6). MCR BIT-2: Internal loop back mode only. Logic 0 = Set -OP1 output to a logic 1. (normal default condition) Logic 1 = Set -OP1 output to a logic 0. MCR BIT-3: Logic 0 = Forces INT outputs to three state mode (normal default condition). Logic 1 = Forces the INT outputs to the active mode. MCR BIT-4: Logic 0 = Disable loopback mode (normal default condition). Logic 1 = Enable local loopback mode (diagnostics). MCR BIT-5: Logic 0 = Disable Xon-Any function (for 16C550 compatibility, normal default condition).
Rev. 1.00P Logic 1 = Enable Xon-Any function. In this mode, any RX character received will enable Xon. MCR BIT-6: Logic 0 = Enable Modem receive and transmit input/ output interface (normal default condition). Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/ Inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions. MCR BIT-7: Logic 0 = Divide by one. The input clock (crystal or external) is divided by sixteen and then presented to the Programmable Baud Rate Generator (BGR) with- out further modification, i.e., divide by one (normal, default condition). Logic 1 = Divide by four. The divide by one clock described in MCR bit-7 equals a logic 0, is further divided by four (also see Programmable Baud Rate Generator section). Line Status Register (LSR) This register provides the status of data transfers between. the 2850 and the CPU. LSR BIT-0: Logic 0 = No data in receive holding register or FIFO (normal default condition). Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR BIT-1: Logic 0 = No overrun error (normal default condition). Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when addi- tional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO; therefore, the data in the FIFO is not corrupted by the error. LSR BIT-2: Logic 0 = No parity error (normal default condition). Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. LSR BIT-3: Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode this error is associated with the character at the top of the FIFO. LSR BIT-4: Logic 0 = No break condition (normal default condi- tion) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. LSR BIT-5: This bit is the Transmit Holding Register Empty indi- cator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. LSR BIT-6: This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty.
Rev. 1.00P LSR BIT-7: Logic 0 = No Error (normal default condition). Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read and there are no subsequent errors in the FIFO. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that the 2850 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition). Logic 1 = The -CTS input to the 2850 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-1: Logic 0 = No -DSR Change (normal default condition). Logic 1 = The -DSR input to the 2850 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-2: Logic 0 = No -RI Change (normal default condition). Logic 1 = The -RI input to the 2850 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. MSR BIT-3: Logic 0 = No -CD Change (normal default condition). Logic 1 = Indicates that the -CD input has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-4: -CTS functions as hardware flow control signal input if it is enabled via EFR bit-7. The transmit holding register flow control is enabled/disabled by MSR bit-4. Flow control, when enabled, allows the starting and stopping of the transmissions based on the external modem -CTS signal. A logic 1 at the -CTS pin will stop 2850 transmissions as soon as current character has finished transmission. Normally MSR bit-4 bit is the compliment of the -CTS input. However, in the loopback mode, this bit is equivalent to the RTS bit in the MCR register. MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loopback mode, this bit is equivalent to the DTR bit in the MCR register. MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loopback mode this bit is equivalent to the OP1 bit in the MCR register. MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loopback mode this bit is equivalent to the OP2 bit in the MCR register. Scratchpad Register (SPR) The XR16C2850 provides a temporary data register to store 8 bits of user information. Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits-0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected (see Table 7), the double 8-bit words are concatenated into two sequential characters. EFR BIT 0-3: (logic 0 or cleared is the default condi- tion) Combinations of software flow control can be selected by programming these bits.
Rev. 1.00P Table 7, SOFTWARE FLOW CONTROL FUNCTIONS Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls 0 0 X X No transmit flow control 1 0 X X Transmit Xon1/Xoff1 0 1 X X Transmit Xon2/Xoff2 1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2 X X 0 0 No receive flow control X X 1 0 Receiver compares Xon1/Xoff1 X X 0 1 Receiver compares Xon2/Xoff2 1011 Transmit Xon1/ Xoff1. Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0111 Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1111 Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0011 N o transmit flow control
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 EFR BIT-5: Logic 0 = Special Character Detect Disabled (normal default condition). Logic 1 = Special Character Detect Enabled. The 2850 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special characters. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR bits 0-3 must be set to a logic 0). EFR BIT-6: Automatic RTS may be used for hardware flow control by enabling EFR bit-6. When AUTO RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and -RTS will go to a logic 1 at the next trigger level. -RTS will return to a logic 0 when data is unloaded below the next lower trigger level (Programmed trigger level -1). The state of this register bit changes with the status of the EFR BIT-4: Enhanced function control bit. The content of the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 can be modified and latched. After modifying any bits in the enhanced registers, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the 2850 enhanced functions. Logic 0 = disable/latch enhanced features. IER bits 4- 7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved to retain the user settings, then IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are initialized to the default values shown in the Internal Resister Table. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0, to be compatible with ST16C550 mode (normal default condition). Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the 2850 are enabled and user settings stored during a reset will be restored.
Rev. 1.00P hardware flow control. -RTS functions normally when hardware flow control is disabled. 0 = Automatic RTS flow control is disabled (normal default condition). 1 = Enable Automatic RTS flow control. EFR bit-7: Automatic CTS Flow Control. Logic 0 = Automatic CTS flow control is disabled (normal default condition). Logic 1 = Enable Automatic CTS flow control. Trans- mission will stop when -CTS goes to a logic 1. Trans- mission will resume when the -CTS pin returns to a logic 0. FEATURE CONTROL REGISTER This register controls the XR16C2850 new functions that are not available on ST16C550 or ST16C650. FCTR BIT 0-1: User selectable -RTS hysterisis for hardware flow control application. After reset, these bits are set to 0 to select the next trigger level for hardware flow control. FCTR FCTR Trigger Bit-1 Bit-0 level 0 0 Next trigger level 0 1 4 word+trigger level 1 0 6 word+trigger level 1 1 8 word+trigger level FCTR BIT-2: 0 = Select RX input as encoded IrDa data. 1 = Select RX input as active high encoded IrDa data. FCTR BIT-3: Interrupt type select and Auto RS-485 half duplex control. 0 = Standard ST16C550 mode. Transmitter generates interrupt when transmit holding register is empty and transmit shift register is shifting data out. 1 = Transmit empty interrupt. Transmit interrupt is generated when the transmitter holding and shift register is empty. The -RTS A/B out pins will stay high during receive mode and will go low during transmit mode. FCTR BIT 4-5: Transmit / receive trigger table select. FCTR FCTR Table Bit-5 Bit-4 0 0 Table-A (TX/RX) 0 1 Table-B (TX/RX) 1 0 Table-C (TX/RX) 1 1 Table-D (TX/RX) FCTR BIT-6: Register mode select. 0 = Scratch Pad register is selected as general read and write register (ST16C550 compatible mode). 1 = FIFO count register. Number of characters in transmit or receive holding register can be read via scratch pad register when this bit is set. FCTR BIT-7: Programmable trigger register select. 0 = Receiver programmable trigger level register is selected. 1 = Transmitter programmable trigger level register is selected.
Rev. 1.00P TRIGGER LEVEL / FIFO DATA COUNT REGISTER User programmable transmit / receive trigger level register. TRG BIT 0-7: Write only. These bits are used to program desire trigger levels that are not available in standard tables. TRG BIT 0-7: Read only. Transmit / receive FIFO count. Number of characters in transmit or receive FIFO can be read via this register. ENHANCED MODE SELECT REGISTER This register is accessible only when FCTR Bit-6 is set to 1. EMSR BIT-0: Write only 0 = Receive FIFO count register. The scratch pad register is used to provide the receive FIFO count when it is read. 1 = Transmit FIFO count register. The scratch pad register is used to provide the transmit FIFO count when it is read. EMSR BIT-1: Write only 0 = Normal. 1 = Alternate receive - transmit FIFO count. When EMSR Bit-0=1 and EMSR Bit=1, scratch pad register is used to provide the receive - transmit FIFO count when it is read every alternate read cycle. The TRG Bit-7 will provide the FIFO count mode information, TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit mode. EMSR BIT 4-7: Reserved for future use. XR16C2850 EXTERNAL RESET CONDITIONS REGISTERS RESET STATE IER IER BITS 0-7 = logic 0 ISR ISR BIT-0=1, ISR BITS 1-7 = logic 0 LCR, MCR BITS 0-7 = logic 0 LSR LSR BITS 0-4 = logic 0, LSR BITS 5-6 = logic 1 LSR, BIT 7 = logic 0 MSR MSR BITS 0-3 = logic 0, MSR BITS 4-7 = logic levels of the input signals FCR, EFR BITS 0-7 = logic 0 FCTR BITS 0-7= logic 0 EMSR BITS 0-7 = logic 0 SIGNALS RESET STATE TX Logic 1 -OP2 Logic 1 -RTS Logic 1 -DTR Logic 1 -RXRDY Logic 1 -TXRDY Logic 0 INT Logic 0
Rev. 1.00P Symbol Parameter Limits Limits Units Con ditions 3.3 5.0 Min Max Min Max AC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. T1w,T2w Clock pulse duration 17 17 ns T3w Oscillator/Clock frequency 8 24 MHz T6s Address setup time 5 0 ns T7d -IOR delay from chip select 10 10 ns T7w -IOR strobe width 35 25 ns T7h Chip select hold time from -IOR 0 0 ns T9d Read cycle delay 40 30 ns T12d Delay from -IOR to data 35 25 ns T12h Data disable time 25 15 ns T13d -IOW delay from chip select 10 10 ns T13w -IOW strobe width 40 25 ns T13h Chip select hold time from -IOW 0 0 ns T15d Write cycle delay 40 30 ns T16s Data setup time 20 15 ns T16h Data hold time 5 5 ns T17d Delay from -IOW to output 50 40 ns 100 pF load T18d Delay to set interrupt from MODEM 40 35 ns 100 pF load input T 19d Delay to reset interrupt from -IOR 40 35 ns 100 pF load T20d Delay from stop to set interrupt 1 1 Rclk T21d Delay from -IOR to reset interrupt 45 40 ns 100 pF load T22d Delay from stop to interrupt 45 40 ns T23d Delay from initial INT reset to transmit 8 24 8 24 Rclk start T 24d Delay from -IOW to reset interrupt 45 40 ns T25d Delay from stop to set -RxRdy 1 1 Rclk T26d Delay from -IOR to reset -RxRdy 45 40 ns T27d Delay from -IOW to set -TxRdy 45 40 ns T28d Delay from start to reset -TxRdy 8 8 Rclk TR Reset pulse width 40 40 ns N Baud rate devisor 1 2 16-1 1 2 16-1 Rclk
Rev. 1.00P ABSOLUTE MAXIMUM RATINGS Supply range 7 Volts Voltage at any pin GND - 0.3 V to VCC +0.3 V Operating temperature -40 ° C to +85° C Storage temperature -65° C to 150° C Package dissipation 500 mW DC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol Parameter Limits Limits Units Con ditions 3.3 5.0 Min Max Min Max VILCK Clock input low level -0.3 0.6 -0.5 0.6 V VIHCK Clock input high level 2.4 VCC 3.0 VCC V VIL Input low level -0.3 0.8 -0.5 0.8 V VIH Input high level 2.0 2.2 VCC V VOL Output low level on all outputs 0.4 V I OL= 5 mA VOL Output low level on all outputs 0.4 V I OL= 4 mA VOH Output high level 2.4 V I OH= -5 mA VOH Output high level 2.0 V I OH= -1 mA IIL Input leakage ±10 ±10 mA ICL Clock leakage ±10 ±10 mA ICC Avg power supply current 1.2 3 mA ISB Avg stand by current 30 100 mA CP Input capacitance 5 5 pF
Rev. 1.00P General write timing General read timing A0-A2 -CSx -IOW D0-D7 T6s T13wT13d T13h T15d T16s T16h X552-WD-2 Valid Address Active Active Data A0-A2 -CS -IOR D0-D7 T6s T7wT7d T7h T9d T12d T12h X552-RD-1 Active Data Valid Address Active
Rev. 1.00P External clock timing Modem input/output timing -IOW -RTS -DTR -CD -CTS -DSR INT -IOR -RI T17d T18d T18d T19d T18d X552-MD-1 Active Active Change of state Change of state Active Active Active Change of state Change of state Change of state Active Active T3w T1wT2w EXTERNAL CLOCK X654-CK-1
Rev. 1.00P Receive timing STOP BIT PARITY BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
-IOR T20d T21d
16 BAUD RATE CLOCK X552-RX-1
Rev. 1.00P Receive timing in FIFO mode Receive ready timing in none FIFO mode STOP BIT PARITY BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 START BIT RX First byte that reaches the trigger level -RXRDY -IOR T25d T26d X552-RX-3 Active Data Ready Active STOP BIT PARITY BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 START BIT RX NEXT DATA START BIT -RXRDY -IOR T25d T26d X552-RX-2 Active Data Ready Active
Rev. 1.00P Transmit timing STOP BIT PARITY BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7
16 BAUD RATE CLOCK X552-TX-1
-IOW T23d Active Active Tx Ready Active
Rev. 1.00P Transmit ready timing in none FIFO mode STOP BIT PARITY BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 START BIT TX NEXT DATA START BIT -TXRDY T28d X552-TX-2 -IOW T27d BYTE #1 Active Active Transmitter ready Transmitter not ready D0-D7
Rev. 1.00P Transmit ready timing in FIFO mode STOP BIT PARITY BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 -IOW D0-D7 -TXRDY BYTE #128 T28d T27d X552-TX-3 FIFO Full Active
Rev. 1.00P UART Frame Data Bits Start Stop 000 0 011 1 11TX IRTX Bit Time 1/2 Bit Time 3/16 Bit Time UART Frame Data Bits Start Stop 000 0 011 1 11RX IRRX Bit Time 0-1 16x clock delay X650-IR-1 Infrared transmit timing Infrared receive timing
D e
40 LEAD PLASTIC DUAL-IN-LINE
(600 MIL PDIP) Rev. 1.00 SYMBOL MIN MAX MIN MAX A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.980 2.095 50.29 53.21 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e 0.100 BSC 2.54 BSC eA 0.600 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 a 0° 15° 0° 15° INCHES MILLIMETERS E A L Seating Plane a B C Note: The control dimension is the inch column eB eA
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC) Rev. 1.00 D A D D1 A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS B e Seating Plane 2 44 Note: The control dimension is the inch column 45° x H2 45° x H1 C R
48 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.0 mm, TQFP) Rev. 1.00 36 25 1 12 D DD1 B e a A Seating Plane A 0.039 0.047 1.00 1.20 A1 0.002 0.006 0.05 0.15 A2 0.037 0.041 0.95 1.05 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 a 0° 7° 0° 7° SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS Note: The control dimension is the millimeter column L C
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.