16962A

16962A HP | Alldatasheet

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Agilent 16962A 2 GHz State, 2/4/8 GHz Timing Logic Analyzer Module Data Sheet Features:

• State analysis up to 2 GHz addresses all DDR speeds Up to 125 ps (8 GHz) timing analysis captures up to 400 M of system activity at high resolution 68-channel cards combined in up to 5-card sets provide 340 channels on a single time base and trigger Selectable memory depths up to 100 M enables you to purchase the memory depth you need now and upgrade later as your needs evolve

analyzer module delivers the performance required for the latest high-speed standards like DDR3 and QuickPath Interconnect (QPI). In addition to covering emerging standards, the 16962A provides conventional state and timing measurements on single- ended or differential signals at rates up to 2 GHz. The 100 M samples of memory ensure you capture enough system activity to troubleshoot complex systems. Optimized for comprehensive DDR memory analysis The 16962A logic analysis module with 2.0 GT/s state speed and 2 GHz trigger sequencer speed provides full capability to reliably trigger and capture all DDR activity, including DDR3 1600. When used with a full suite of DDR probing solutions (Interposer, BGA, SODIMM, mid-bus) and compliance/performance analysis software, you obtain full test capability for system integration in the memory industry. Automate measurement setup and quickly gain diagnostic clues Quickly get up and running by automating your measurement setup process. In addition, the logic analyzer’s sampling position and threshold voltage settings are automatically determined so that data on high-speed buses is captured with the highest accuracy. Identify problem signals over hundreds of channels simultaneously As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement in the design validation process. Eye scan lets you acquire signal integrity information on all the buses in your design, under a wide variety of operating conditions, in a matter of minutes. Identify problem signals quickly for further investigation with an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple signals or buses.

16962A Key Specifi cations and Characteristics Agilent model number 16962A Channels per card (unused clock and clock ready bits can be used as data bits) 68 channels State: 64 data + 2 clock + 2 clock ready Timing: 68 data channels Maximum channels on single time base and trigger 340 channels Number of mainframe slots per card 1 Number of independent analyzers per module set 1 Timing mode – conventional Maximum sample rate (conventional timing) 125 ps (8 GHz): quarter channel mode 250 ps (4 GHz): half channel mode 500 ps (2 GHz): full channel mode Maximum memory depth Option 100 Option 064 Option 032 Option 016 Option 004 (included standard) (4x memory option) 400 M 256 M 128 M 64 M 16 M (2x memory option) 200 M 128 M 64 M 32 M 8 M 100 M 64 M 32 M 16 M 4 M Channels per multi-card module 1-card module 2-card module 3-card module 4-card module 5-card module 102 136 170 136 204 272 340 Pod usage 1 pod from each pod pair, user selectable 1 pod from each pod pair, user selectable All pods Channel usage Even bits of selected pods All channels of selected pods All channels Probe connection E5386A adapter recommended between probe and logic analyzer cable for selected pods Direct to logic analyzer cable for selected pods Direct to logic analyzer cable Timing mode – transitional Transitional timing 2 GHz: full channel mode

16962A Key Specifi cations and Characteristics Agilent model number 16962A State modes Maximum state speed1 2 GHz (single edge, 2 GHz clock) Maximum state data rate*,1 2 Gb/s (DDR, 1 GHz clock) Channels per multi-card module 1-card module 2-card module 3-card module 4-card module 5-card module State 64 data + 2 clocks + 2 clock ready 132 data + 2 clocks + 2 clock ready 200 data + 2 clocks + 2 clock ready 268 data + 2 clocks + 2 clock ready 336 data + 2 clocks + 2 clock ready Maximum memory depth Option 100 Option 064 Option 032 Option 016 Option 004 (included standard) 100 M 64 M 32 M 16 M 4 M Minimum time between active clock edges 500 ps Minimum state clock pulse width Single edge Multiple edge 250 ps 500 ps Number of clocks 2 (on odd pods), 1 can be selected Number of clock ready inputs 2 (on even pods), 1 can be selected Time tag resolution 25 ps Maximum time count between stored states 83.4 days Automated threshold/sample position, Simultaneous eye diagrams, all channels Yes Maximum memory depth³ Option 100 Option 064 Option 032 Option 016 Option 004 (included standard) State 100 M 64 M 32 M 16 M 4 M Timing (full/half/quarter ch)

100 M/200 M/400 M

64 M/128 M/256 M

32 M/64 M/128 M

16 M/32 M/64 M

4 M/8 M/ 16 M

Memory depth upgrade after purchase Available via E5887A Items marked with an asterisk (*) are specifi cations. All others are characteristics. “Typical” represents the average or median value of the parameter based on measurements from a signifi cant number of units. Requires continuous, periodic clock. Tested with input signal Vih = 1.125 V, Vil = 0.875 V, threshold = 1.0 V, tr/tf = 180 ps ±30 ps (10%, 90%) Store qualifi cation consumes 1 sample per store qualifi ed block.

16962A Key Specifi cations and Characteristics Agilent model number 16962A Trigger characteristics Maximum trigger sequencer speed 2 GHz (500 ps) Trigger resources – create a trigger from any 8 of the listed resources (7 in transitional timing) 16 pattern detectors evaluated as =, !=, >, ≥, <, ≤, in range, not in range 8 range detectors 4 to 8 burst detectors 4 edge detectors in timing, 3 in transitional timing 4 fl ags 1 timer in timing or transitional timing 1 arm in Trigger resource combinations Arbitrary Boolean combinations Trigger actions Goto Trigger and fi ll memory Trigger and Goto Trigger, send e-mail, and fi ll memory Store qualifi cation actions (available in state mode) Store sample Don’t store sample Turn on default storage Turn off default storage Store sample and turn on default storage Don’t store sample and turn off default storage Timer actions Start from reset Stop and reset Pause Resume Flag actions Set Clear Pulse set Pulse clear Trigger sequence level branching Arbitrary 4-way if/then/else Trigger position Start, center, end, or user-defi ned Maximum pattern width 128 bit – single label 340 bit – AND of multiple labels across multi-card set Other Supported signal types Single-ended and differential Probe compatibility 90-pin cable connector Voltage threshold –3 V to 5 V in 10 mv increments Threshold accuracy ±(30 mV + 1% of setting) Threshold setting granularity By channel

16962A Key Specifi cations and Characteristics 16962A Logic analyzer mainframe compatibility 16902B 6-slot modular logic analysis system with software revision 3.82 or greater Power requirements All necessary power is supplied by the backplane connector of the logic analyzer mainframe. Environmental characteristics Indoor use only Operating environment Temperature 0 °C to 40 °C (+32 °F to 104 °F). Reliability is enhanced when operating within the range Humidity 0 to 80% relative humidity at 40 °C (+104 °F). Reliability is enhanced when operating within the range 20% to 80% non-condensing Altitude 0 to 3,000 m (10,000 ft) Vibration Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 0.2 g rms Non-operating environment Temperature –40 to +75 °C (–40 to +167 °F). Protect the instrument from temperature extremes which cause condensation on the instrument. Humidity 0 to 90% at 65 °C (149 °F) Altitude 0 to 15,300 m (50,000 ft) Vibration (in shipping carton) Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 2.41 g rms; and swept sine resonant search, 5 to 500 Hz, 0.50 g (0-peak), 5 minute resonant dwell at 4 resonances per axis.

Ordering Information

16962A 2/4/8 GHz timing, 2 GHz state logic analyzer Base confi guration: 4 M acquisition memory included standard Option 016 – increase acquisition memory to 16 M Option 032 – increase acquisition memory to 32 M Option 064 – increase acquisition memory to 64 M Option 100 – increase acquisition memory to 100 M E5887A after-purchase, memory upgrade for 16962A logic analyzer modules Upgrade your 16962A logic analyzer module by “turning on” additional memory depth when you need more. Purchase the capability you need now, then upgrade as your needs evolve. Option 016 – increase acquisition memory to 16 M Option 032 – increase acquisition memory to 32 M Option 064 – increase acquisition memory to 64 M Option 100 – increase acquisition memory to 100 M DDR memory probes and analysis software Product Description DDR2 BGA probes W2631A W2632A W2633A W2634A DDR2 x16 BGA command and data probe for logic analyzer and oscilloscope – kit of 4 probes DDR2 x16 BGA data probe for logic analyzer and oscilloscope – kit of 4 probes DDR2 x8 BGA command and data probe for logic analyzer and oscilloscope – kit of 4 probes DDR2 x8 BGA data probe for logic analyzer and oscilloscope – kit of 4 probes ZIF probes (used to connect W2630A Series DD2 BGA probes to 90-pin logic analyzer cables) E5384A E5876A E5877A 46-ch single-ended ZIF probe for x8/x16 DRAM BGA probe connection to 90-pin logic analyzer cable 46-ch single-ended ZIF probe for x16 DRAM data only BGA probe connection to 90-pin logic analyzer cable 46-ch single-ended ZIF probe for 2 x8 DRAMs data only BGA probe connection to 90-pin logic analyzer cable DDR3 BGA probes W3631A-001 W3631A-002 W3631A-004 W3633A-001 W3633A-002 W3633A-004 Quantity of 1 – DDR3 x16 BGA command and data probe for logic analyzers and oscilloscopes Quantity of 2 – DDR3 x16 BGA command and data probe for logic analyzers and oscilloscopes Quantity of 4 – DDR3 x16 BGA command and data probe for logic analyzers and oscilloscopes Quantity of 1 – DDR3 x4/x8 BGA command and data probe for logic analyzers and oscilloscopes Quantity of 2 – DDR3 x4/x8 BGA command and data probe for logic analyzers and oscilloscopes Quantity of 4 – DDR3 x4/x8 BGA command and data probe for logic analyzers and oscilloscopes ZIF probes (used to connect W3630A Series DD3 BGA probes to 90-pin logic analyzer cables) E5845A E5847A 46-ch SE ZIF probe for DDR3 x16 DRAM BGA probe connection to 90-pin logic analyzer cable 46-ch SE ZIF probe for DDR3 x4/x8 DRAM BGA probe connection to 90-pin logic analyzer cable DDR3 DIMM interposer N4835A DDR3 advanced slot interposer probe - enhanced DDR2/3 analysis software B4621A B4622A DDR2/3 bus decoder DDR2/3 protocol compliance and analysis tool

General purpose logic analyzer probes Probes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic analyzer and device under test. When operating in 8 GHz quarter channel timing mode, the E5386A adapter enables easy signal connection and reduces the number of probes and connectors used in quarter channel timing mode. The adapter maps the appropriate logic analyzer channels to all pins of the probe to which it is connected. The following probes are compatible with the 90-pin cable of the 16962A logic analyzer module. Probe type Model number Channels Maximum data rate Supported signal types Soft touch connectorless probes E5406A (Pro series) 34 (32 data, 2 clock) > 2.5 Gb/s Single-ended data, differential or single-ended clock E5402A (Low profi le) 34 (32 data, 2 clock) > 2.5 Gb/s Single-ended data, differential or single-ended clock E5390A (Classic) 34 (32 data, 2 clock) > 2.5 Gb/s Single-ended data, differential or single-ended clock E5398A (Half-size) 17 (16 data, 1 clock) > 2.5 Gb/s Single-ended data, differential or single-ended clock E5405A (Pro series) 17 (16 data, 1 clock) > 2.5 Gb/s Differential or single-ended data, differential or single-ended clock E5387A (Classic) 17 (16 data, 1 clock) > 2.5 Gb/s Differential or single-ended data, differential or single-ended clock Samtec connector probes E5378A 34 (32 data, 2 clock) 1.5 Gb/s Single-ended data, Differential or single-ended clock E5379A 17 (16 data, 1 clock) 1.5 Gb/s Differential or single-ended data, Differential or single-ended clock Mictor connector probe E5380A 34 (32 data, 2 clock) 600 Mb/s Single-ended data, Differential or single-ended clock General purpose fl ying lead probes E5382A 17 (16 data, 1 clock) 1.5 Gb/s Single-ended data, Differential or single-ended clock E5381A 17 (16 data, 1 clock) 1.5 Gb/s Differential or single-ended data, Differential or single-ended clock E5386A adapter and 16962A module quantity requirements Probe models Number of channels Quantity of E5386A Quantity of 16962A E5379A, E5387A, E5398A, E5405A 17 1 1 E5378A, E5380A, E5390A, E5402A, E5406A 34 2 2 E5384A, E5826A, E5827A, E5845A, E5847A 46 3 3

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