STD15N50M2AG STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 16
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package information
- 4.1 DPAK (TO-252) type A2 package information
- 4.2 DPAK (TO-252) packing information
- 5 Revision history
Features
Order code VDS RDS(on) max. ID PTOT STD15N50M2AG 500 V 0.380 Ω 10 A 85 W Designed for automotive applications and AEC-Q101 qualified Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packing STD15N50M2AG 15N50M2 DPAK Tape and reel
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ±30 V ID Drain current (continuous) at Tcase = 25 °C 10 A Drain current (continuous) at Tcase = 100 °C 7 IDM(1) Drain current (pulsed) 40 A PTOT Total dissipation at Tcase = 25 °C 85 W dv/dt(2) Peak diode recovery voltage slope 10 V/ns dv/dt(3) MOSFET dv/dt ruggedness 25 Tstg Storage temperature range -55 to 150 °C Tj Operating junction temperature range Notes: (1) Pulse width is limited by safe operating area. (2) ISD ≤ 10 A, di/dt=800 A/μs; VDS peak < V(BR)DSS,VDD = 80% V(BR)DSS (3) VDS ≤ 400 V. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max. 1.47 °C/W Rthj-pcb(1) Thermal resistance junction-pcb max. 50 Notes: (1)When mounted on a 1 inch² FR-4, 2 Oz copper board Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR(1) Avalanche current, repetitive or not repetitive 3.5 A EAS(2) Single pulse avalanche energy 200 mJ Notes: (1) pulse width limited by Tjmax (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V.
2 Electrical characteristics
(Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 500 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 500 V µA VGS = 0 V, VDS = 500 V, Tcase = 125 °C 100 IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 5 A 0.336 0.380 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 530 - pF Coss Output capacitance - 33 - Crss Reverse transfer capacitance - 0.8 - Coss eq.(1) Equivalent output capacitance VDS = 0 to 400 V, VGS = 0 V - 125 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6.9 - Ω Qg Total gate charge VDD = 400 V, ID = 9 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 13 - nC Qgs Gate-source charge - 2.8 - Qgd Gate-drain charge - 5.1 - Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 250 V, ID = 4.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 10 - ns tr Rise time - 3.2 - td(off) Turn-off delay time - 84 - tf Fall time - 8.8 -
Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 10 A ISDM(1) Source-drain current (pulsed) 40 A VSD(2) Forward on voltage VGS = 0 V, ISD = 10 A - 1.6 V trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 230 ns Qrr Reverse recovery charge - 2 µC IRRM Reverse recovery current - 17.4 A trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 310 ns Qrr Reverse recovery charge - 2.7 µC IRRM Reverse recovery current - 17.5 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ±250 µA, ID = 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
Test circuits STD15N50M2AG
3 Test circuits
Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 DPAK (TO-252) type A2 package information
Figure 20: DPAK (TO-252) type A2 package outline 0068772_type-A2_rev21
Table 10: DPAK (TO-252) type A2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 5.10 5.25 E 6.40 6.60 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 1.00 R 0.20 V2 0°
Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)
4.2 DPAK (TO-252) packing information
Figure 22: DPAK (TO-252) tape outline
Figure 23: DPAK (TO-252) reel outline Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm Dim. mm Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3
5 Revision history
Table 12: Document revision history Date Revision Changes 13-Apr-2015 1 First release. 07-May-2016 2 Minor text edits Document status promoted to production data Updated Section 1: "Electrical ratings" Updated Section 2: "Electrical characteristics" Updated Section 2.1: "Electrical characteristics (curves)" Updated Section 4.1: "DPAK (TO-252) type A2 package information"