EBK-GS2984-00 SEMTECH | Alldatasheet
Document overview
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- PDF pages: 20
Technical content
Datasheet sections
- 1.1 GS2984 Pin Assignment
- 1.2 GS2984 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 DC Electrical Characteristics
- 2.3 AC Electrical Characteristics
- 2.4 Typical Performance Curves
- 4.1 Serial Digital Inputs
- 4.2 Cable Equalization
- 4.3 Serial Digital Outputs
- 4.4 Programmable Squelch Adjust (SQ_ADJ)
- 4.5 Mute and Carrier Detect
- 4.6 GAIN_SEL
- 4.7 CMSET Operation
- 4.8 Output Rise/Fall Times
- 5.1 High Gain Adaptive Cable Equalizers
- 5.2 PCB Layout
- 5.3 Typical Application Circuit
- 6.1 Package Dimensions
- 6.2 Packaging Data
- 6.3 Recommended PCB Footprint
- 6.4 Marking Diagram
- 6.5 Solder Reflow Profiles
- 6.6 Ordering Information
1 of 20GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 GS2984 Adaptive Cable Equalizer www.gennum.com Key Features
- SMPTE 424M, SMPTE 292M and SMPTE 259M compliant
- Automatic cable equalization
- Multi-standard operation from 143Mb/s to 2.97Gb/s
- Performance optimized for 270Mb/s, 1.485Gb/s and 2.97Gb/s. T ypical equalized length of Belden 1694A cable: 140m at 2.97Gb/s 200m at 1.485Gb/s 400m at 270Mb/s
- Supports DVB-ASI at 270Mb/s
- Manual bypass (useful for low data rates with slow rise/fall times)
- Programmable carrier detect with squelch threshold adjustment
- Differential outputs support DC coupling to 3.3V and 2.5V CML logic
- 0/6 dB gain boost selection pin
- Standard EIA/JEDEC logic control and status signal levels
- Single 3.3V power supply operation
- 195mW power consumption (typical)
- Wide temperature range of -40ºC to +85ºC
- Small footprint QFN package (4mm x 4mm) Drop-in compatible with the GS2974
- Pb-free and RoHS compliant
Applications
- SMPTE 424M, SMPTE 292M and SMPTE 259M coaxial cable serial digital interfaces
Description
The GS2984 is a high-speed BiCMOS integrated circuit designed to equalize and restore signals received over 75Ω coaxial cable. The device is designed to support SMPTE 424M, SMPTE292M and SMPTE 259M, and is optimized for performance at 270Mb/s, 1.485Gb/s and 2.97Gb/s. The GS2984 features DC restoration to compensate for the DC content of SMPTE pathological test patterns. The Carrier Detect output pin (CD ) indicates whether a valid input signal has been detected. It can be connected directly to the MUTE pin to mute the output on loss of carrier. A voltage programmable threshold, which can be changed via the SQ_ADJ pin, forces CD high when the input signal amplitude falls below the threshold. This allows the GS2984 to distinguish between low-amplitude SDI signals and noise at the input of the device. The equalizing and DC restore stages are disengaged when the BYPASS pin is HIGH. No equalization occurs in Bypass mode. The GS2984 includes a gain selection pin (GAIN_SEL) which, when tied HIGH, compensates for 6dB flat attenuation. The differential outputs can be DC-coupled to Gennum 3.3V cable drivers and reclockers and to industry-standard 3.3V and 2.5V CML logic using the CMSET pin. The GS2984 is footprint and drop-in compatible with existing GS2974 designs, with no additional application changes required. The device is available in a 16-pin, 4mm x 4mm QFN package. Power consumption of the GS2984 is typically 195mW. The GS2984 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant.
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 2 of 20 GS2984 Functional Block Diagram
Revision History
Version ECR PCN Date Changes and/or Modifications 3 153913 54547 March 2010 Changed ESD rating from 6kV to 5kV in Section 2.1 Absolute Maximum Ratings. 2 152311 – July 2009 Converted to Data Sheet. 1 152027 – June 2009 Removed ‘Proprietary & Confidential’ from footer. Updated 6.4 Marking Diagram. 0 151621 – April 2009 Converted to Preliminary Data Sheet. Added sections 2.4 Typical Performance Curves and 4.8 Output Rise/Fall Times. Updates to section 2. Electrical Characteristics. B 151182 – January 2009 Updates. A 150385 – September 2008 New document. Equalizer Output AGC SDI MUTE SDO BYPASS CD SDI SDO AGCAGC CMSET GAIN_SEL SQ_ADJ Squelch Adjust Carrier Detect Mute DC Restore
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 4 of 20 1. Pin Out
1.1 GS2984 Pin Assignment
Figure 1-1: GS2984 Pin Out
1.2 GS2984 Pin Descriptions
VEE_A GAIN_SEL Ground Pad (bottom of package) AGC BYPASS SQ_ADJ VEE_D CMSET VCC_A CD MUTE VCC_D GS2984 16-pin QFN (top view) AGC Table 1-1: GS2984 Pin Descriptions Pin Number Name Timing Type Description 1 VEE_A Analog Power Most negative power supply for analog circuitry. Connect to GND. 2, 3 SDI, SDI Analog Input Serial digital differential input.
4 GAIN_SEL Not
Input CONTROL SI GNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V tolerant) Controls flat band gain. See Section 4.6. (Internal pull-down). 5, 6 A GC, AGC Analog – External A GC capacitor. Connect pin 5 and pin 6 together as shown in the Typical Application Circuit on page 16. 7B Y P A S S N o t Synchronous Input Forces the E qualizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. (Internal pull-down).
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 5 of 20 8 SQ_ADJ Analog Input S quelch Adjust. Adjusts the approximate amount of cable equalized before CD goes 9C M S E T N o t Synchronous Input CONTROL SI GNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V Tolerant) Controls output common mode level. (Internal pull-down). See Section 4.7. 10, 11 SDO , SDO Analog Output E qualized serial digital differential output.
12 VEE_D Analog Power Most negative power supply for the digital circuitry and output
buffer. Connect to GND. 13 VCC_D Analog Power Most positive power supply for the digital I/O pins of the device. Connect to +3.3V DC.
14 MUTE Not
Input CONTROL SI GNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V Tolerant) Controls output behaviour on SDO and SDO. (Internal pull-down). See Section 4.5.
15 CD Not
Output STATUS SI GNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Indicates the presence of an input signal. See Section 4.5. 16 VCC_A Analog Power Most positive power supply for the analog circuitry of the device. Connect to +3.3V DC. – Center Pad – Power Internally bonded to VEE_A. Table 1-1: GS2984 Pin Descriptions (Continued) Pin Number Name Timing Type Description
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 6 of 20 2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 DC Electrical Characteristics
Supply Voltage -0.5V to +3.6V DC Input ESD Voltage (HBM) 5kV Storage Temperature Range -50°C < T s < 125°C Input Voltage Range (any input) -0.3 to (V CC +0.3)V Operating Temperature Range -20°C to +85°C Functional Temperature Range -40°C to +85°C Solder Reflow Temperature 260°C Table 2-1: DC Electrical Characteristics VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Notes Supply Voltage V CC – 3.135 3.3 3.465 V – Power Consumption P D TA = 25°C – 195 250 mW – Supply Current I s TA = 25°C – 59 – mA – Output Common Mode Voltage VCMOUT TA = 25°C – V CMSET - ΔVSDO/2 – V 1 Input Common Mode Voltage V CMIN TA = 25°C – 1.8 – V – SQ_ADJ DC Voltage (to mute signal) SQ_ADJ Range – T A = 25°C – 0.9 – V – CD Output Voltage V CD(OH) Carrier not present 2.4 – – V – VCD(OL) Carrier present – – 0.4 V – Mute Input Voltage Required to Force Outputs to Mute VMute Min to Mute 2.0 – – V – Mute Input Voltage Required to Force Outputs Active VMute Max to Activate –– 0 . 8 V – NOTES: 1. V CMSET is the voltage determined by the setting of the CM_SET pin. It will be either 3.3V or 2.5V
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 7 of 20
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Notes Serial input data rate DR SDO – 143 – 2970 Mb/s – Input Voltage Swing ΔVSDI TA =25°C, differential, 270Mb/s and 1.485Gb/s 720 800 950 mV p-p 1 TA =25°C, differential, 2.97Gb/s 720 800 880 mV p-p 1 Output Voltage Swing ΔVSDO 100Ω load, TA =25°C, differential 680 800 900 mV p-p – Output Jitter of Various Cable Lengths and Data Rates –2 . 9 7 Gb/s Belden 1694A: 0-120m – – 0.25 UI 2, 5 –2 . 9 7 Gb/s Belden 1694A: 120-140m – 0.3 – UI 3, 5 – 1.485 Gb/s Belden 1694A: 0-160m – – 0.25 UI 2, 5 – 1.485 Gb/s Belden 1694A: 160-200m – 0.2 – UI 3, 5 – 270Mb/s Belden 1694A: 0-400m –– 0 . 2 U I 2 , 5 Output Rise/Fall time – 2.97 Gb/s & 1.485Gb/s 20% - 80% 35 65 90 ps – – 270Mb/s (see Section 4.8) Mismatch in rise/fall time – – – – 30 ps – Duty cycle distortion – – – – 30 ps – Input Return Loss – – 15 21 – dB 4 Input Resistance – single ended – 1.9 – k Ω – Input Capacitance – single ended – 1.3 – pF – Output Resistance – single ended – 50 – Ω – NOTES: 1. 0m cable length. 2. All parts are production tested. In order to guarantee jitter over the full range of specification (V CC = 3.3V ±5%, TA = -20°C to +85°C, and 720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used. 3. Based on characterization data using the recommended applications circuit, at VCC = 3.3V, TA = 25°C and 800mV launch swing from the SDI cable driver. 4. Tested on a 2984 board from 5MHz to 3GHz. 5. CM_SET = 0, GAIN_SEL = 0
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 8 of 20
2.4 Typical Performance Curves
VCC=3.3V , room temperature, 800mV launch swing Figure 2-1: Jitter vs. Cable Length (270 Mb/s) Figure 2-2: Jitter vs. Cable Length (1485 Mb/s) Figure 2-3: Jitter vs. Cable Length (2970 Mb/s) 200 400 600Jitter (ps) 0 100 200 300 400 Cable Length (m) 100Jitter (ps) 0 50 100 150 Cable Length (m) 80Jitter (ps) 0 25 50 75 100 125 Cable Length (m)
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 10 of 20 4. Detailed Description The GS2984 is a high-speed BiCMOS IC designed to equalize serial digital signals. The GS2984 can equalize 3Gb/s, HD and SD serial digital signals, and will typically equalize 140m of Belden 1694A cable at 2.97Gb/s, 200m at 1.485Gb/s and 400m at 270Mb/s.The GS2984 is powered from a single +3.3V power supply and consumes approximately 195mW of power.
4.1 Serial Digital Inputs
The Serial Data Signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V. Figure 3-6: CM_SET Figure 3-7: GAIN_SEL VCC RCM_SET RR LL OUT OUT IN IN I VCC GAIN_SEL
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 11 of 20
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage, whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling.
4.3 Serial Digital Outputs
The digital output signals have a nominal voltage of 800mVpp differential, or 400mVpp single-ended when terminated with 50Ω as shown in Figure 4-1. Figure 4-1: Typical Output Voltage Levels (for 3.3V Common Mode) 50 50 SDO SDO +200mV -200mV VCM = 2.9V typical +200mV -200mV VCM = 2.9V typical
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 12 of 20
4.4 Programmable Squelch Adjust (SQ_ADJ)
The GS2984 incorporates a programmable Squelch Adjust (SQ_ADJ) threshold. This feature can be useful in applications where there are multiple input channels using the GS2984 and the maximum gain can be limited to avoid crosstalk. The SQ_ADJ pin acts to change the threshold of the Carrier Detect (CD) pin, through voltage level variances. When the input signal drops below a certain threshold, the CD pin will be driven high, indicating that there is not a valid input signal. In order to enable automatic muting of the output of the GS2984, the CD pin should be connected directly to the MUTE pin. In applications where programmable squelch adjust is not required, the SQ_ADJ pin may be left unconnected. Figure 4-2 shows the relationship between the SQ_ADJ voltage and cable length at which CD will assert or deassert. This feature has been designed for use in applications such as routers, where signal crosstalk and circuit noise cause the Equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem, since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. Figure 4-2: SQ_ADJ vs. Cable Length (VCC=3.3V, room temperature, 800mV launch swing)
4.5 Mute and Carrier Detect
The GS2984 includes a MUTE input pin that allows the application interface to mute the Serial Digital Output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In this case, the outputs will mute regardless of the setting of the BYPASS pin. A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of the GS2984. When CD is LOW, the device has detected a valid input on SDI and SDI. When CD is HIGH, the device has not detected a valid input. NOTE 1: CD will only detect loss of carrier for data rates greater than 19Mb/s. The CD output pin may be connected directly to the MUTE input pin to enable automatic muting of the GS2984 when no valid input signal has been detected. NOTE 2: If the maximum cable length is exceeded (set by the SQ_ADJ pin) and the device is not in Bypass mode, the CD pin will not be driven low, even if a carrier is present. SQ_ADJ (V) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 Cable Length (m) 0 50 100 150 200 250 300 350 400 450
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 13 of 20
4.6 GAIN_SEL
The GS2984 has an option of compensating for 6dB of flat attenuation in applications where there has been some type of attenuation prior to the equalizer.
4.7 CMSET Operation
The GS2984 has a selectable output common mode level. This is useful when interfacing to chips that can accept 2.5V input common mode levels. In these cases, AC coupling can be avoided by selecting the correct output common mode. NOTE: See Section 2.2 for Output Common Mode Voltage specification. Table 4-1: Mute Input Table Mute Function
0 SDO and SDO operate normally
1 SDO and SDO are forced to a steady
state (either high or low) Table 4-2: CD Output Table CD Input Status
0 Valid Input on SDI, SDI pins
1 Input is not valid
Table 4-3: GAIN_SEL Input Table GAIN_SEL Function
0 No flat band gain is applied
1 6dB of flat attenuation will be compensated by the equalizer.Table 4-4: CMSET Output Table CMSET Output Common Mode Voltage Level
0 The output common mode will be
compatible with 3.3V CML
1 The output common mode will be
compatible with 2.5V CML
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 14 of 20
4.8 Output Rise/Fall Times
Figure 4-3: Typical Rise/Fall time for 270Mb/s data rate (VCC=3.3V, room temperature, 800mV launch swing) The GS2984 was designed to limit bandwidth as cable length is increased. During normal 3G (2.97Gb/s), HD (1.485Gb/s), and SD (270Mb/s) operation, the impact of this is minimal on rise and fall time over the operating range from 0-200m. Above 200m, this bandwidth limitation becomes more significant, and reduction in rise and fall time is observed. This means that for SD (270Mb/s) operation at cable lengths greater than 200m, rise and fall times slow as shown in Figure 4-3 above. This is beneficial because at 270Mb/s, one unit interval is equal to 3.7ns, therefore rise and fall times less than 100ps are not required, and slower rise and fall times actually help to reduce EMI. 200Rise/Fall Time (ps) 0 100 200 300 400 Cable Length (m)
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 15 of 20 5. Application Information
5.1 High Gain Adaptive Cable Equalizers
The GS2984 is Gennum's latest multi-rate adaptive cable equalizer. In order to continue to extend the cable length that an equalizer will remain operational over, it is necessary to have high gain in the equalizer. A video cable equalizer must provide wide band gain over a range of frequencies in order to accommodate the range of data rates and signal patterns that are present in a SMPTE compliant serial video stream. The GS2984 has an increase in gain over the GS2974A at critical HD and 3Gbps frequencies, and because of this, the GS2984 may be sensitive to signals at the input that the GS2974A will not be sensitive to. Small levels of signal or noise present at the input pins of the Equalizer may cause chatter at the output. In order to prevent this from happening, particular attention must be paid to board layout.
5.2 PCB Layout
Special attention must be paid to component layout when designing Serial Digital Interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance:
- PCB trace width for 3Gb/s rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance.
- The PCB ground plane is removed under the GS2984 input components to minimize parasitic capacitance.
- The PCB ground plane is removed under the GS2984 output components to minimize parasitic capacitance.
- High speed traces are curved to minimize impedance changes.
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 16 of 20
5.3 Typical Application Circuit
Figure 5-1: GS2984 Typical Application Circuit GS2984 SDI CD SDI VEE_D MUTE VCC_D AGC BYPASS VEE_A NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. * Value dependent on layout GAIN_SEL AGC VCC_A SDO SDO CMSET 10n 10n SDO 4u7 4u7 SDO CD MUTE VCC BYPASS SQ_ADJ470n 6.2n* SDI 37R4 VCC 5 6 1415 470n GAIN_SEL CMSET SQ_ADJ
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 17 of 20 6. Package & Ordering Information
6.1 Package Dimensions
6.2 Packaging Data
4.00+/-0.05 B 4.00+/-0.05 0.15 0.15 C C 0.10 C 16X 0.08 C SEATING PLANE 0.85+/-0.05 0.00-0.05 0.65/2 0.65 DETAIL B SCALE:NTS DATUM A OR B TERMINAL TIP
0.20 REF
0.65 16X 0.35+/-0.05 0.10 0.05 C A BC DATUM A 2.76+/-0.10 0.40+/-0.05 2.76+/-0.10DETAIL B CENTER TAB PIN 1 AREA A C PIN #1 IDENTIFICATION Φ0.4500 Parameter Value Package Type 4mm x 4mm 16-pin QFN Package Drawing Reference JEDEC M0220 Moisture Sensitivity Level 3 Junction to Case Thermal Resistance, θ j-c 31.0°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 43.8°C/W Psi, ψ 11.0°C/W Pb-free and RoHS compliant Yes
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 18 of 20
6.3 Recommended PCB Footprint
The Center Pad should be connected to the most negative power supply plane for analog circuitry in the device (VEE_A) by a minimum of 5 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations.
6.4 Marking Diagram
0.35 0.55 2.76 3.70 2.763.70 NOTE: All dimensions are in millimeters. 0.65 Center Pad GS2984 XXXXE3 YYWW Pin 1 ID XXXX - Last 4 digits (excluding decimal) of SAP Batch Assembly (FIN) as listed on Packing Slip. E3 - Pb-free & Green indicator YYWW - Date Code
GS2984 Adaptive Cable Equalizer Data Sheet 50985 - 3 March 2010 19 of 20
6.5 Solder Reflow Profiles
The GS2984 is available in a Pb-free package. It is recommended that the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 6-1. Figure 6-1: Maximum Pb-free Solder Reflow Profile
6.6 Ordering Information
25° C 150° C 200° C 217° C 260°C 250° C Time Temperature 8 min. max 60-180 se c. max 60-150 se c. 20-40 se c. 3° C/se c max 6°C/se c max Part Number Package Temperature Range GS2984 GS2984-INE3 16-pin QFN -40°C to 85°C GS2984 GS2984-INTE3 16-pin QFN Tape & Reel (250pcs) -40°C to 85°C GS2984 GS2984-INTE3Z 16-pin QFN Tape & Reel (2500pcs) -40°C to 85°C
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