1500457 FREESCALE | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 87
Technical content
© 2006–2011 Freescale Semiconductor, Inc. All rights reserved. Freescale Semiconductor Technical Data The MPC8349EA PowerQUICC II Pro is a next generation PowerQUICC II integrated host processor. The MPC8349EA contains a processor core built on Power Architecture® technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual. To locate published errata or updates for this document, refer to the MPC8349EA product summary page on our website, as listed on the back cover of this document, or contact your local Freescale sales office. Document Number: MPC8349EAEC Rev. 13, 09/2011
Contents
- Ethernet: Three-Speed Ethernet, MII Management . 22 12. I MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications
2 Freescale Semiconductor
PowerQUICC II Pro Integrated Host Processor Hardware Specifications. silicon revision level determination.
1 Overview
Figure 1. MPC8349EA Block Diagram
- Embedded PowerPC e300 processor core; operates at up to 667 MHz — High-performance, superscalar processor core — Floating-point, integer, lo ad/store, system register, and branch processing units — 32-Kbyte instruction cach e, 32-Kbyte data cache — Lockable portion of L1 cache — Dynamic power management — Software-compatible with the other Freescale processor families that implement Power Architecture technology TSEC Coherent System Bus PCI1 10/100/1Gb MII, GMII, TBI, RTBI, RGMII SPI Serial IRQs ROM I2C I2C Interfaces TSEC DDR/DDR2 Memory Controller Local Bus Controller Programmable Interrupt Controller DUART e300 Core DMA Controller Serial Peripheral Interface 32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache Sequencer SEQ 64/32b PCI Controller PCI20/32b PCI Controller Security Engine Arbiter Bus Monitor USB Hi-Speed Host Device General Purpose I/O USB0 USB1 GPIO SDRAM DDR/DD DMA MII, GMII, TBI, RTBI, RGMII10/100/1Gb
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 3 Overview
- Double data rate, DDR1/DDR 2 SDRAM memory controller — Programmable timing support ing DDR1 and DDR2 SDRAM — 32- or 64-bit data interface, up to 400 MHz data rate — Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable — DRAM chip configurations from 64 Mbit s to 1 Gbit with ×8/×16 data ports — Full error checking and correction (ECC) support — Support for up to 16 simultaneous open pages (up to 32 pages for DDR2) — Contiguous or discontiguous memory mapping — Read-modify-write support — Sleep-mode support for SDRAM self refresh — Auto refresh — On-the-fly power management using CKE — Registered DIMM support — 2.5-V SSTL2 compatible I/O for DDR 1, 1.8-V SSTL2 compatible I/O for DDR2
- Dual three-speed (10/100/1000) Et hernet controllers (TSECs) — Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™, 802.3ac™ standards — Ethernet physical interfaces: – 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex – 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex — Buffer descriptors are backward-compa tible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — Internal 2-Kbyte transmit and 2-K byte receive FIFOs per TSEC module — MII management interface for control and status — Programmable CRC ge neration and checking
- Dual PCI interfaces — Designed to comply with PCI Specification Revision 2.3 — Data bus width options: – Dual 32-bit data PCI interfac es operating at up to 66 MHz – Single 64-bit data PCI interface operating at up to 66 MHz — PCI 3.3-V compatible — PCI host bridge capa bilities on both interfaces — PCI agent mode on PCI1 interface — PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Posting of processor-to-PCI and PCI-to-memory writes
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
4 Freescale Semiconductor
— On-chip arbitration supporting five masters on PCI1, three masters on PCI2 — Accesses to all PCI address spaces — Parity supported — Selectable hardware-enforced coherency — Address translation units for addres s mapping between host and peripheral — Dual address cycle for target — Internal configuration regi sters accessible from PCI
- Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): — Public key execution unit (PKEU) : – RSA and Diffie-Hellman algorithms – Programmable field size up to 2048 bits – Elliptic curve cryptography – F2m and F(p) modes – Programmable field size up to 511 bits — Data encryption standard (DES) execution unit (DEU) – DES and 3DES algorithms – Two key (K1, K2) or three key (K1, K2, K3) for 3DES – ECB and CBC modes for both DES and 3DES — Advanced encryption standard unit (AESU) – Implements the Rijndael symmetric-key cipher – Key lengths of 128, 192, and 256 bits – ECB, CBC, CCM, and counter (CTR) modes — XOR parity generation acceler ator for RAID applications — ARC four execution unit (AFEU) – Stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — Message digest execution unit (MDEU) – SHA with 160-, 224-, or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm — Random number generator (RNG) — Four crypto-channels, each supporting multi-command descriptor chains – Static and/or dynamic assignm ent of crypto-execution units through an integrated controller – Buffer size of 256 bytes for each execution uni t, with flow control for large data sizes
- Universal serial bus (USB) dual role controller — USB on-the-go mode with bot h device and host functionality
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 5 Overview — Complies with USB specification Rev. 2.0 — Can operate as a stand-alone USB device – One upstream facing port – Six programmable USB endpoints — Can operate as a stand-alone USB host controller – USB root hub with one downstream-facing port – Enhanced host controller in terface (EHCI) compatible – High-speed (480 Mbps), full -speed (12 Mbps), and low-speed (1.5 Mbps) operations — External PHY with UTMI, serial a nd UTMI+ low-pin interface (ULPI)
- Universal serial bus (USB ) multi-port host controller — Can operate as a stand-alone USB host controller – USB root hub with one or two downstream-facing ports – Enhanced host controller in terface (EHCI) compatible – Complies with USB Specification Rev. 2.0 — High-speed (480 Mbps), full -speed (12 Mbps), and low-speed (1.5 Mbps) operations — Direct connection to a high-speed device without an external hub — External PHY with serial and low-pin count (ULPI) interfaces
- Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 133 MHz — Eight chip selects for eight external slaves — Up to eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controll ed by an on-chip memory controller — Three protocol engines on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user-programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with conf igurable bus width (8-, 16-, or 32-bit)
- Programmable interrupt controller (PIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for 8 external and 35 inte rnal discrete interrupt sources — Support for 1 external (optional) and 7 in ternal machine checkstop interrupt sources — Programmable highest priority request — Four groups of interrupts with programmable priority — External and internal interrupt s directed to host processor — Redirects interrupts to external INTA pin in core disable mode. — Unique vector number fo r each interrupt source
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
6 Freescale Semiconductor
Electrical Characteristics
- Dual industry-standard I 2C interfaces — Two-wire interface — Multiple master support — Master or slave I 2C mode support — On-chip digital filtering rejects spikes on the bus — System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware
- DMA controller — Four independent virtual channels — Concurrent execution across multiple channels with programmable bandwidth control — Handshaking (external control) si gnals for all channels: DMA_DREQ [0:3], DMA_DACK[0:3], DMA_DDONE[0:3] — All channels accessible to local core and remote PCI masters — Misaligned transfer capability — Data chaining and direct mode — Interrupt on completed segment and chain
- DUART — Two 4-wire interfaces (RxD, TxD, RTS, CTS) — Programming model compat ible with the original 16450 UART and the PC16550D
- Serial peripheral interface (S PI) for master or slave
- General-purpose parallel I/O (GPIO) — 64 parallel I/O pins multip lexed on various chip interfaces
- System timers — Periodic interrupt timer — Real-time clock — Software watchdog timer — Eight general-purpose timers
- Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
- Integrated PCI bus and SDRAM clock generation
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8349EA. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 7
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 permanent damage to the device. power-on reset and power-down sequences. power-on reset and power-down sequences. reset and power-down sequences. 5 (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
8 Freescale Semiconductor
2.1.2 Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8349EA. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349EA. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD Table 2. Recommended Operating Conditions
1.8 V ± 90 mV
2.5 V ± 125 mV
- tinterface refers to the clock period associated with the bus clock interface.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 9 Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349EA for the 3.3-V signals, respectively. Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling
2.1.3 Output Driver Characteristics
2.2 Power Sequencing
This section details the power sequencing considerations for the MPC8349EA.
2.2.1 Power-Up Sequencing
Table 3. Output Drive Capability
7.1 V p-to-p
10 Freescale Semiconductor
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V , see Figure 4. Figure 4. Power Sequencing Example
3 Power Characteristics
The estimated typical power dissipation for the MPC8349EA device is shown in Table 4. Table 4. MPC8349EA Power Dissipation1 1 The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5.
Table 5 shows the estimated typical I/O power dissipation for MPC8349EA. Table 5. MPC8349EA Typical I/O Power Dissipation
12 Freescale Semiconductor
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the device.
4.1 DC Electrical Characteristics
Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8349EA.
4.2 AC Electrical Characteristics
(CLKIN/PCI_CLK) AC timing specifications for the device. Table 6. CLKIN DC Timing Specifications Table 7. CLKIN AC Timing Specifications
- Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
- Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
- Timing is guaranteed by design and characterization.
- This represents the total input jitter—short te rm and long term—and is guaranteed by design.
- The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
- Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless
4.3 TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
5 RESET Initialization
electrical requirements of the MPC8349EA.
5.1 RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8349EA. Table 8. EC_GTX_CLK125 AC Timing Specifications
- EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
Table 9. RESET Pins DC Electrical Characteristics1
14 Freescale Semiconductor
5.2 RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the MPC8349EA.
- This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
- HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
Table 10. RESET Initialization Timing Specifications
- tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
- tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
- POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 9. RESET Pins DC Electrical Characteristics1 (continued)
Table 11 lists the PLL and DLL lock times.
6 DDR and DDR2 SDRAM
MPC8349EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V . The AC electrical specifications are the same for DDR and DRR2 SDRAM. Document,” for silicon revision level determination.
6.1 DDR and DDR2 SDRAM DC Electrical Characteristics
MPC8349EA when GVDD(typ) = 1.8 V. Table 11. PLL and DLL Lock Times
- DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
- The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
16 Freescale Semiconductor
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V .
- GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
- MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise
on MVREF cannot exceed ±2% of the DC value.
- VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MVREF. This rail should track variations in the DC level of MVREF.
- Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
- GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
- MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
- VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
- Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V . Table 16 provides the current draw characteristics for MVREF.
6.2 DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V . Table 18 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V . Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V Table 16. Current Draw Characteristics for MVREF
- The voltage regulator for MVREF must supply up to 500 μA current.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GVDD of 1.8 ± 5%. Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions with GVDD of 2.5 ± 5%.
18 Freescale Semiconductor
Table 19 provides the input AC timing specifications for the DDR SDRAM interface. Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter. Figure 5. DDR Input Timing Diagram Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
400 MHz –600 600 3
333 MHz –750 750 —
266 MHz –750 750 —
200 MHz –750 750 —
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
- The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
- This specification applies only to the DDR interface.
6.2.2 DDR and DDR2 SDRAM Outp ut AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications. Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
400 MHz 700 —
333 MHz 775 —
266 MHz 1100 —
200 MHz 1200 —
333 MHz 900 —
20 Freescale Semiconductor
Figure 6 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 6. Timing Diagram for tDDKHMH
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
low (L) until data outputs (D) are invalid (X) or data output hold time.
- All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
- ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
- tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the
register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value. enabled by use of these bits.
- Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.
- All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1. Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Figure 7 shows the DDR SDRAM output timing diagram. Figure 7. DDR SDRAM Output Timing Diagram Figure 8 provides the AC test load for the DDR bus. Figure 8. DDR AC Test Load
7.1 DUART DC Electrical Characteristics
Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8349EA. Table 21. DUART DC Electrical Characteristics
22 Freescale Semiconductor
7.2 DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface of the MPC8349EA.
8 Ethernet: Three-Speed Ethernet, MII Management
8.1 Three-Speed Ethernet Controller
Table 22. DUART AC Timing Specifications
- Actual attainable baud rate will be limited by the latency of interrupt processing.
- The middle of a start bit is detected as the 8
Table 21. DUART DC Electrical Characteristics (continued)
8.1.1 TSEC DC Electrical Characteristics
interface voltage as defined by JEDEC EIA/JESD8-5.
8.2 GMII, MII, TBI, RGMII, an d RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1 GMII Timing Specifications
This section describes the GMII transmit and receive AC timing specifications. Table 23. GMII/TBI and MII DC Electrical Characteristics
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
- GMII/MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply.
Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
24 Freescale Semiconductor
8.2.1.1 GMII Transmit AC Timing Specifications
Table 25 provides the GMII transmit AC timing specifications. Figure 9 shows the GMII transmit AC timing diagram. Figure 9. GMII Transmit AC Timing Diagram
8.2.1.2 GMII Receive AC Timing Specifications
Table 26 provides the GMII receive AC timing specifications. Table 25. GMII Transmit AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
- The symbols for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and
letter: R (rise) or F (fall). Table 26. GMII Receive AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Figure 10 shows the GMII receive AC timing diagram. Figure 10. GMII Receive AC Timing Diagram
8.2.2 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1 MII Transmit AC Timing Specifications
Table 27 provides the MII transmit AC timing specifications.
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
Table 27. MII Transmit AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Table 26. GMII Receive AC Timing Specifications (continued) At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
26 Freescale Semiconductor
Figure 11 shows the MII transmit AC timing diagram. Figure 11. MII Transmit AC Timing Diagram
8.2.2.2 MII Receive AC Timing Specifications
Table 28 provides the MII receive AC timing specifications.
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
Table 28. MII Receive AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Table 27. MII Transmit AC Timing Specifications (continued) At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Figure 12 provides the AC test load for TSEC. Figure 12. TSEC AC Test Load Figure 13 shows the MII receive AC timing diagram. Figure 13. MII Receive AC Timing Diagram
8.2.3 TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
Table 28. MII Receive AC Timing Specifications (continued) At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
28 Freescale Semiconductor
8.2.3.1 TBI Transmit AC Timing Specifications
Table 29 provides the TBI transmit AC timing specifications. Figure 14 shows the TBI transmit AC timing diagram. Figure 14. TBI Transmit AC Timing Diagram
8.2.3.2 TBI Receive AC Timing Specifications
Table 30 provides the TBI receive AC timing specifications. Table 29. TBI Transmit AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Table 30. TBI Receive AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
30 Freescale Semiconductor
8.2.4 RGMII and RTBI AC Timing Specifications
Table 31 presents the RGMII and RTBI AC timing specifications. Table 31. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LVDD of 2.5 V ± 5%.
- In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For
follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).
- This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
to the associated clock signal.
- For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
- Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned.
- Duty cycle reference is LVDD/2.
Figure 16 shows the RBMII and RTBI AC timing and multiplexing diagrams. Figure 16. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3 Ethernet Management Interface Electrical Characteristics
8.3.1 MII Management DC Electrical Characteristics
characteristics for MDIO and MDC are provided in Table 32 and Table 33. Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V
32 Freescale Semiconductor
8.3.2 MII Management AC Electrical Specifications
Table 34 provides the MII management AC timing specifications.
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 33. MII Management DC Electrical Characteristics Powered at 3.3 V
- The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 34. MII Management AC Timing Specifications At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%. Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V (continued)
34 Freescale Semiconductor
This section provides the AC and DC electrical specifications for the USB interface of the MPC8349EA.
9.1 USB DC Electrical Characteristics
Table 35 provides the DC electrical characteristics for the USB interface.
9.2 USB AC Electrical Specifications
Table 36 describes the general timing parameters of the USB interface of the MPC8349EA. Table 35. USB DC Electrical Characteristics Table 36. USB General Timing Parameters (ULPI Mode Only)
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
- All timings are in reference to USB clock.
- All signals are measured from OV
- Input timings are measured at the pin.
- For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
Figure 18 and Figure 19 provide the AC test load and signals for the USB, respectively. Figure 18. USB AC Test Load Figure 19. USB Signals
10 Local Bus
10.1 Local Bus DC Electrical Characteristics
Table 37 provides the DC electrical characteristics for the local bus interface. Table 37. Local Bus DC Electrical Characteristics
36 Freescale Semiconductor
10.2 Local Bus AC Electrical Specification
Table 38. Local Bus General Timing Parameters—DLL On
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
(O) going invalid (X) or output hold time.
- All timings are in reference to the rising edge of LSYNC_IN.
- All signals are measured from OV
- Input timings are measured at the pin.
the load on the LAD output pins.
- tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
load on the LAD output pins.
- tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD
- For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
38 Freescale Semiconductor
Figure 21 through Figure 26 show the local bus signals. Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
40 Freescale Semiconductor
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
11 JTAG
11.1 JTAG DC Electrical Characteristics
Table 40. JTAG Interface DC Electrical Characteristics
42 Freescale Semiconductor
11.2 JTAG AC Timing Specifications
Table 41. JTAG AC Timing Specifications (Independent of CLKIN)1 At recommended operating conditions (see Table 2). Table 40. JTAG Interface DC Electrical Characteristics (continued)
44 Freescale Semiconductor
Figure 30 provides the boundary-scan timing diagram. Figure 30. Boundary-Scan Timing Diagram Figure 31 provides the test access port timing diagram. Figure 31. Test Access Port Timing Diagram
12 I 2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8349EA.
12.1 I 2C DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the I2C interface of the MPC8349EA.
12.2 I 2C AC Electrical Specifications
refer to VIH(min) and VIL(max) levels (see Table 42). Table 42. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 10%.
- Output voltage (open drain or open collector) condition = 3 mA sink current.
B = capacitance of one bus line in pF .
- Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used.
- I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
Table 43. I2C AC Electrical Specifications
46 Freescale Semiconductor
Figure 32 provides the AC test load for the I2C. Figure 32. I2C AC Test Load Figure 33 shows the AC timing diagram for the I2C bus. Figure 33. I2C Bus AC Timing Diagram
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
letter: R (rise) or F (fall).
- The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
- The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
- CB = capacitance of one bus line in pF .
5.)The device does not follow the “I2C-BUS Specifications” version 2.1 regarding the tI2CF AC parameter. Table 43. I2C AC Electrical Specifications (continued)
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8349EA.
13.1 PCI DC Electrical Characteristics
Table 44 provides the DC electrical characteristics for the PCI interface of the MPC8349EA.
13.2 PCI AC Electrical Specifications
configured as a host or agent device. Table 45 provides the PCI AC timing specifications at 66 MHz. Table 44. PCI DC Electrical Characteristics
- The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1.
Table 45. PCI AC Timing Specifications at 66 MHz1
48 Freescale Semiconductor
Table 46 provides the PCI AC timing specifications at 33 MHz.
- PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
high (H) relative to the frame signal (F) going to the valid (V) state.
- See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
- For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
- Input timings are measured at the pin.
- The setup and hold time is with respect to the rising edge of PO
Table 46. PCI AC Timing Specifications at 33 MHz
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
high (H) relative to the frame signal (F) going to the valid (V) state.
- See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
- For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
- Input timings are measured at the pin.
- The setup and hold time is with respect to the rising edge of PO
Table 45. PCI AC Timing Specifications at 66 MHz1 (continued)
Figure 34 provides the AC test load for PCI. Figure 34. PCI AC Test Load Figure 35 shows the PCI input AC timing diagram. Figure 35. PCI Input AC Timing Diagram Figure 36 shows the PCI output AC timing diagram. Figure 36. PCI Output AC Timing Diagram
14 Timers
This section describes the DC and AC electrical specifications for the timers.
14.1 Timer DC Electrical Characteristics
Table 47. Timer DC Electrical Characteristics
50 Freescale Semiconductor
14.2 Timer AC Timing Specifications
Table 48 provides the timer input and output AC timing specifications.
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO.
15.1 GPIO DC Electrical Characteristics
Table 49 provides the DC electrical characteristics for the MPC8349EA GPIO. Table 48. Timers Input AC Timing Specifications1
- Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.
- Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external
synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation. Table 49. GPIO DC Electrical Characteristics Table 47. Timer DC Electrical Characteristics (continued)
15.2 GPIO AC Timing Specifications
Table 50 provides the GPIO input and output AC timing specifications.
16 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins.
16.1 IPIC DC Electrical Characteristics
Table 51 provides the DC electrical characteristics for the external interrupt pins.
16.2 IPIC AC Timing Specifications
Table 52 provides the IPIC input and output AC timing specifications. Table 50. GPIO Input AC Timing Specifications1
- Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.
- GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external
synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation. Table 51. IPIC DC Electrical Characteristics1
- This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT.
- IRQ_OUT and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins.
Table 52. IPIC Input AC Timing Specifications1
- Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin.
- IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external
synchronous logic. IPIC inputs must be valid for at least tPICWID ns to ensure proper operation in edge triggered mode.
52 Freescale Semiconductor
17 SPI
This section describes the SPI DC and AC electrical specifications.
17.1 SPI DC Electrical Characteristics
Table 53 provides the SPI DC electrical characteristics.
17.2 SPI AC Timing Specifications
Table 54 provides the SPI input and output AC timing specifications. Table 53. SPI DC Electrical Characteristics Table 54. SPI AC Timing Specifications1
- Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
- The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Figure 37 provides the AC test load for the SPI. Figure 37. SPI AC Test Load Figure 38 shows the SPI timings in slave mode (external clock). Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 39 shows the SPI timings in master mode (internal clock). Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram Section 18.2, “Mechanical Dimensions for the MPC8349EA TBGA. Note: The clock edge is selectable on SPI. Note: The clock edge is selectable on SPI.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
54 Freescale Semiconductor
18.1 Package Parameters for the MPC8349EA TBGA
The package parameters are provided in the following list. The package type is 35 mm × 35 mm, 672 tape ball grid array (TBGA). Package outline 35 mm × 35 mm Interconnects 672 Pitch 1.00 mm Module height (typical) 1.46 mm Solder balls 62 Sn/36 Pb/2 Ag (ZU package) 96.5 Sn/3.5Ag (VV package) Ball diameter (typical) 0.64 mm
18.2 Mechanical Dimensions for the MPC8349EA TBGA
Figure 40. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8349EA TBGA
- All dimensions are in millimeters.
- Dimensions and tolerances per ASME Y14.5M-1994.
- Maximum solder ball diameter measured parallel to datum A.
- Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
- Parallelism measurement must exclude any effect of mark on top surface of package.
56 Freescale Semiconductor
18.3 Pinout Listings
Table 55 provides the pin-out listing for the MPC8349EA, 672 TBGA package. Table 55. MPC8349EA (TBGA) Pinout Listing
Table 55. MPC8349EA (TBGA) Pinout Listing (continued)
58 Freescale Semiconductor
60 Freescale Semiconductor
62 Freescale Semiconductor
64 Freescale Semiconductor
1.3 V for
667 MHz)
- This pin is an open-drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
- This pin is an open-drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
- During reset, this output is actively driven rather than three-stated.
- These JTAG pins have weak internal pull-up P-FETs that are always enabled.
- This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.
- This pin must always be tied to GND.
- This pin must always be left not connected.
- Thermal sensitive resistor.
- It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net.
- A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LV
- For systems that boot from local bus (GPCM)-controlled NOR flash, a pullup on LGPL4 is required.
66 Freescale Semiconductor
19 Clocking
Figure 41 shows the internal distribution of the clocks. Figure 41. MPC8349EA Clock Subsystem whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk). In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency. register after the device exits reset. Table 56 specifies which units have a configurable clock frequency. Table 56. Configurable Clock Units
68 Freescale Semiconductor
distributor for more information.
19.1 System PLL Configuration
encodings for the system PLL. Table 57. Operating Frequencies for TBGA frequency of the security core and USB modules does not exceed the respective values listed in this table.
400 MHz 533 MHz 667 MHz Unit
2 The DDR data rate is 2x the DDR memory bus frequency. 3 The DDR data rate is 2x the DDR memory bus frequency. csb_clk frequency (depending on RCWL[LBIUCM]). Table 58. System PLL Multiplication Factors
0001 Reserved
Table 59. CSB Frequency Options for Host Mode Table 58. System PLL Multiplication Factors (continued)
70 Freescale Semiconductor
1 CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. Table 60. CSB Frequency Options for Agent Mode Table 59. CSB Frequency Options for Host Mode (continued)
19.2 Core PLL Configuration
not listed in Table 61 should be considered as reserved. 1 CFG_CLKIN_DIV doubles csb_clk if set high. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. Table 60. CSB Frequency Options for Agent Mode (continued)
72 Freescale Semiconductor
Table 61. e300 Core PLL Configuration is in the range of 800–1800 MHz.
19.3 Suggested PLL Configurations
Table 62 shows suggested PLL configurations for 33 and 66 MHz input clocks. Table 62. Suggested PLL Configurations
33 MHz CLKIN/PCI_CLK Options
66 MHz CLKIN/PCI_CLK Options
74 Freescale Semiconductor
20 Thermal
This section describes the thermal specifications of the MPC8349EA.
20.1 Thermal Characteristics
Table 63 provides the package thermal characteristics for the 672 35× 35 mm TBGA of the MPC8349EA. COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. Table 63. Package Thermal Characteristics for TBGA Table 62. Suggested PLL Configurations (continued)
20.2 Thermal Management Information
For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 5 for I/O power dissipation values.
20.2.1 Estimation of Junction Temp erature with Junction-to-Ambient
demonstrated that errors of a factor of two (in the quantity TJ –T A) are possible.
20.2.2 Estimation of Junction Te mperature with Junction-to-Board
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
- Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
- Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM).
- Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
- Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 63. Package Thermal Characteristics for TBGA (continued)
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
76 Freescale Semiconductor
(edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TA + (RθJA × PD) where: TJ = junction temperature (°C) TA = ambient temperature for the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
20.2.3 Experimental Determinat ion of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (ΨJT) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TJ = junction temperature (°C) TT = thermocouple temperature on top of package (°C) ΨJT = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
20.2.4 Heat Sinks and Juncti on-to-Case Thermal Resistance
Some application environments require a heat sink to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA
board, or change the thermal dissipation on the printed-circuit board surrounding the device. application environment, a standard heat sink is not required. Table 64 shows heat sink thermal resistance for TBGA of the MPC8349EA. detailed thermal models can be made available on request. Table 64. Heat Sink and Thermal Resistance of MPC8349EA (TBGA)
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
78 Freescale Semiconductor
Heat sink vendors include the following list: Aavid Thermalloy 603-224-9988 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 408-567-8082 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) 408-436-8770 Loroco Sites
671 East Brokaw Road
San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics 800-522-2800 Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 603-635-5102 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Interface material vendors include the following: Chomerics, Inc. 781-935-4850 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation 800-248-2481 Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 79 System Design Information The Bergquist Company 800-347-4572 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com
20.3 Heat Sink Attachment
When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements.
20.3.1 Experimental Determination of the Junction Temperature with a
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. TJ = TC + (RθJC × PD) where: TJ = junction temperature (°C) TC = case temperature of the package (°C) RθJC = junction-to-case thermal resistance (°C/W) PD = power dissipation (W)
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8349EA.
21.1 System Clocking
The MPC8349EA includes two PLLs: 1. The platform PLL generates the platform cloc k from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 19.1, “System PLL Configuration.”
80 Freescale Semiconductor
- The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
21.2 PLL Power Supply Filtering
low frequency filter scheme. provide four independent filter circuits as illustrated in Figure 42, one to each of the four A VDD pins. Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other. pin, which is on the periphery of package, without the inductance of vias. Figure 42 shows the PLL power supply filter circuit. Figure 42. PLL Power Supply Filter Circuit
21.3 Decoupling Recommendations
the device using a standard escape pattern. Others can surround the part. capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
capacitors are 100–330 µF (A VX TPS tantalum or Sanyo OSCON).
21.4 Connection Recommendations
connected to GND. All NC (no-connect) signals must remain unconnected.
21.5 Output Buffer DC Impedance
driver is a push-pull single-ended driver type (open drain for I2C). output impedance is the average of two components, the resistances of the pull-up and pull-down devices. other in value. Then, Z0 = (RP + RN) ÷ 2. Figure 43. Driver Impedance Measurement
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
82 Freescale Semiconductor
Ordering Information
V2 =( 1 ÷ (1/R1 +1 / R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1 ÷ V2 –1 ) . The drive current is then Isource =V 1 ÷ Rsource. Table 65 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105°C.
21.6 Configuration Pin Multiplexing
The MPC8349EA power-on configuration options can be set through external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see the customer-visible configuration pins). These pins are used as output only pins in normal operation. However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for the output pins.
21.7 Pull-Up Resistor Requirements
The MPC8349EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins, including I2C pins, and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, refer to application note AN2931, “PowerQUICC Design Checklist.” This section presents ordering information for the device discussed in this document, and it shows an example of how the parts are marked. NOTE The information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending in A or B). For information on revision 1.1 silicon and earlier versions, see the MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications (Document Order No. MPC8349EEC). Table 65. Impedance Characteristics Note: Nominal supply voltages. See Table 1, Tj = 105°C.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 83
22.1 Part Numbers Fully Ad dressed by This Document
Table 66 shows an analysis of the Freescale part numbering nomenclature for the MPC8349EA. The individual part numbers correspond to a maximum processor core frequency. Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration parts including extended temperatures, refer to the device product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. Table 67 shows the SVR settings by device and package type. Table 66. Part Numbering Nomenclature
- For temperature range = C, processor frequency is limited to with a platform frequency of 266 and up to 533 with a platform
- See Section 18, “Package and Pin Listings,” for more information on available package types.
- Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
- ALF marked parts support DDR1 data rate up to 333 MHz (at 333 MHz CSB as the 'F' marking implies) and DDR2 data rate
Table 67. SVR Settings
84 Freescale Semiconductor
22.2 Part Marking
Parts are marked as in the example shown in Figure 44. Figure 44. Freescale Part Marking for TBGA Devices
23 Document Revision History
This table provides a revision history of this document. Table 68. Document Revision History 13 09/2011 In Section 2.2, “Power Sequencing,” added Section 2.2.1, “Power-Up Sequencing” and Figure 4. I n Table 25, Table 29 and Table 31, removed the GTX_CLK125. I n Table 34, updated tMDKHDX Max value from 170ns to 70ns. 12 11/2010 In Table 55 added note for pin LGPL4. I n Section 21.7, “Pull-Up Resistor Requirements, updated the list of open drain type pins. 11 05/2010 In Table 25 through Table 30, changed VIL(min) to VIH(max) to (20%–80%). ATWL YYWW is the traceability code. YWWLAZ is the assembly traceability code.
9 2/2009 Added footnote 6 to Table 7. I n Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only. Added footnote 11 to Table 55. Added footnote 4 to Table 66. I n Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list. I n Table 57, corrected the max csb_clk to 266 MHz. added USB to the seventh row. paragraph, added a new paragraph. row, changed the value in the 533 MHz column to 100-333. changed the CORE PLL value to 0000110. In Section 23, “Ordering Information,” replaced first paragraph and added a note. In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph. 6 2/2007 Page 1, updated first paragraph to reflect PowerQUICC II Pro information. and deleted original note 3; renumbered the remaining notes. In Figure 41, “JTAG Interface Connection,” updated with new figure. voltage and PLL supply voltage of 1.3 V for 667-MHz parts. nominal core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts. core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts. Table 68. Document Revision History (continued)
86 Freescale Semiconductor
3 11/2006 Updated note in introduction. for TBGA parts for silicon 3.x and 400 MHz for DDR2 for TBGA parts for silicon 3.x. In Section 23, “Ordering Information,” replicated note from document introduction. 2 8/2006 Changed all references to revision 2.0 silicon to revision 3.0 silicon. = 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8. In Table 66, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703. Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Document Number: MPC8349EAEC Rev. 13 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Freescale, the Freescale logo and PowerQUICC are trademarks of Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2006–2011 Freescale Semiconductor, Inc.