14N25

RFD14N05SM FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• 14A, 50V r DS(ON) = 0.100Ω  Temperature Compensating PSPICE® Model  Peak Current vs Pulse Width Curve  UIS Rating Curve 1 7 5oC Operating Temperature  Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-251AA JEDEC TO-252AA

Ordering Information

RFD14N05SM TO-252AA F14N05 NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05SM9A. G D S SOURCE DRAIN (FLANGE) GATE DRAIN GATE SOURCE DRAIN (FLANGE) Data Sheet February 2004

©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N05, RFD14N05SM UNITS Refer to Peak Current Curve A 0.32 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 9) 50 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS , VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS , VGS = 0V, TC = 150oC - - 250 µA Gate to Source Leakage Current I GSS VGS = ±20V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 14A, VGS = 10V, (Figure 11) - - 0.100 Ω Turn-On Time t ON VDD = 25V, ID ≈ 14A, VGS = 10V, R GS = 25Ω, R L = 1.7Ω (Figure 13) - - 60 ns Turn-On Delay Time t d(ON) -1 4- n s Rise Time t r -2 6- n s Turn-Off Delay Time t d(OFF) -4 5- n s Fall Time t f -1 7- n s Turn-Off Time t OFF - - 100 ns Total Gate Charge Q g(TOT) VGS = 0V to 20V V DD = 40V, ID = 14A, R L = 2.86Ω Ig(REF) = 0.4mA (Figure 13) - - 40 nC Gate Charge at 5V Q g(10) VGS = 0V to 10V - - 25 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - - 1.5 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 570 - pF Output Capacitance C OSS - 185 - pF Reverse Transfer Capacitance C RSS -5 0- p F Thermal Resistance Junction to Case R θJC - - 3.125 oC/W Thermal Resistance Junction to Ambient RθJA - - 100 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = 14A - - 1.5 V Diode Reverse Recovery Time t rr ISD = 14A, dISD /dt = 100A/µs - - 125 ns NOTES: 2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). RFD14N05, RFD14N05SM

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

175 T C–

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C .SUBCKT RFD14N05 2 1 3 ; rev 9/12/94 CA 12 8 8.84e-10 CB 15 14 9.34e-10 CIN 6 8 5.2e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 62.87 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.34e-9 LSOURCE 3 7 3.79e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 2.2e-3 RGATE 9 20 5.64 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 42.3e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.82 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))} .MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5) .MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6) .MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5) .MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5) .MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. EVTO CA CB EGS EDS RIN CIN MOS1 MOS2 DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE LSOURCE SOURCE RBREAK RVTO VBAT IT VTO DPLCAP 7 3 17 18 RDRAIN ESCL RSCL1 RSCL2 51 S1A S2A S2BS1B 12 1513 -18 8RGATE GATE LGATE 2091 ESG 11 + RFD14N05, RFD14N05SM

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Preliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Formative or In Design First Production Full Production Not In Production ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC OPTOPLANAR™ PACMAN™ FACT Quiet Series™ FAST FASTr™ FPS™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ I 2C™ ImpliedDisconnect™ Rev. I8 ACEx™ ActiveArray™ Bottomless™ CoolFET™ CROSSVOLT ™ DOME™ EcoSPARK™ E 2CMOS TM EnSignaTM FACT™ POP™ Power247™ PowerSaver™ PowerTrench QFET  QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™