MC14553B ONSEMI | Alldatasheet

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 Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3

1 Publication Order Number:

/C0077/C0067/C0049/C0052/C0053/C0053/C0051/C0066 /C0051/C0045/C0068/C0105/C0103/C0105/C0116 /C0066/C0067/C0068 /C0067/C0111/C0117/C0110/C0116/C0101/C0114 The MC14553B 3–digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on–chip oscillator provides the low–frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications.

  • TTL Compatible Outputs
  • On–Chip Oscillator
  • Cascadable
  • Clock Disable Input
  • Pulse Shaping Permits Very Slow Rise Times on Input Clock
  • Output Latches
  • Master Reset MAXIMUM RATINGS (Voltages Referenced to VSS ) (Note 1.) Symbol Parameter Value Unit VDD DC Supply Voltage Range –0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) –0.5 to VDD + 0.5 V Iin Input Current (DC or Transient) per Pin ±10 mA Iout Output Current (DC or Transient) per Pin +20 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Ambient Temperature Range –55 to +125 °C Tstg Storage Temperature Range –65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW//C0095C From 65/C0095C To 125/C0095C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS /C0118 (Vin or Vout) /C0118 VDD . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD ). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work WeekDevice Package Shipping

ORDERING INFORMATION

MC14553BCP PDIP–16 25/Rail MC14553BDW SOIC–16 47/Rail MARKING DIAGRAMS PDIP–16 P SUFFIX CASE 648 MC14553BCP AWLYYWW SOIC–16 DW SUFFIX CASE 751G 14553B AWLYYWW

http://onsemi.com BLOCK DIAGRAM V DD = PIN 16 VSS = PIN 8 CLOCK LE DIS MR O.F. DS1 DS2 DS3 CIA CIB TRUTH TABLE Inputs Master Reset Clock Disable LE Outputs 0 0 0 No Change 0 0 0 Advance

0 X 1 X No Change

0 X X Latched

0 X X 1 Latched

1 X X 0 Q0 = Q1 = Q2 = Q3 = 0

X = Don’t Care

http://onsemi.com ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS ) VDD – 55/C0095C 25/C0095C 125/C0095C Characteristic Symbol VDD Vdc Min Max Min Typ (3.) Max Min Max Unit Output Voltage “0” Level Vin = VDD or 0 VOL 5.0 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 Vdc “1” Level Vin = 0 or VDD VOH 5.0 4.95 9.95 14.95 4.95 9.95 14.95 5.0 4.95 9.95 14.95 Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 1.5 3.0 4.0 2.25 4.50 6.75 1.5 3.0 4.0 1.5 3.0 4.0 Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIH 5.0 3.5 7.0 3.5 7.0 2.75 5.50 8.25 3.5 7.0 Vdc Output Drive Current (VOH = 4.6 Vdc) Source — (VOH = 9.5 Vdc) Pin 3 (VOH = 13.5 Vdc) IOH 5.0 – 0.25 – 0.62 – 1.8 – 0.2 – 0.5 – 1.5 – 0.36 – 0.9 – 3.5 0.14 0.35 1.1 mAdc (VOH = 4.6 Vdc) Source — (VOH = 9.5 Vdc) Other (VOH = 13.5 Vdc) Outputs 5.0 – 0.64 – 1.6 – 4.2 – 0.51 – 1.3 – 3.4 – 0.88 – 2.25 – 8.8 – 0.36 – 0.9 – 2.4 mAdc (VOL = 0.4 Vdc) Sink — (VOL = 0.5 Vdc) Pin 3 (VOL = 1.5 Vdc) IOL 5.0 0.5 1.1 1.8 0.4 0.9 1.5 0.88 2.25 8.8 0.28 0.65 1.20 mAdc (VOL = 0.4 Vdc) Sink — Other (VOL = 0.5 Vdc) Outputs (VOL = 1.5 Vdc) 5.0 3.0 6.0 2.5 5.0 4.0 8.0 1.6 3.5 mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Quiescent Current (Per Package) MR = VDD IDD 5.0 5.0 0.010 0.020 0.030 5.0 150 300 600 µAdc Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 IT = (0.35 µA/kHz) f + IDD IT = (0.85 µA/kHz) f + IDD IT = (1.50 µA/kHz) f + IDD µAdc 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25/C0095C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS ) in volts, f in kHz is input frequency, and k = 0.004.

http://onsemi.com ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25/C0095C) Characteristic Figure Symbol VDD Min Typ (7.) Max Unit Output Rise and Fall Time tTLH , tTHL = (1.5 ns/pF) CL + 25 ns tTLH , tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH , tTHL = (0.55 ns/pF) CL + 9.5 ns 2a tTLH , tTHL 5.0 100 200 100 ns Clock to BCD Out 2a tPLH , tPHL 5.0 900 500 200 1800 1000 400 ns Clock to Overflow 2a tPHL 5.0 600 400 200 1200 800 400 ns Reset to BCD Out 2b tPHL 5.0 900 500 300 1800 1000 600 ns Clock to Latch Enable Setup Time Master Reset to Latch Enable Setup Time 2b tsu 5.0 600 400 200 300 200 100 ns Removal Time Latch Enable to Clock 2b trem 5.0 – 80 – 10 – 200 – 70 – 50 ns Clock Pulse Width 2a tWH(cl) 5.0 550 200 150 275 100 ns Reset Pulse Width 2b tWH(R) 5.0 1200 600 450 600 300 225 ns Reset Removal Time — trem 5.0 – 80 – 180 – 50 – 30 ns Input Clock Frequency 2a fcl 5.0 1.5 5.0 7.0 0.9 2.5 3.5 MHz Input Clock Rise Time 2b tTLH 5.0 No Limit ns Disable, MR, Latch Enable Rise and Fall Times — tTLH , tTHL 5.0 5.0 4.0 µs Scan Oscillator Frequency (C1 measured in µF) 1 fosc 5.0 1.5/C1 4.2/C1 7.0/C1 Hz 6. The formulas given are for the typical characteristics only at 25/C0095C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

display control. All outputs are TTL compatible. scanning clock which drives the multiplexer output selector. one pulse for every 1000 counts. three BCD counters and the multiplexer scanning circuit. operating on input pulses with very slow rise times. while the latch input is high, independent of other inputs. during the entire reset cycle. Figure 3. Expanded Block Diagram

Figure 4. Six–Digit Display

http://onsemi.com PACKAGE DIMENSIONS PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 /C0095/C0095/C0095/C0095

http://onsemi.com PACKAGE DIMENSIONS SOIC–16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–03 ISSUE B D 14X B16X SEATING PLANE SAM0.25 B ST 16 9 h X 45/C0095 MBM0.25 H8X E B A e T A L C /C0113 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 /C0113 0 7 /C0095/C0095

http://onsemi.com Notes

http://onsemi.com Notes

http://onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone : 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–asia@hibbertco.com JAPAN : ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone : 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. MC14553B/D NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone : (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) Email: ONlit–german@hibbertco.com French Phone : (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: ONlit–french@hibbertco.com English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland