13892

13892_10 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 161

Technical content

Features

• Battery charger system for wa ll charging and USB charging
• 10 bit ADC for monitoring battery and other inputs, plus a coulomb counter support module
• 4 adjustable output buck converters for direct supply of the processor core and memory
• 12 adjustable output LDOs with internal and external pass devices
• Boost converter for supplying RGB LEDs
• Serial backlight drivers for displays and keypad, plus RGB LED drivers
• Power control logic with proce ssor interface and event detection
• Real time clock and crystal oscillat or circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC
• Touch screen interface
• SPI/I 2C bus interface for control and register access
• Two package offerings in 7 x 7 mm and 12 x 12 mm

Figure 1. 13892 Typical Operating Circuit

ORDERING INFORMATION

See Device Variation Table on Page 2. CALENDAR USB Li Ion Battery Adapter IRDA Camera AP Aud& Pwr Mgmt TV Out Camera MC13892 Power Mgmt & User Interface i.MX51 Apps Processor NVR DRAM BT (+FM) Display Backlight SPI/I2C SSI UI RTC Touch Screen MMC APAud Audio IC Mic Inputs Stereo Loudspeakers Line In/Out UI Backlight Stereo headphones Light Sensor Thermistor Power Power Coin Cell Battery Charger LED RGB Color Indicators CALENDARCALENDAR USB Li Ion Battery Adapter IRDA Camera AP Aud& Pwr Mgmt TV Out Camera MC13892 Power Mgmt & User Interface i.MX51 Apps Processor NVR DRAM BT (+FM) Display Backlight SPI/I2C SSI UIUI RTC Touch Screen MMC APAud Audio IC Mic Inputs Stereo Loudspeakers Line In/Out UI Backlight Stereo headphones Light Sensor Thermistor Power Power Coin Cell Battery Charger LED RGB Color Indicators

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Table 1. MC13892 Device Variations Table

1. For Tape and Reel product, add “/R2” as a suffix to the device number.
2. Recommended for all new designs
3. Not recommended for new designs
4. Backward compatable replacement part for MC13892VK, MC13892JVK, MC13892VL and MC13892JVL

Figure 2. 13892 Simplified Internal Block Diagram

10 Bit GP

32 KHz

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Figure 3. 13892VK Pin Connections

Figure 4. 13892VL Pin Connections

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Table 2. 13892 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 32.

1. Battery current sensing point 2
2. Battery supply voltage sense
3. Output to battery supplied accesories
4. Input supply to the IC core circuitry
5. Application supply voltage sense

1. Charge current sensing point 2

Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 32.

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A functional description of each pin can be found in the Functional Pin Description section beginning on page 32.

A functional description of each pin can be found in the Functional Pin Description section beginning on page 32.

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1. Input regulator camera using internal
2. Drive output regulator for camera voltage
3. Drive VGEN3 output regulator

A functional description of each pin can be found in the Functional Pin Description section beginning on page 32.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 13892

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

1. USB Input Voltage applies to UVBUS pin only
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 W) and the Charge Device

Model (CDM), Robotic (CZAP = 4.0pF).

1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

1. Mode Pin is not ESD protected.

Table 4. Dissipation Ratings

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

1. VPLL, VIOHI, VGEN2, VAUDIO, VVIDEO

Analog Integrated Circuit Device Data Freescale Semiconductor 13 13892 STATIC ELECTRICAL CHARACTERISTICS VSRTC ACTIVE MODE – DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VSRTC 1.15 1.20 1.25 V Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IRTCQS - 0.8 1.0 µA CLK AND MISO Input Low CS, MOSI, CLK VINCSLO VINMOSILO VINCLKLO 0 - 0.3*SPIVCC V Input High CS, MOSI, CLK VINCSHI VINMOSIHI VINCLKHI 0.7*SPIVCC - SPIVCC+0.3 V Output Low MISO, INT Output sink 100 µA VOMISOLO VOINTLO 0 - 0.2 V Output High MISO, INT Output source 100 µA VOMISOHI VOINTHI SPIVCC-0.2 - SPIVCC V SPIVCC Operating Range SPIVCC 1.75 - 3.1 V BUCK CONVERTERS Operating Input Voltage PWM operation, 0 < IL < IMAX PFM operation, 0 < IL < IMAX Extended PWM or PFM operation(13) VSWIN 3.0 2.8 UVDET 4.65 4.65 4.65 V Output Voltage Range Switcher 1 Switchers 2, 3, and 4 VSW1 0.6 0.6 1.375 1.850 V Output Accuracy PWM mode including ripple, load regulation, and transients (14) PFM Mode, including ripple, load regulation, and transients VSWLOPP VSWLIPPI Nom-50 Nom-50 Nom Nom Nom+50 Nom+50 mV Maximum Continuous Load Current, IMAX, VINMIN<BP<4.65 V SW1 in PWM mode (SWILIMB = 0, no max current limit) SW1 in PWM Mode (SWILIMB = 1, no max current limit)(15) SW2, SW3, SW4 in PWM mode (SWILIMB = 0, no max current limit) SW2, SW3, SW4 in PWM mode (SWILIMB = 1, no max current limit)(15) SW1, SW2, SW3, SW4 in PFM mode ISW1 ISW2,3,4 ISW2,3,4 ISW1, 2, 3, 4 800 1050 800 800 mA Maximum Peak Load Current, IPEAK, BP ≤ 4.2 V, SW1 in PWM Mode (SWILIMB = 1, no max current limit)(15) SW4 in PWM Mode (SWILIMB = 1, no max current limit)(15) ISW1 ISW4 1250 1000 mA Notes 13. In the extended operating range the performance may be degraded 14. Transient loading for load steps of ILmax/2 15. In this mode, current limit protection is disabled for SW1 - SW4 by setting SWILIMB = 1. Therefore, the load on SW1-4 should not exceed the conditions specified in the table above. Application needs to provide current limit protection circuitry either in battery or as pre- regulated supply to BP. the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS BUCK CONVERTERS (CONTINUED) Effective Quiescent Current Consumption PWM Mode, IL = 0 mA; device not switching PFM Mode, IL = 0 mA; device not switching ISWQS 100 µA Automatic Mode Change Threshold, Switchover between PFM and PWM modes AMCTH - 50 - mA Efficiency PFM, 0.9 V, 1.0 mA PFM, 01.8 V, 1.0 mA PWM Pulse Skipping, 1.25 V, 50 mA PWM Pulse Skipping, 1.8 V, 50 mA PWM, 1.25 V, 500 mA PWM, 1.8 V, 500 mA External Components, Used as a condition for all other parameters Inductor for SW2, SW3, SW4(16) Inductor for SW1(16) Inductor Resistance Bypass Capacitor for SW2, SW3, SW4(17) Bypass Capacitor for SW1(18) Bypass Capacitor ESR Input Capacitor(19) LSW234 LSW1 RWSW COSW234 COSW1 ESRSW -20% -30% -35% -35% 5.0 1.0 2.2 1.5 2x22 4.7 +20% +30% 0.16 +35% +35% µH µH W µF µF mΩ µF SWBST Average Output Voltage(20) 3.0 V < VIN < 4.65 (1), 0 < IL < ILMAX (21) VBST Nom-5% 5.0 Nom+5% V Output Ripple 3.0 V < VIN < 4.65, 0 < IL < ILMAX, Excluding reverse recovery of Schottky diode VBSTPP - - 120 mVpp Average Load Regulation VIN = 3.6 V, 0 < IL < ILMAX VBSTLOR - - 0.5 mV/mA Average Line Regulation 3.0 V < VIN < 4.65 V, IL = ILMAX VBSTLIR - - 50 mV Notes 16. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 17. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J106M 18. Preferably 0805 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C2012X5R0J226M 19. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J475 20. Output voltage when configured to supply VBUS in OTG mode can be as high as 5.75 V 21. Vin is the low side of the inductor that is connected to BP. the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 13892 STATIC ELECTRICAL CHARACTERISTICS SWBST (CONTINUED) Maximum Continuous Load Current ILMAX 3.0 V < VIN < 4.65, VOUT = 5.0 V IBST 300 - - mA Peak Current Limit At SWBSTIN; VIN = 3.6 V BSTPK 800 - 1500 mA Start-up Overshoot IL = 0 mA VBSTOS - - 500 mV Efficiency, IL = ILMAX SWBSTEFF - 80 - % Bias Current Consumption IBSTBIAS - 390 1200 µA External Components - Used as a condition for all other parameters Inductor(22) Inductor Resistance Inductor saturation current at 30% loss in inductance value Bypass Capacitor(23) Bypass Capacitor ESR at resonance Input Capacitor Diode current capability Diode current capability LBST R_WBST ILSAT COBST ESRBST CBSTD IBSTDPK IBSTDPK -20% 1.0 -60% 1.0 1.0 850 1500 2.2 4.7 +20% 0.2 +35% µH W A µF mΩ µF mAdc mApk NMOS Off Leakage, SWBSTIN = 4.5 V, SWBSTEN = 0 IBSTIK - 1.0 5.0 µA VVIDEO Operating Input Voltage Range VINMIN to VINMAX VINVIDEO VNOM+0.25 - 4.65 V Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) IVIDEO 0 -- 350 mA Minimum Bypass Capacitor Value Used as a condition for all other parameters COVIDEO 1.1 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRVIDEO 20 - 100 mΩ VVIDEO ACTIVE MODE DC Output Voltage VOUT Vinmin < VIN < VINMAX, ILMIN < IL < ILMAX ΔVVIDEO VNOM – 3% VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX VVIDEOLOPP - - 0.20 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VVIDEOLIPP - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND IVIDEOSHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IVIDEOQS - 30 45 µA Notes 22. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 23. Applications of SWBST should take into account impact of tolerance and voltage derating on the bypass capacitor at the output level. the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS VVIDEO LOW POWER MODE DC - VVIDEOMODE = 1 Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP ΔVVIDEOLO VNOM -3% VNOM VNOM +3% V Current Load Range ILminlp to ILMAXLP IVIDEOLO 0.0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IVIDEOQSLO - 8.0 10.5 µA VAUDIO Operating Input Voltage Range VINMIN to VINMAX VAUDIO VNOM+0.25 - 4.65 V Operating Current Load Range ILMIN to ILMAX IAUDIO 0 - 150 mA Minimum Bypass Capacitor Value COAUDIO 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRAUDIO 0 - 0.1 W VAUDIO ACTIVE MODE DC Output Voltage VOUT (VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX) VAUDIO VNOM – 3% VNOM VNOM + 3% V Load Regulation (1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX) VAUDIOLOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VAUDIOLIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short circuit VOUT to GND IAUDIOSHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IAUDIOQS - 8.0 10.5 µA VPLL AND VDIG Operating Input Voltage Range VINMIN to VINMAX VDIG, VPLL all settings, BP biased VPLL, VDIG [1:0] = 00,01 VPLL, VDIG [1:0] = 10, 11, External Switcher VINPLL, VINDIG UVDET 1.75 2.15 SW4 = 1.8 2.2 4.65 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX IPLL, IDIG 0 - 50 mA Minimum Bypass Capacitor Value Used as a condition for all other parameters COPLL, CODIG 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRPLL, ESRDIG 0 - 0.1 W VPLL AND VDIG ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VPLL, VDIG VNOM – 0.05 VNOM VNOM + 0.05 V Load Regulation 1.0 mA < IL < ILMAX for any VINMIN < VIN < VINMAX VPLLLOR, VDIGLOR - - 0.35 mV/mA the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 13892 STATIC ELECTRICAL CHARACTERISTICS VPLL AND VDIG ACTIVE MODE DC (CONTINUED) Line Regulation VINMIN < VIN < VINMAX for any ILMIN < IL < ILMAX VPLLLIR, VDIGLIR - 5.0 8.0 mV Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IPLLLQS, IDIGLQS - 8.0 10.5 µA VIOHI Operating Input Voltage Range VINMIN to VINMAX VNOM = 2.775 V VINIOHI VNOM+0.25 - 4.65 V Operating Current Load Range ILMIN to ILMAX IIOHI 0 - 100 mA Minimum Bypass Capacitor Value COIOHI 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRIOHI 0 - 100 mΩ VIOHI ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VIOH VNOM -3% VNOM VNOM +3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VIOHLOR - - 0.35 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VIOHLIR - 5.0 8.0 mV Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IIOHQS - 8.0 10.5 µA VCAM Operating Input Voltage Range VINMIN to VINMAX VINCAM VNOM +0.25 - 4.65 V Operating Current Load Range ILMIN to ILMAX Internal pass FET External PNP ICAM 250 mA Minimum Bypass Capacitor Value Internal pass device External PNP (not exceeding PNP max power) COCAM 0.65 1.1 2.2 2.2 µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRCAM 20 - 100 mΩ VCAM ACTIVE MODE DC Output Voltage VOUT (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VCAM VNOM – 3% VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VCAMLOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VCAMLIR - 5.0 8.0 mV the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS VCAM ACTIVE MODE DC (CONTINUED) Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND ICAMSHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration VINMIN < VIN < VINMAX, IL = 0, External PNP configuration ICAMQS µA VCAM LOW POWER MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VCAMLO VNOM -3% VNOM VNOM +3% V Current Load Range ILMINLP to ILMAXLP ICAMLO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ICAMQSLO - 8.0 10.5 µA VSD Operating Input Voltage Range VINMIN to VINMAX VSD[2:0] = 010 to 111 VSD[2:0] = 010 to 111, Extended Operation VSD[2:0] = 000, 001 [000] BP Supplied VSD[2:0] = 000 External Switcher Supplied VINSD VNOM+0.25 UVDET UVDET 2.15 2.20 4.65 4.65 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX Not exceeding PNP max power ISD 0 - 250 mA Minimum Bypass Capacitor Value COSD 1.1 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRSD 20 - 100 mΩ VSD ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VSD VNOM – 3% VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VSDLOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VSDLIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND ISDSHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ISDQS - 30 45 µA VSD LOW POWER MODE DC - VSDMODE = 1 Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VSDLO VNOM -3% VNOM VNOM +3% V Current Load Range ILMINLP to ILMAXLP ISDLO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ISDQSLO - 8.0 10.5 µA the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 13892 STATIC ELECTRICAL CHARACTERISTICS VUSB GENERAL Operating Input Voltage Range VINMIN to VINMAX Supplied by VBUS Supplied by SWBST VINUSB 4.4 5.0 5.25 5.75 V Operating Current Load Range ILMIN to ILMAX IUSB 0 - 100 mA Bypass Capacitor Value Range COUSB 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRUSB 0 - 0.1 W VUSB ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VUSB VNOM – 4% 3.3 VNOM + 4% V Load Regulation 0 < IL < ILMAX from DM/DP for any VINMIN < VIN < VINMAX VUSBLOR - - 1.0 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VUSBLIR - - 20 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VUSBSHT ILMAX+20% - - mA VUSB2 Operating Input Voltage Range VINMIN to VINMAX Extended operation VINUSB2 VNOM +0.25 UVDET 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX IUSB2 0 - 50 mA Minimum Bypass Capacitor Value Used as a condition for all other parameters COUSB2 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRUSB2 0 - 0.1 W VUSB2 ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VUSB2 VNOM -3% VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VUSB2LOR - - 0.35 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VUSB2LIR - 5.0 8.0 mV Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IUSB2QS - 8.0 13 µA the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS UVBUS Operating Input Voltage Range VINMIN to VINMAX VINUSB supplied by SWBST VINUVBUS 4.75 5.0 5.25 V Operating Current Load Range ILMIN to ILMAX IUVBUS 0 - 100 mA Minimum Bypass Capacitor Value COUVBUS Bypass Capacitor ESR 10 kHz -1.0 MHz VINUVBUS (24) (24) (25) W UVBUS ACTIVE MODE DC Output Voltage Vout VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VUVBUS 4.4 5.0 5.25 V VGEN1 Operating Input Voltage Range VINMIN to VINMAX All settings, BP biased VGEN1=00,01, External switcher supplied VINGEN1 UVDET < VNOM +0.25 2.15 2.2 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX (not exceeding PNP max power) IGEN1 0 - 200 mA Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN1[1:0] = 10 to 11) UVDET - 4.65 V Minimum Bypass Capacitor Value COGEN1 1.1 2.2 +35% µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN1 20 - 100 mΩ VGEN1 ACTIVE MODE DC Output Voltage VOUT VGEN1 = 00, 01, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN1 = 10, 11, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN1 VNOM – 0.05 VNOM – 3% VNOM VNOM VNOM + 0.05 VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VGEN1LOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VGEN1LIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VGEN1SHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN1QS - 20 45 µA Notes 24. Filtering is shared with CHRGRAW (shorted at board level). 2.2 µF is typically included at the CHRGRAW pin. 25. 6.5 µF is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level). the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 13892 STATIC ELECTRICAL CHARACTERISTICS VGEN1 LOW POWER MODE DC - VGEN1MODE = 1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN1 = 00, 01 VGEN1 = 10, 11 VGEN1LO VNOM – 0.05 VNOM -3% VNOM VNOM VNOM + 0.05 VNOM +3% V Current Load Range ILMINLP to ILMAXLP IGEN1LO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN1QSLO - 8.0 10.5 µA VGEN2 GENERAL Operating Input Voltage Range VINMIN to VINMAX All settings, BP biased VGEN2=000,001, External switcher supplied VINGEN2 UVDET< VNOM+0.25 2.15 2.2 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) IGEN2 0 - 350 mA Minimum Bypass Capacitor Value COGEN2 1.1 2.2 +35% µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN2 20 - 100 mΩ VGEN2 ACTIVE MODE DC Output Voltage VOUT VGEN2 = 000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2 = 011, 100, 101, 110, 111, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2 VNOM -0.05 VNOM -3% VNOM VNOM VNOM +0.05 VNOM +3% V Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX VGEN2LOR - - 0.20 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VGEN2LIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VGEN2SHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN2QS - 35 45 uA VGEN2 LOW POWER MODE DC - VGEN2MODE=1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN2 = 000 to 010 VGEN2 = 011 to 111 VGEN2LO VNOM -0.05 VNOM -3% VNOM VNOM VNOM +0.05 VNOM +3% V Current Load Range ILMINLP to ILMAXLP IGEN2LO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN2QSLO - 8.0 10.5 µA the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS VGEN3 GENERAL Operating Input Voltage Range VINMIN to VINMAX VGEN3CONFIG, VGEN3 = 01, 11 VGEN3CONFIG, VGEN3 = 00, 10 VINGEN3 VNOM+0.2 UVDET 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX Internal Pass FET External PNP (Not exceeding PNP max power) IGEN3 200 mA Minimum Bypass Capacitor Value Internal pass device External pass device COGEN3 0.65 1.1 2.2 2.2 µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN3 20 - 100 mΩ VGEN3 ACTIVE MODE DC Output Voltage VOUT VGEN2 = 000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN3 VNOM – 3% VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX VGEN3LOR - - 0.40 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VGEN3SHT - 5.0 9.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short circuit VOUT to GND VGEN3SHT ILMAX+20% - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration VINMIN < VIN < VINMAX, IL = 0, external PNP configuration IGEN3QS µA VGEN3 LOW POWER MODE DC Output Voltage VOUT - (Accuracy) VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN3LO VNOM -3% VNOM VNOM +3% V Current Load Range ILMINLP to ILMAXLP IGEN3LO 0 1.0 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN3QSLO - 8.0 10.5 µA CHARGE PATH REGULATOR Input Operating Voltage - CHRGRAW VINCHRG BATTMIN - 17 V Output Voltage Spread - VCHRG[2:0]=011, 1XX Charge current 1.0 mA to 100 mA Charge current 100 mA and above BPSP 1.5 -3.0 1.5 1.5 the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 13892 STATIC ELECTRICAL CHARACTERISTICS CHARGE PATH REGULATOR (CONTINUED) Current Limit Tolerance (26) ICHRG[3:0] = 0001 ICHRG[3:0] = 0100 ICHRG[3:0] = 0110 All other settings ΔILIM 360 500 400 560 440 620 mA mA mA Start-up Overshoot - Unloaded BPOS-START - - 2.0 % Configuration Input Capacitance - CHRGRAW(27) Load Capacitor - BPSNS(27) Cable length CINCHRG CBP LC 2.2 3.0 µF µF m THERMAL Thermal Warning Lower Threshold TWL - 100 - °C Thermal Warning Higher Threshold TWH - 120 - °C Thermal Warning Hysteresis TWHYS - 3.0 - °C Thermal Protection Threshold TPT - 140 - °C BACKLIGHT LED DRIVERS Absolute Accuracy - All current settings - - 15 % Matching - At 400 mV, 21 mA - - 3.0 % Leakage - LEDxDC[5:0] = 000000 - - 1.0 µA SIGNALING LED DRIVERS Absolute Accuracy - All current settings - - 15 % Matching - At 400 mV, 21 mA - - 10 % Leakage - LEDxDC[5:0] = 000000 - - 1.0 µA ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775), VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX 4.4 5.0 5.25 V ADC Conversion Current 1.0 mA Converter Core Input Range Single ended voltage readings Differential readings -1.2 2.4 1.2 V Maximum Input Voltage(28) Channels ADIN5, ADIN6 and ADIN7 BP V Integral Nonlinearity 3.0 LSB Differential Nonlinearity 1.0 LSB Notes 26. Excludes spread and tolerance due to board and 100 mOhm sense resistor tolerances. 27. An additional derating of 35% is allowed. 28. ADIN5, 6 and 7 inputs must not exceed BP voltage. the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS ADC (CONTINUED) Zero Scale Error (Offset) Before auto calibration After auto calibration 1.0 LSB Full Scale Error (Gain) Before auto calibration After auto calibration 5.0 LSB Drift Over-temperature - Including scaling 1.0 LSB Source Impedance No bypass capacitor at input Bypass capacitor at input 10 nF 5.0 KΩ TOUCH SCREEN Plate Maximum Voltage X, Y(29) VCORE V Plate Resistance X, Y 100 1000 W Resistance Between Plates Settling Time - Contact Position measurement 180 3.0 1200 5.5 W µs TOUCH SCREEN IN STAND ALONE MODE(30) Quiescent Current - Active Mode 20 µA Max Load Current - Active Mode 20 mA Output Voltage - 0<IL<20 mA -3% 1.20 +3% V PSRR - IL=15 mA 50 dB Bypass Capacitor ESR 0 0.1 W Bypass Capacitance 0.65 2.2 +35% µF Notes 29. TS[xy][1,2] inputs must not exceed BP or VCORE 30. All characteristics in this table are applicable only for non touch screen operation. This applies to Touch Screen in Standalone Mode and below. the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 13892 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

32 KHZ CRYSTAL OSCILLATOR

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS VVIDEO ACTIVE MODE - AC (CONTINUED) Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VVIDEOtOFF 0.1 - 10 ms Transient Load Response VIN = VINMIN, VINMAX VVIDEOTLOR - 1.0 2.0 Transient Line Response IL = 75% of ILMAX VVIDEOTLIR - 5.0 8.0 mV Mode Transition Time From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP VVIDEOtMOD - - 100 µs Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VVIDEOMTR - 1.0 2.0 VAUDIO PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV, > UVDET VIN = VNOM + 1.0 V, > UVDET VAUDIOPSSR dB Max Output Noise - VIN = VINMIN, IL = 0.75*ILmax 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VAUDIOON -114 -124 -129 dBV/√Hz Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VAUDIOtON - - 1.0 ms Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VAUDIOtOFF 0.1 - 10 ms Transient Load Response - See Transient Waveforms on page 84, VIN = VINMIN, VINMAX VAUDIOTLOR - 1.0 2.0 Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VAUDIOTLIR - 5.0 8.0 mV VPLL AND VDIG ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = UVDET VIN = VNOM + 1.0 V, > UVDET VPLLPSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1 kHz – 1.0 MHz VPLLON 2.5 dB/dec µV/√Hz Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VPLLtON - - 100 µs Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VPLLtOFF 0.1 - 10 ms values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 13892 DYNAMIC ELECTRICAL CHARACTERISTICS VPLL AND VDIG ACTIVE MODE - AC (CONTINUED) Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX VPLLTLOR, VDIGTLOR - 50 70 mV Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VPLLTLIR, VDIGTLIR - 5.0 8.0 mV VIOHI ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV, > UVDET VIN = VNOM + 1.0 V, > UVDET VIOHIPSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VIOHION 1.0 dB/dec µV/√Hz Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VIOHItON - - 1.0 ms Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VIOHItOFF 0.1 - 10 ms Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX VIOHITLOR - 1.0 2.0 Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VIOHITLIR - 5.0 8.0 mV Mode Transition Time - See Transient Waveforms on page 84 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP VIOHIMTR - - 10 µs Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VIOHIMTR - 1.0 2.0 VCAM ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VCAMPSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VCAMON 1.0 dB/dec µV/√Hz Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) VCAMtON - - 1.0 ms Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) VCAMtOFF 0.1 - 10 ms Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX VCAM = 01, 10, 11 VCAM = 00 VCAMLOR 1.0 2.0 mV Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VCAMLIR - 5.0 8.0 mV values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS VCAM ACTIVE MODE - AC (CONTINUED) Mode Transition Time - See Transient Waveforms on page 84 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP VCAMtMOD - - 100 µs Mode Transition Response From low power to active and from, active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VCAMMTR - 1.0 2.0 VSD ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VSDPSSR dB Max Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VSDON -115 -126 -132 dBV/√Hz Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) VSDtON - - 1.0 ms Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) VSDtOFF 0.1 - 10 ms Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX - VSD[2:0] = 010 to 111 - VSD[2:0] = 000 to 001 VSDTLOR 1.0 2.0 mV Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VSDTLIR - 5.0 8.0 mV Mode Transition Time - See Transient Waveforms on page 84 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP VSDtMOD - - 100 µs Mode Transition Response - See Transient Waveforms on page 84 From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VSDMTR - 1.0 2.0 VUSB ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VUSBPSSR 35 40 - dB Max Output Noise - VIN = VINMIN, IL = 75% of ILMAX

100 Hz – 50 kHz

50 kHz – 1.0 MHz VUSBON 1.0 0.2 µV/√Hz VUSB2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VUSB2PSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VUSB2ON 0.2 dB/dec µV/√Hz

values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 29 13892 DYNAMIC ELECTRICAL CHARACTERISTICS VUSB2 ACTIVE MODE - AC (CONTINUED) Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VUSB2tON - - 100 µs Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VUSBtOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VUSB2OS - 1.0 2.0 Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX VUSB2TLOR - 1.0 2.0 Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VUSB2TLIR - 5.0 8.0 mV UVBUS ACTIVE MODE DC Turn-on Time VBUS Rise Time per USB OTG with max loading of 6.5 µF+10 µF UVBUStON - - 100 ms Turn-off Time Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD, VIN = VINMIN, VINMAX, IL = 0 UVBUStOFF - - 1.3 sec VGEN1 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = UVDET VIN = VNOM + 1.0 V, > UVDET VGEN1PSSR dB Max Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VGEN1ON -115 -126 -132 dBV/√Hz Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 VGEN1tON - - 1.0 ms Turn-off Time Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 VGEN1tOFF 0.1 - 10 ms Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX - VGEN1[1:0] = 10 to 11 - VGEN[1:0] = 00 to 01 VGEN1TLOR 1.0 3.0 mV Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VGEN1TLIR - 5.0 8.0 mV Mode Transition Time - See Transient Waveforms on page 84 From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN1tMOD - - 100 µs Mode Transition Response - See Transient Waveforms on page 84 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN1MTR - 1.0 2.0 values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS VGEN2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VGEN2PSSR dB Max Output Noise - VIN = VINMIN, IL = ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VGEN2ON -115 -126 -132 dBV/√Hz Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 VGEN2tON - - 1.0 ms Turn-off Time (Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0) VGEN2tOFF 0.1 - 10 ms Transient Load Response - See Transient Waveforms on page 84 VIN = VINMIN, VINMAX - VGEN2[2:0] = 100 to 111 - VGEN2[2:0] = 000 to 011 VGEN2TLOR 1.0 3.0 mV Transient Line Response - See Transient Waveforms on page 84 IL = 75% of ILMAX VGEN2TLIR - 5.0 8.0 mV Mode Transition Time - See Transient Waveforms on page 84 From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN2tMOD - - 100 µs Mode Transition Response - See Transient Waveforms on page 84 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN2MTR - 1.0 2.0 VGEN3 ACTIVE MODE - AC PSRR IL = 75% of ILMAX, 20 Hz to 20 kHz, VIN = VINMIN +100 mV VIN = VNOM+1.0 V VGEN3PSSR dB Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VGEN3ON 1.0 dB/dec µV/√Hz Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 VGEN3tON - - 1.0 ms Turn-off Time Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 VGEN3tOFF 0.1 - 5.0 ms Transient Load Response VIN = VINMIN, VINMAX - VGEN3 = 1 - VGEN3 = 0 VGEN3TLOR 1.0 2.0 mV Transient Line Response (IL = 75% of ILMAX) VGEN3TLIR - 5.0 8.0 mV values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 31 13892 DYNAMIC ELECTRICAL CHARACTERISTICS VGEN3 ACTIVE MODE - AC (CONTINUED) Mode Transition Time From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN3tMOD - - 100 µs Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN3MTR - 1.0 2.0 UVBUS - ACTIVE MODE DC Turn-on Time - VBUS Rise Time por USB OTG with max loading of 6.5 µF+10 µF - - 100 ms Turn-off Time - Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD VIN = VINMIN, VINMAX, IL=0 - - 1.3 sec ADC Conversion Time per Channel - PLLX[2:0] = 100 10 µs Turn On Delay If Switcher PLL was active If Switcher PLL was inactive µs TOUCH SCREEN Turn-on Time - 90% of output 500 µs values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CHARGER CHRGRAW 1. Charger input. The charger voltage is measured through an ADC at this pin. The UVBUS pin must be shorted to CHRGRAW in cases where the charger is being supplied from the USB cable. The minimum voltage for this pin depends on BATTMIN threshold value (see Battery Interface and Control). 2. Output to battery supplied accessories. The battery voltage can be applied to an accessory by enabling the charge path for the accessory via the CHRGRAW pin. To accomplish this, the charger needs to be configured in reverse supply mode. CHRGCTRL1 Driver output for charger path FET M1. CHRGCTRL2 Driver output for charger path FET M2. CHRGISNS Charge current sensing point 1. The charge current is read by monitoring the voltage drop over the charge current 100 mΩ sense resistor connected between CHRGISNS and BPSNS. BPSNS 1. BP sense point. BP voltage is sensed at this pin and compared with the voltage at CHRGRAW. 2. Charge current sensing point 2. The charge current is read by monitoring the voltage drop over the charge current 100 mΩ sense resistor. This resistor is connected between CHRGISNS and BPSNS. BP This pin is the application supply point, the input supply to the IC core circuitry. The application supply voltage is sensed through an ADC at this pin. BATTFET Driver output for battery path FET M3. If no charging system is required or single path is implemented, the pin BATTFET must be floating. BATTISNS Battery current sensing point 1. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. BATT Battery positive terminal. Battery current sensing point 2. The supply voltage of the battery is sensed through an ADC on this pin. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. BATTISNSCC Accumulated current counter current sensing point. This is the coulomb counter current sense point. It should be connected directly to the 0.020 Ω sense resistor via a separate route from BATTISNS. The coulomb counter monitors the current flowing in/ out of the battery by integrating the voltage drop over the BATTISNCC and the BATT pin.

Analog Integrated Circuit Device Data Freescale Semiconductor 33 13892 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CFP AND CFM Accumulated current filter cap plus and minus terminals respectively. The coulomb counter will require a 10 µF output capacitor connected between these pins to perform a first order filtering of the signal across R1. CHRGSE1B An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB, it can be left open since it is internally pulled up to VCORE. The recommendation is to place an external FET that can pull it low or left it open, depending on the charge method. CHRGLED Trickle LED driver output 1. Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. This LED is to be connected between this pin and CHRGRAW. GNDCHRG Ground for charger interface. LEDR, LEDG AND LEDB General purpose LED driver output Red, Green and Blue respectively. Each channel provides flexible LED intensity control. These pins can also be used as general purpose open drain outputs for logic signaling, or as generic PWM generator outputs. GNDLED Ground for LED drivers IC CORE VCORE Regulated supply output for the IC analog core circuitry. It is used to define the PUMS VIH level during initialization. The bandgap and the rest of the core circuitry are supplied from VCORE. Place a 2.2 μF capacitor from this pin to GNDCORE. VCOREDIG Regulated supply output for the IC digital core circuitry. No external DC loading is allowed on VCOREDIG. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Place a 2.2 μF capacitor from this pin to GNDCORE. REFCORE Main bandgap reference. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. No external DC loading is allowed on REFCORE. Place a 100 nF capacitor from this pin to GNDCORE. GNDCORE Ground for the IC core circuitry. POWER GATING PWGTDRV1 AND PWGTDRV2 Power Gate Drivers. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In typical applications, SW1, SW2, and SW3 will both be kept active for the processor modules in state retention, and SW4 retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to isolate the maintained supply domains from any peripheral loading.

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION SWITCHERS SW1IN, SW2IN, SW3IN AND SW4IN Switchers 1, 2, 3, and 4 input. Connect these pins to BP to supply Switchers 1, 2, 3, and 4. SW1FB, SW2FB, SW3FB AND SW4FB Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4 output voltage sense respectively. Connect these pins to the farther point of each of their respective SWxOUT pin, in order to sense and maintain voltage stability. SW1OUT Switcher 1 output. Buck switcher for processor core(s). GNDSW1 Ground for Switcher 1. SW2OUT Switcher 2 output. Buck switcher for processor SOG, etc. GNDSW2 Ground for Switcher 2. SW3OUT Switcher 3 output. Buck switcher for internal processor memory and peripherals. GNDSW3 Ground for switcher 3. SW4OUT Switcher 4 output. Buck switcher for external memory and peripherals. GNDSW4 Ground for switcher 4. DVS1 AND DVS2 Switcher 1 and 2 DVS input pins. Provided for pin controlled DVS on the buck switchers targeted for processor core supplies. The DVS pins may be reconfigured for Switcher Increment / Decrement (SID) mode control. When transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mV per time step. These pins must be set high in order for the DVS feature to be enabled for each of switchers 1 or 2, or low to disable it. SWBSTIN Switcher BST input. The 2.2 μH switcher BST inductor must be connected here. SWBSTOUT Power supply for gate driver for the internal power NMOS that charges SWBST inductor. It must be connected to BP. SWBSTFB Switcher BST feedback. When SWBST is configured to supply the UVBUS pin in OTG mode the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. GNDSWBST Ground for switcher BST.

Analog Integrated Circuit Device Data Freescale Semiconductor 35 13892 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION REGULATORS VINIOHI Input of VIOHI regulator. Connect this pin to BP in order to supply VIOHI regulator. VIOHI Output regulator for high voltage IO. Fixed 2.775 V output for high voltage level interface. VINPLL AND VINDIG The input of the regulator for processor PLL and Digital regulators respectively. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail, such as from SW4 for the two lower set points of each regulator (the 1.2 1.8V outputs for VPLL, and 1.65 and 1.8V for VDIG), they can be connected to either BP or a 2.2V nominal external switched mode power supply rail, to improve power dissipation. VPLL Output of regulator for processor PLL. Quiet analog supply (PLL, GPS). VDIG Output regulator Digital. Low voltage digital (DPLL, GPS). VVIDEODRV Drive output for VVIDEO external PNP transistor. VVIDEO Output regulator TV DAC. This pin must be connected to the collector of the external PNP transistor of the VVIDEO regulator. VINAUDIO Input regulator VAUDIO. Typically connected to BP. VAUDIO Output regulator for audio supply. VINUSB2 Input regulator VUSB2. This pin must always be connected to BP even if the regulators are not used by the application. VUSB2 Output regulator for powering USB PHY. VINCAMDRV 1. Input regulator camera using internal PMOS FET. Typically connected to BP. 2. Drive output regulator for camera voltage using external PNP device. In this case, this pin must be connected to the base of the PNP in order to drive it. VCAM Output regulator for the camera module. When using an external PNP device, this pin must be connected to its collector. VSDDRV Drive output for the VSD external PNP transistor. VSD Output regulator for multi-media cards such as micro SD, RS-MMC.

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION VGEN1DRV Drive output for the VGEN1 external PNP transistor. VGEN1 Output of general purpose 1 regulator. VGEN2DRV Drive output for the VGEN2 external PNP transistor. VGEN2 Output of general purpose 2 regulator. VINGEN3DRV 1. Input for the VGEN3 regulator when no external PNP transistor used. Typically connected to BP. 2. Drive output for VGEN3 in case an external PNP transistor is used on the application. In this case, this pin must be connected the base of the PNP transistor. VGEN3 Output of general purpose 3 regulator. VSRTC Output regulator for the SRTC module on the processor. The VSRTC regulator provides the CLK32KMCU output level (1.2 V). Additionally, it is used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. GNDREG1 Ground for regulators 1. GNDREG2 Ground for regulators 2. GNDREG3 Ground for regulators 3. GENERAL OUTPUTS GPO1 General purpose output 1. Intended to be used for battery thermistor biasing. In this case, connect a 10 KΩ resistor from GPO1 to ADIN5, and one from ADIN5 to GND. GPO2 General purpose output 2. GPO3 General purpose output 3. GPO4 General purpose output 4. It can be configured for a muxed connection into Channel 7 of the GP ADC.

Analog Integrated Circuit Device Data Freescale Semiconductor 37 13892 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CONTROL LOGIC LICELL Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This pin also works as a current-limited voltage source for battery charging. A small capacitor should be placed from LICELL to ground under all circumstances. XTAL1 32.768 kHz Oscillator crystal connection 1. XTAL2 32.768 kHz Oscillator crystal connection 2. GNDRTC Ground for the RTC block. CLK32K 32 kHz Clock output for peripherals. At system start-up, the 32 kHz clock is driven to CLK32K (provided as a peripheral clock reference), which is referenced to SPIVCC. The CLK32K is restricted to state machine activation in normal on mode. CLK32KMCU 32 kHz Clock output for processor. At system start-up, the 32 kHz clock is driven to CLK32KMCU (intended as the CKIL input to the system processor) referenced to VSRTC. The driver is enabled by the start-up sequencer and the CLK32KMCU is programmable for Low Power Off mode control by the state machine. RESETB AND RESETBMCU Reset output for peripherals and processor respectively. These depend on the Power Control Modes of operation (See Functional Device Operation on page 41). These are meant as reset for the processor, or peripherals in a power up condition, or to keep one in reset while the other is up and running. WDI Watchdog input. This pin must be high to stay in the On mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW4 = 1.8 V). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration). STANDBY AND STANDBYSEC Standby input signal from processor and from peripherals respectively. To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it. This is referred to as a Standby event. The Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarities associated with each pin. Since the Standby pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. The state of the Standby pins only have influence in the On mode and are therefore ignored during start up and in the Watchdog phase. This allows the system to power up without concern of the required Standby polarities, since software can make adjustments accordingly, as soon as it is running. INT Interrupt to processor. Unmasked interrupt events are signaled to the processor by driving the INT pin high.

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FUNCTIONAL PIN DESCRIPTION PWRON1, 2 AND 3 A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the 13892, so that it is in effect a parallel path for the power key. In addition to the turn on event, the 13892A/B versions include a global reset feature on the PWRON3 pin. The 13892A version has the global reset feature enabled by default. The 13892B version has the global reset feature disabled by default, but can be enabled by setting the SPI bit GLBRSTENB = 0. The global reset feature powers down the part, disables the charger, resets the SPI registers to their default value and then powers back on. To enable a global reset the PWRON3 pin needs to be pulled low for greater than 12 seconds and then pulled back high. If the PWRON3 pin is held low for less than 12 seconds the pin will act as a normal PWRON pin. PUMS1 AND PUMS2 Power up mode supply setting. Default start-up of the device is selectable by hardwiring the Power Up Mode Select pins. The Power Up Mode Select pins (PUMS1 and PUMS2) are used to configure the start-up characteristics of the regulators. Supply enabling and output level options are selected by hardworking the PUMS pins for the desired configuration. MODE USB LBP mode, normal mode, test mode selection & anti-fuse bias. During evaluation and testing, the IC can be configured for normal operation or test mode via the MODE pin as summarized in the following table. GNDCTRL Ground for control logic. SPIVCC Supply for SPI bus and audio bus CS CS held low at Cold Start configures the interface for SPI mode. Once activated, CS functions as the SPI Chip Select. CS tied to VCORE at Cold Start configures the interface for I2C mode; the pin is not used in I2C mode other than for configuration. Because the SPI interface pins can be reconfigured for reuse as an I2C interface, a configuration protocol mandates that the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). CLK Primary SPI clock input. In I2C mode, this pin is the SCL signal (I2C bus clock). MOSI Primary SPI write input. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses (A0 address selection). MISO Primary SPI read output. In I2C mode, this pin is the SDA signal (bi-directional serial data line). GNDSPI Ground for SPI interface. MODE PIN STATE MODE Ground Normal Operation VCOREDIG USB Low Power Boot Allowed VCORE Test Mode

Analog Integrated Circuit Device Data Freescale Semiconductor 39 13892 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION USB UID This pin identifies if a mini-A or mini-B style plug has been connected to the application. The state of the ID detection can be read via the SPI, to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin. UVBUS 1. USB transceiver cable interface. 2. OTG supply output. When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will switch to sense the UVBUS pin instead of the SWBSTFB pin. VUSB This is the regulator used to provide a voltage to an external USB transceiver IC. VINUSB Input option for VUSB; supplied by SWBST. This pin is internally connected to the UVBUS pin for OTG mode operation (for more details about OTG mode). Note: When VUSBIN = 1, UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270 μA maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled. VBUSEN External VBUS enable pin for the OTG supply. VBUS is defined as the power rail of the USB cable (+5.0 V). A TO D CONVERTER Note: The ADIN5/6/7 inputs must not exceed BP. ADIN5 ADC generic input channel 5. ADIN5 may be used as a general purpose unscaled input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor must be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, in particular when the thermistor check function is used. ADIN6 ADC generic input channel 6. ADIN6 may be used as a general purpose unscaled input, but in a typical application, the PA thermistor is connected here. ADIN7 ADC generic input channel 7, group 1. ADIN7 may be used as a general purpose unscaled input or as a divide by 2 scaled input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available on channel 7. This input is muxed on the GPO4 pin. In the application, a second ambient light sensor is supposed to be connected here. TSX1 AND TSX2, TSY1 AND TSY2 - Note: The TS[xy] [12] inputs must not exceed BP or VCORE. Touch Screen Interfaces X1 and X2, Y1 and Y2. The touch screen X plate is connected to TSX1 and TSX2, while the Y plate is connected to Y1 and Y2. In inactive mode, these pins can also be used as general purpose ADC inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Y-plate is connected to ground (TSY1).

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FUNCTIONAL PIN DESCRIPTION TSREF Touch Screen Reference regulator. This regulator is powered from VCORE. In applications not supporting touch screen, the TSREF can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted. ADTRIG ADC trigger input. A rising edge on this pin will start an ADC conversion. GNDADC Ground for A to D circuitry. THERMAL GROUNDS GNDSUB1-9 General grounds and thermal heat sinks.

details for each interface mode follow in this chapter. information on external signals. the bus configuration will be latched for SPI mode. addressable register map spans 64 registers of 24 data bits each. accessible by either interface. Table 7. SPI / I2C Bus Configuration

1. CS held low at Cold Start configures interface for SPI m ode; once activated, CS functions as the SPI Chip Select.
2. CS tied to VCORE at Cold Start configures interface for I2 C mode; the pin is not used in I2C mode other than for configuration.
3. In I2C mode, the MOSI pin hardwired to ground or VCORE is used to select between two possible addresses.

Table 8. Register Set

0 Interrupt Status 0 16 Unused 32 Regulator Mode 0 48 Charger 0

1 Interrupt Mask 0 17 Unused 33 Regulator Mode 1 49 USB0

2 Interrupt Sense 0 18 Memory A 34 Power Miscellaneous 50 Charger USB1

3 Interrupt Status 1 19 Memory B 35 Unused 51 LED Control 0

4 Interrupt Mask 1 20 RTC Time 36 Unused 52 LED Control 1

5 Interrupt Sense 1 21 RTC Alarm 37 Unused 53 LED Control 2

6 Power Up Mode Sense 22 RTC Day 38 Unused 54 LED Control 3

7 Identification 23 RTC Day Alarm 39 Unused 55 Unused

8 Unused 24 Switchers 0 40 Unused 56 Unused

9 ACC 0 25 Switchers 1 41 Unused 57 Trim 0

10 ACC 1 26 Switchers 2 42 Unused 58 Trim 1

11 Unused 27 Switchers 3 43 ADC 0 59 Test 0

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The SPI interface is comprised of the package pins listed in Table 9. the 64 data fields and one write enable bit to select whether the SPI transaction is a read or a write. The register set will be to a large extent compatible with the MC13783 in order to facilitate software development. write bit if this is to be a read command only. go active again. The MISO line will be tri-stated while CS is low. Figure 5. SPI Transfer Protocol Single Read/Write Access

12 Unused 28 Switchers 4 44 ADC 1 60 Test 1

13 Power Control 0 29 Switchers 5 45 ADC 2 61 Test 2

14 Power Control 1 30 Regulator Setting 0 46 ADC 3 62 Test 3

15 Power Control 2 31 Regulator Setting 1 47 ADC4 63 Test 4

Table 9. SPI Interface Pin Description

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Table 10. SPI Interface Timing Specifications

1. This table reflects a maximum SPI clock frequency of 26 MHz

Table 11. SPI Interface Logic IO Specifications

Analog Integrated Circuit Device Data Freescale Semiconductor 45 13892 FUNCTIONAL DEVICE OPERATION I2C INTERFACE I2C INTERFACE I2C CONFIGURATION When configured for I2C mode (see Table 7) the interface may be used to access the complete register map previously described for SPI access. The MC13892 can function only as an I2C slave device, not as a host. I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus conflict avoidance, pin programmable selection is provided through the MOSI pin to allow configuration for the address LSB(s). This product supports 7-bit addressing only; support is not provided for 10-bit or General Call addressing. The I2C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s operation. Timing diagrams, electrical specifications, and further details can be found in the I2C specification. Standard I2C protocol utilizes packets of 8 bits (bytes), with an acknowledge bit (ACK) required between each byte. However, the number of bytes per transfer is unrestricted. The register map of the MC13892 is organized in 24 bit registers which corresponds to the 24 bit words supported by the SPI protocol of this product. To ensure that the I2C operation mimics SPI transactions in behavior of a complete 24 bit word being written in one transaction, software is expected to perform write transactions to the device in 3 byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third consecutive byte. Failure to complete a 3 byte write sequence will abort the I2C transaction and the register will retain its previous value. This could be due to a premature STOP command from the master. I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and 3 bytes will be sent out, unless a STOP command or NACK is received prior to completion. The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the transaction. I2C DEVICE ID The I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product supports 7-bit addressing only. Support is not provided for 10-bit or General Call addressing. Because the MOSI pin is not utilized for I2C communication, it is reassigned for pin programmable address selection by hardwiring to VCORE or GND at the board level, when configured for I2C mode. MOSI will act as Bit 0 of the address. The I2C address assigned to FSL PM ICs (shared amongst our portfolio) is as follows: 00010-A1-A0, where the A1 and A0 bits are allowed to be configured for either 1 or 0. It is anticipated for a maximum of two FSL PM ICs on a given board, which could be sharing an I2C bus. The A1 address bit is internally hardwired as a “0”, leaving the LSB A0 for board level configuration. The A1 bit will be implemented such that it can be re-wired as a “1” (with a metal change or fuse trim), if conflicts are encountered before the final production material is manufactured. The designated address is defined as: 000100-A0. I2C OPERATION The I2C mode of the interface is implemented, generally following the Fast mode definition, which supports up to 400 kbits/s operation. The exceptions to the standard are noted to be 7-bit only addressing, and no support for General Call addressing. Timing diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at: http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf Standard I2C protocol utilizes bytes of 8 bits, with an acknowledge bit (ACK) required between each byte. However, the number of bytes per transfer are unrestricted. The register map is organized in 24 bit registers, which corresponds to the 24 bit words supported by the SPI protocol of this product. To ensure that I2C operation mimics SPI transactions in behavior of a complete 24 bit word being written in one transaction. The software is expected to perform write transactions to the device in 3 byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third consecutive byte. Failure to complete a 3 byte write sequence will abort the I2C transaction, and the register will retain its previous value. This could be due to a premature STOP command from the master, for example. I2C read operations are also performed in byte

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command or NACK is received prior to completion. Figure 8. I2C 3 Byte Write Example Figure 9. I2C 3 Byte Read Example

to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I2C. to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high. interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking. The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. period before an interrupt is generated. descriptions, refer to the related chapters. Table 12. Interrupt, Mask and Sense Bits BPONI BPONM BPONS BP turn on threshold detection.

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Additional sense bits are available to reflect the state of the power up mode selection pins, as summarized in Table 13.

1. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Power Control System for details.

The 13892 parts can be identified though identification bits which are hardwired on chip. of the 13892. The bits are set to ICID[2:0] = 111 and are located in the revision register. revision, where bits REV[2:0] track the metal revisions. These bits are hardwired. The bits FIN[3:0] are Freescale use only and are not to be explored by the application. Generation and Real Time Clock. Table 13. Additional Sense Bits Table 14. IC Revision Bit Assignment

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The 13892 generates a 32.768 kHz clock as well as several 32.768 kHz derivative clocks that are used internally for control. CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented. external 32.768 kHz crystal is not present. supplied from the coin cell battery until the coin cell is depleted. the startup sequencer, and CLK32KMCU is programmable for Low Power Off mode, controlled by the state machine. on RTCPORB, to ensure the buffer is activated at the first power up and configured as desired for subsequent power ups. CLK32K is restricted to state machine activation in normal On mode. transition, for example, due to a sag in the switchover output voltage, or absence of a signal on the clock output pins. and an interrupt will be generated if the corresponding CLKM mask bit is cleared. equivalent (such as Micro Crystal CC5V-T1A or Epson FC135). applying an external source, the XTAL2 pin is to be connected to VCOREDIG. Table 15. RTC Crystal Specifications

The guidelines below may prove to be helpful in providing a crystal oscillator that starts reliably and runs with minimal jitter. and good PCB manufacturing processes should be maintained. load capacitance leads and the RTC Ground must form a minimal loop area. composed out of the load capacitance, the effective input capacitance at each pin, plus the PCB stray capacitance for each pin. providing a VSRTC voltage to bias the SRTC module of the processor, as well as a CLK32KMCU at the VSRTC output level. internal MEMHOLD PCUT modes. Table 16. Crystal Oscillator Main Characteristics

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Figure 10. SRTC block diagram conserve current drain by setting the RTCDIS bit to a 1 (defaults on at power up). Table 17. VSRTC Specifications

in DAYA, the TODAI interrupt will be generated. oscillator as defined in Table 18. counter. Therefore, the frequency at the clock outputs CLK32K and CLK32KMCU are not affected. The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode. Table 18. RTC Calibration Settings Table 19. RTC Calibration Enabling

00 RTC Calibration disabled (default)

01 RTC Calibration enabled in all modes except coin cell only

10 Reserved for future use. Do not use.

11 RTC Calibration enabled in all modes

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have not skewed the clock beyond desired tolerances. capacitor should be placed from LICELL to ground under all circumstances. conditions as for initial insertion. charge current is fixed at ICOINHI. be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs. Table 20. Coin cell Charger Voltage Specifications Table 21. Coin cell Charger Specifications

uses on chip signals and detector outputs. Table 22 gives a listing of the principal elements of this interface. Table 22. Power Control System Interface Signals

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Figure 11. Power Control State Machine Flow Diagram

Analog Integrated Circuit Device Data Freescale Semiconductor 57 13892 FUNCTIONAL DEVICE OPERATION OPERATING MODES POWER CONTROL MODES DESCRIPTION Following are text descriptions of the power states of the system, which give additional details of the state machine, and complement Figure 11. Note that the SPI control is only possible in the Watchdog, On, and User Off Wait states, and that the interrupt line INT is kept low in all states except for Watchdog and On. Off If the supply at BP is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered, all other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode. If the supply at BP is below the UVDET threshold no turn on events are accepted. If a valid coin cell is present, the core gets powered from LICELL. The only active circuitry is the RTC module, with BP greater than UVDET detection, and the SRTC support circuitry, if so configured. Cold Start Entered upon a Turn On event from Off, Warm Boot, successful PCUT, or Silent System Restart. The switchers and regulators are powered up sequentially to limit the inrush current. See the Power Up section for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering a Cold Start. When expired, the Cold Start state is exited for the Watchdog state, and both RESETB and RESETBMCU become high (open drain output with external pull ups). The input control pins WDI, and STANDBYx are ignored. Watchdog The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBYx are ignored while in the Watchdog state. On The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode. The WDI IO supply voltage is referenced to SPIVCC (Normally connected to SW4). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration. Refer to the section on Silent System Restart with WDI Event for details). User Off Wait The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for User Off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power key. Upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off. The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks. When expired, the Wait mode is exited for User Off mode or Memory Hold mode, depending on warm starts being enabled or not via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low. Memory Hold and User Off (Low Power Off states) As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state retention (User Off only). The switcher mode control bits allow selective powering of the buck switchers for optimizing the supply behavior in the Low Power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, and Turn On event detection are maintained). Memory Hold RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled. If DRM is set, the CLK32KMCU is kept active. To ensure that SW1, SW2, and SW3 shut off in Memory Hold, appropriate mode settings should be used such as SW1MHMODE = SW2MHMODE = SW3MHMODE = 0 (refer to the mode control description later in this chapter). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.

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FUNCTIONAL DEVICE OPERATION OPERATING MODES Any peripheral loading on SW4 should be isolated from the SW4 output node by the PWGT2 switch, which opens in both low power off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the memory subsystem. Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and an the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this mode. Buck switchers that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when coming out of MEMHOLD and entering a Warm Boot. The switchers will be reconfigured for their default settings as selected by the PUMS pin in the normal time slot that would affect them. User Off RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled. CLK32KMCU (connected to the processor's CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1, and/or SW2, and/or SW3 supply domains can be configured for SWxUOMODE = 1 to keep them powered through the User Off event. If one of the switchers can be shut down on in User Off, its mode bits would typically be set to 0. Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens in both Low Power Off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the processor core. Since power is maintained for the core (which is put into its lowest power state) and since MCU RESETBMCU does not trip, the processor's state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used for very low frequency / low power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a turn on event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode. Warm Start Entered upon a Turn On event from User Off. The switchers and regulators are powered up sequentially to limit the inrush current; see the Power Up section for sequencing and default level details. If SW1, SW2, SW3, and/or SW4 were configured to stay on in User Off mode, they will not be turned off when coming out of User Off and entering a Warm Start. The buck switchers will be reconfigured for their default settings as selected by the PUMS pin in the respective time slot defined in the sequencer selection. RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if enabled via the SPI. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high. Internal MemHold Power Cut Refer to the next section for details about Power Cuts and the associated state machine response. POWER CUT DESCRIPTION When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. The maximum duration of a power cut is determined by the PCUT timer PCT[7:0] preset via SPI. When a PCUT occurs, the PCUT timer will internally be decremented till it expires, meaning counted down to zero. The contents of PCT[7:0] does not reflect the actual count down value but will keep the programmed value and therefore does not have to be reprogrammed after each power cut. If power is not reestablished above BPON before the PCUT timer expires, the state machine transitions to the Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT. Upon re-application of power before expiration (an “successful PCUT”, defined as BP first rising above the UVDET threshold and then above the BPON threshold before the PCUT timer expires), a Cold Start is engaged.

Analog Integrated Circuit Device Data Freescale Semiconductor 59 13892 FUNCTIONAL DEVICE OPERATION OPERATING MODES In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by software. The PCI interrupt is cleared by software or when cycling through the Off state. Because the PCUT system quickly disables all of the power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current through the battery and trace impedances can once again cause the BP node to drop below UVDET. This chain of cyclic power down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. First, the successful recovery out of a PCUT requires the BP node to rise above BPON, providing hysteretic margin from the UVDET threshold. Secondly, the number of times the PCUT mode is entered is counted with the counter PCCOUNT[3:0], and the allowed count is limited to PCMAXCNT[3:0] set through the SPI. When the contents of both become equal, then the next PCUT will not be supported and the system will go to Off mode. After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor reassumes control), software should clear the PCCOUNT[3:0] counter. Counting of PCUT events is enabled via the PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not enabled, in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB=1 (see the Silent Restart from PCUT Event section later in this chapter). Internal MemHold Power Cut As described above, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply the MC13892 core along with the 32 kHz crystal oscillator, the RTC system and coin cell backed up registers. All regulators and switchers will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start. If the PCT timer expires before power is reestablished, the system transitions to the Off state and awaits a sufficient supply recovery. SILENT RESTART FROM PCUT EVENT If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent restart, so the system is reinitialized without alerting the user. This can be configured by setting the PCUTEXPB bit to a “1” at booting or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and PCUTEXPB is still a “1”, then the state machine has not transitioned through Off, which confirms that the PCT timer has not expired during the PCUT event (i.e., a successful power cut). In case of a successful power cut, a silent restart may be appropriate. If PCUTEXPB is found to be a “0” after the Cold Start where PCI is found to be a “1”, then it is inferred that the PCT timer has expired before power was reestablished, flagging an unsuccessful power cut or first power up, so the startup user greeting may be desirable for playback. SILENT SYSTEM RESTART WITH WDI EVENT A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset, but it is desired to make the reset a silent event so as to happen without end user awareness. The default response to WDI going low is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine will go to Cold Start without passing through Off mode A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is unrelated to PCUTs, but it shares the PCUT counter so that the number of silent system restarts can be limited by the programmable PCMAXCNT counter. When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, the software can detect a silent system restart, if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine that an inconspicuous restart without showing may be more appropriate than launching into the welcoming routine. A PCUT event does not trip the WDIRESETI bit.

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• - Power down
• - Disable the charger
• - Reset the registers all the registers including the RTCPORB registers
• - Power back up after the difference between the 12 sec timer, and when the user releases the button as the power off time (for example, if the power button was held for 12.1 s, then the time that the IC would be off would be only 100 mS) If PWRON3 is held low for less than 12 seconds, it will act as a normal PWRON pin. This feature is enabled by default in the 13892A, and disabled by default in 13892B. CLK32KMCU CLOCK DRIVER CONTROL THROUGH STATES As described previously, the clocking behavior is influenced by the state machine is in and the setting of the clocking related SPI bits. A summary is given in Table 23 for the clock output CLK32KMCU. TURN ON EVENTS When in Off mode, the MC13892 can be powered on via a Turn On event. The Turn On events are listed in Table 24. To indicate to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events. Masking the interrupts related to the turn on events will not prevent the part to turn on, except for the time of day alarm. Power Button Press PWRON1, PWRON2, or PWRON3 pulled low with corresponding interrupts and sense bits PWRON1I, PWRON2I, or PWRON3I, and PWRON1S, PWRON2S, or PWRON3S. A power on/off button is connected here. The PWRONx can be hardware debounced through a programmable debouncer PWRONxDBNC[1:0] to avoid the application to power up upon a very short key press. In addition, a software debounce can be applied. BP should be above UVDET. The PWRONxI interrupt is generated for both the falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The PWRONxI interrupt is cleared by software or when cycling through the Off mode.

Table 23. CLK32MCU Control Logic Table

1 X X Enabled

0 X 0 Disabled

1 X X Enabled0 1 1

Table 24. PWRONx Hardware Debounce Bit Settings

1. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin

Analog Integrated Circuit Device Data Freescale Semiconductor 61 13892 FUNCTIONAL DEVICE OPERATION OPERATING MODES Charger Attach CHRGRAW is pulled high with corresponding interrupt and sense bits CHGDETI and CHGDETS. This is equivalent to plugging in a charger. BP should be above BPON. The charger turn on event is dependent on the charge mode selected. For details on the charger detection and turn on, see Battery Interface and Control. Battery Attach BP crossing the BPON threshold which corresponds to attaching a charged battery to the product. A corresponding BPONI interrupt is generated, which can be cleared by software or when cycling through the Off mode. Note that BPONI is also generated after a successful power cut and potentially when applying a charger. USB Attach VBUS pulled high with corresponding interrupt and sense bits BVALIDI and BVALIDS. This is equivalent to plugging in a USB cable. BP should be above BPON and the battery voltage above BATTON. For details on the USB detection, see Connectivity. RTC Alarm TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset time. BP should be above BPON. For details and related interrupts, see Clock Generation and Real Time Clock. System Restart System restart may occur after a system reset. This is an optional function, see also the following Turn Off events section. BP should be above BPON. TURN OFF EVENTS Power Button Press User shut down of a product is typically done by pressing the power button connected to the PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off by the processor's response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore under normal circumstances not considered as a turn off event for the state machine. Note that software can configure a user initiated power down via a power button press for transition to a low power off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state. Power Button System Reset A secondary application of the PWRON pin is the option to generate a system reset. This is recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the PWRONxRSTEN bits. When enabled, a 4 second long press on the power button will cause the device to go to the Off mode and as a result the entire application will power down. An SYSRSTI interrupt is generated upon the next power up. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. Thermal Protection If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling sufficiently to accept a Turn On event. There are no specific interrupts related to this other than the warning interrupts. Under-Voltage Detection When the voltage at BP drops below the under-voltage detection threshold UVDET, the state machine will transition to Off mode if PCUT is not enabled, or if the PCT timer expires when PCUT is enabled. TIMERS The different timers as used by the state machine are in Table 25. This listing does not include RTC timers for timekeeping. A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous event. The duration listed below is therefore the effective minimum time period.

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A Turn On event timing diagram example shows in Figure 12. Figure 12. Power Up Timing Diagram at BP is masked while the power up sequencer is running. VCOREDIG to 10, and VCORE to 11. core(s) to startup before any peripheral loading is introduced. Table 25. Timer Main Characteristics

The power up sequence is shown in Table 27. VCOREDIG, VSRTC, and VCORE are brought up in the pre-sequencer startup. Table 26. Power Up Defaults Table

1. The switchers SWx are activated in PWM pulse skipping mode, but allowed when enabled by the startup sequencer.
2. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS.
3. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1,

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The voltage at BPSNS and BP is monitored by detectors as summarized in Table 28. sense bits are coded in line with previous generation parts. Table 27. Power Up Sequence

0 SW2 SW2

1 SW4 VGEN2

2 VIOHI SW4

3 VGEN2 VIOHI, VSD

4 SW1 SWBST, VUSB (44)

5 SW3 SW1

6 VPLL VPLL

7 VDIG SW3

9 VUSB (43), VUSB2 VUSB2

1. Time slots may be included for blocks which are def ined by the PUMS pin as disabled to allow for
2. The following supplies are not included in the matrix since they are not intended for activation by the
3. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS.
4. SWBST = 5.0 V powers up and so does VUSB regardless of 5.0 V present on UVBUS. By default

VUSB will be supplied by SWBST. Table 28. BP Detection Thresholds

1. Default setting for BPSNS[1:0] is 00. The above specified thresholds are ±50 mV accurate for the indicated edge. A hysteresis is applied

Table 29. Power Monitoring Summary

control of timing in and out of such deep sleep modes. circuits along with control of the Standby pins. take into account the programmed input polarities associated with each pin. actually going into standby (i.e. before turning off some supplies). No delay is applied when coming out of standby. control is required to put these regulators in a Low Power mode. not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired. read back what is programmed, not the actual state. Table 30. Standby Pin and Polarity Control

1. STANDBY = 0: System is not in Standby; STANDBY = 1: System is in Standby and Standby programmability is activated.

Table 31. Delay of STANDBY- Initiated Response

00 No Delay

01 One 32 K period (default)

10 Two 32 K periods

11 Three 32 K periods

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For regulators with internal pass devices and general outputs, the previous table can be simplified. be achieved by disabling switchers when not needed, or running them in PFM mode if loading conditions are light enough. modes to support state retention for faster startup from the low power Off modes for Warm Start or Warm Boot. Table 34 summarizes the Buck switcher programmability for Normal and Standby modes. Table 32. LDO Regulator Control (External Pass Device LDOs)

0 X X X Off

1 X 1 0 On

1. This table is valid for regulat ors with an external pass device
2. STANDBY refers to a Standby event as described earlier

Table 33. LDO Regulator Control (Internal Pass Device LDOs)

0 X X Off

1. This table is valid for regulat ors with an internal pass device
2. STANDBY refers to a Standby event as described earlier

Table 34. Switcher Mode Control for Normal and Standby Operation

0000 Off Off

0001 PWM Off

0010 PWMPS Off

0011 PFM Off

0100 Auto Off

0101 PWM PWM

0110 PWM Auto

0111 NA NA

1000 Auto Auto

1001 PWM PWMPS

1010 PWMPS PWMPS

1011 PWMPS Auto

1100 Auto PFM

1101 PWM PFM

back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described previously. Low Power Off mode will not be off when the startup sequencer is started). keeps the external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention. the processor core to complete booting, and begin running software before additional supplies or peripheral devices are powered. included for optimizing the system power tree. of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating. User Off configuration maintains PFM mode switchers on both the processor and external memory power domains. or SW3. In addition, PWGTDRV2 is provided support to power gate peripheral loads on the SW4 supply domain.

1110 PWMPS PFM

1111 PFM PFM

1. STANDBY defined as logical AND of STANDBY and STANDBYSEC pin

Table 35. Switcher Control In Memory Hold

0 Off

1 PFM

1. For Memory Hold mode, an activated SWx should use the Standby set point as programmed

Table 36. Switcher Control In User Off

1. For User Off mode, an activated SWx shoul d use the Standby set point as programmed by

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isolate the maintained supply domains from any peripheral loading. the charge pump gate drive voltage to reach its full value for minimum switch RDS_on. Figure 13. Power Gating Diagram external memory is maintained in self refresh mode. or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain.

Figure 14. Memory Hold Circuit by software to complete restoration of the full system power tree. the active modes as shown in Table 38. Table 37. Power Gating Characteristics

1. Larger capacitive loading values will l ead to longer turn on times exceeding the given limits; smaller values will lead to larger ripple at
2. Input supply is assumed in the range of 3.0 < BP < 4.65 V; lower BP values may extend turn on time, and functionality not supported

Table 38. Power Gate Drive State Control

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by SPI enable bits PWGTxSPIEN, according to Table 39. camera flash, or even supplemental regulators. Four general purpose outputs are provided, summarized in Table 40 and Table 41 (active high polarities assumed). resistance of the GPO1 driver is of importance; see ADC Subsystem. Finally, a muxing option is included to allow GPO4 to be configured for a muxed connection into Channel 7 of the GP ADC. configured by software for GPO operation with GPO4ADIN = 0. Refer to ADC Subsystem for GP ADC details. Table 39. Power Gating Logic Table

1 Low

0 High

1. Applicable for Watchdog, On and User Off Wait modes

the charge pump is disabled. Table 40. GPO Control Bits Table 41. GPO Control Scheme

0 X X Low

1. GPO1 is automatically made active high when a charger is

Table 42. GPO1 Driver Output Characteristics

The switched mode power supplies and the linear regulators are dimensioned to support a supply flow based upon Figure 15. Figure 15. Supply Distribution voltages, the performance may be degraded. Table 43 summarizes the available power supplies. Table 43. Power Tree Summary

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can run at the same voltage level. direct interfacing without bandwidth limiting synchronizers. (when present). Figure 16 shows a high level block diagram of the buck switchers. Figure 16. Buck Switcher Architecture

benefit from this. The buck converters permit a 100% duty cycle operation. feature improves efficiency by reducing dynamic switching losses by simply switching less often. Switchers section in Power Control System for details. steps, state machine defined modes, and direct DVSx pin control. is not exceeded. This current limiter can be disabled by setting the SWILIMB bit. Point of Load feedback is intended for minimizing errors due to board level IR drops. via PLLX[2:0] to different values as shown in Table 44. continuous operation by setting the SPI bit PLLEN = 1. Table 44. PLL Multiplication Factor

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Table 45. PLL Main Characteristics

1 Buck Switcher active 100 150 μA

2 Buck Switchers active 115 170 μA

3 Buck Switchers active 130 190 μA

4 Buck Switchers active 145 210 μA

1. Clock input to PLL is 32.768 kHz

Table 46. PLL Control Registers Table 47. Buck Switchers (SW1, 2, 3, 4) Output Voltage Programmability

Note that the following efficiency curves were measured with the MC13892 in a socket. Table 48. SWxHI States for Power Up Defaults

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Figure 17. Buck Switcher PFM Efficiency

Figure 18. Buck Switcher PWM (No Pulse Skipping) Efficiency

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Figure 19. Buck Switcher PWM (Pulse Skipping) Efficiency

• Normal operation: output value selected by SPI bits SWx[4:0]. Voltage transitions initiated by SPI writes to SWx[4:0] are governed by the same DVS stepping rate that is programmed for DVSx pin initiated transitions.
• DVS: output can be higher or lower than normal operation fo r tailoring to application requirements. Configured by SPI bits SWxDVS[4:0] and controlled by a DVSx pin transition.
• Standby (Deep Sleep): can be higher or lower than normal operatio n, but is typically selected to be the lowest state retention voltage of a given process. Set by SPI bits SWxSTBY[4:0] and controlled by a Standby event (STANDBY logically and'd with STANDBYSEC). Voltage transitions initiated by Standby are governed by the same DVS stepping that is programmed for DVSx pin initiated transitions. The following tables summarize the set point control and DVS time stepping applied to SW1 and SW2.

Table 49. DVS Control Logic Table for SW1 and SW2

1 X SWxSTBY[4:0]

1. STANDBY is the logical andi ng of STANDBY and STANDBYSEC

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function of how many contiguous SPI clock falling edges are seen while the DVSx pin is held high. not change. The set point adjustment takes place in the SID block prior to bit delivery to the switcher's digital control. Figure 21. SID Control Example for Increment & Decrement Figure 22. SID Control Example for Panic Mode Recovery decode of the jog up command is ignored, because it came in before the previous step was completed. Table 51. SID Control Protocol

to within the acceptable bounds for a given process technology used for the BB IC. SW1SIDMIN = 1000 (default value) should be decoded as 01000, which corresponds to 0.800 V (assuming SW1HI = 0). as 11010, which corresponds to 1.250 V (again, assuming SW1HI = 0). system only uses the SWx[4:0] bits and the min/max stops SWxSIDMIN[3:0] and SWxSIDMAX[3:0]. is integrated on-chip. An external fly back Schottky diode, inductor and capacitor are required. Figure 23. Boost Switcher Architecture Enabling of SWBST is accomplished through the SWBSTEN SPI control bit. Table 52. Switch Mode Supply SWBST Control Function Summary

1 SWBST ON

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Figure 24. Boost Switcher Efficiency Definition and Control in Power Control System for more details. supplies are included in Connectivity). a battery pack thermistor bias in synchronization with timed ADC conversions. is kept powered as long as there is a valid supply and/or coin cell. Table 53 captures the main characteristics of the core circuitry. Table 53. Core Specifications

1. 3.0 V < BP < 4.65 V, no external loading on VCOREDIG, VCORE, or REFCORE. Extended operation down to UVDET, but no system
2. The core is in On mode when charging or when the state machine of the IC is not in the Off mode nor in the power cut mode. Otherwise,

Analog Integrated Circuit Device Data Freescale Semiconductor 83 13892 FUNCTIONAL DEVICE OPERATION SUPPLIES REGULATORS GENERAL CHARACTERISTICS The following applies to all linear regulators unless otherwise specified.

• Specifications are for an ambi ent temperature of -30 to +85 °C.
• Advised bypass capacitor is the Murata™ GR M155R60G225ME15 which comes in a 0402 case.
• In general, parametric performance specifications assume the use of low ESR X5R ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may require a larger room temperature nominal capacitance value to meet performance specs over temperature. In addition, capacitor derating as a function of DC bias voltage requires special attention. Finally, minimum bypass capacitor guidelines are provided for stability and transient performance. Larger values may be applied; performance metrics may be altered and generally improved, but should be confirmed in system applications.
• Regulators which require a minimum output capacitor ESR (thos e with external PNPs) can avoid an external resistor if ESR is assured with capacitor specifications, or board level trace resistance.
• The output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static line regulation, and static load regulation.
• The PSRR of the regulators is measured with the perturbed signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements care must be taken not to reach the drop out of the regulator under test.
• In the Low Power mode the output performanc e is degraded. Only those parameters listed in the Low Power mode section are guaranteed. In this mode, the output current is limited to much lower currents than in the Active mode.
• Regulator performance is degraded in the extended input volt age range. This means that the supply still behaves as a regulator and will try to hold up the output voltage by turning the pass device fully on. As a result, the bias current will increase and all performance parameters will be heavily degraded, such as PSRR and load regulation.
• Note that in some cases, the minimum operating range specifications may be conflicting due to numerous set point and biasing options, as well as the potential to run BP into one of the software or hardware shutdown thresholds. The specifications are general guidelines which should be interpreted with some care.
• When a regulator gets disabled, the output will be pulled towa rds ground by an internal pull-down. The pull-down is also activated when RESETB goes low.
• 3 2 kHz spur levels are specified for fully loaded conditions.
• Short-circuit protection (SCP) is included on certain LDOs (see the SCP section later in this chapter). Exceeding the SCP threshold will disable the regulator and generate a system interrupt. The output voltage will not sag below the specified voltage for the rated current being drawn. For the lower current LDOs without SCP, they are less accessible to the user environment and essentially self-limiting.
• The power tree of a given application must be scrubbed for crit ical use cases to ensure consistency and robustness in the power strategy. TRANSIENT RESPONSE WAVEFORMS The transient load and line response are specified with the waveforms as depicted in Figure 25. Note that the transient load response refers to the overshoot only, excluding the DC shift itself. The transient line response refers to the sum of both overshoot and DC shift. This is also valid for the mode transition response.

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Figure 25. Transient Waveforms an interrupt SCPI will be generated to flag the fault to the system processor. The SCPI interrupt is maskable through the SCPM mask bit. to optimize power efficiency during Deep Sleep modes.

minimum ESR may be required. VAUDIO is implemented with an integrated PMOS pass FET and has a dedicated input supply pin VINAUDIO. The following tables contain the specifications for the VVIDEO, VAUDIO. power supply rail to improve power dissipation. VIOHI has an internal PMOS pass FET which will support loads up to 100 mA. Table 54. VVIDEO and VAUDIO Voltage Control Table 55. VPLL and VDIG Voltage Control

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the ON Semiconductor NSS12100UW3TCG. For stability reasons a small minimum ESR may be required. The input VINCAM should always be connected to BP, even if the VCAM regulator is not used by the system. dissipation in the pass devices. external buck switcher as the input to the regulators is a hardwired board level commitment, and not changed on-the-fly). Table 56. VCAM Voltage Control Table 57. VSD Voltage Control

A short circuit condition will shut down the VGEN3 regulator and generate an interrupt for SCPI. Table 58. VGEN1 Control Register Bit Assignments

1. The max load given for VGEN1MODE = 0 and must take into account the capabilities of the external pass device and operating

conditions, to manage its power dissipation. Load capability is 3.0 mA for VGEN1MODE = 1. Table 59. VGEN2 Control Register Bit Assignments

1. The max load is given for as VGEN2MODE = 0, and must take into account the capabilities of the external pass device and operating

conditions to manage its power dissipation. Load capability is 3.0 mA for VGEN2MODE = 1. Table 60. VGEN3 Voltage Control

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charger or a USB host can be connected. It can also support dead battery operation and unregulated chargers. The charge path is depicted in the following diagram. Figure 26. Charge Path Block Diagram battery operation is not supported in this case. Transistors M1 and M2 become non-conducting if the charger voltage is too high. The VBUS must be shorted to CHRGRAW in cases where the wall charger and VBUS voltages are contained on a common pin. can be found in ADC Subsystem. The preferred devices for M1 and M2 are Fairchild™ FDZ193P, due to their small package outline and thermal characteristics. The preferred device for M3 is the On Semiconductor NTHS2101P for its low RDSON and small footprint. chapter and the SPI bit summary in SPI Bitmap.

Table 61. Main Control Bit Signals CHRGSSS Charger configuration sense, serial versus single. A logic 1 indicates a serial path.

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and programmable current limit. resistor is of no influence on the output voltage. The output voltage is programmable by SPI through VCHRG[2:0] bits. Table 62. Charge Path Regulator Voltage Settings Table 63. Charge Path Regulator Current Limit Settings

1111 Fully On – M3

disappears for longer than the debounce time, charging will resume and previously programmed SPI settings will be reloaded. An interrupt CHGFAULTI is generated with associated CHGFAULTM mask bit with the CHGFAULTS[1:0] bits set to 01. over-voltage fault state, and therefore an interrupt may not always be generated. guaranteed. If the user wants to protect against these failure conditions, additional protection will be required. Table 64. Charge Path Regulator Characteristics

1. Excludes spread and tolerances due to board routing and 100 mOhm sense resistor tolerances.
2. An additional derating of 35% is allowed.
3. This condition applies when using an external charger with a 3.0 m long cable.

Table 65. Charger Over-voltage Protection Characteristics

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CHGFAULTI interrupt generated with the CHGFAULTS[1:0] bits set to 01. pass FETs. The power limiter is automatically disabled in serial path factory mode and in reverse mode. estimated. When this estimated duty cycle falls below the power limiter minimum duty cycle, the charger circuit will be disabled. current through the accessory supply path is monitored via the charge path sense resistor R2, and can be read out via the ADC. The accessory supply path is disabled and an interrupt CHGSHORTI is generated when the slow or fast threshold is crossed. The reverse path is disabled when a current reversal occurs and an interrupt CHREVI is generated. Table 66. Charger Power Dissipation Limiter Control Table 67. Charger Power Dissipation Limiter Characteristics Table 68. Accessory Supply Main Characteristics

BATTISNS and BP are shorted on the board. charger removal detection. The table below summarizes the charger detection logic. in the charger flow to provide enough time to the battery protection circuit to reconnect the battery cell. Table 69. Internal Trickle Charger Control Table 70. Internal Trickle Charger Characteristics

1. The effective trickle current may be significantly reduced

Table 71. Charger Detection

0 X X No

Table 72. Charger Detectors main characteristics

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interrupts can be used as a simple way to implement a 3-bar battery meter. the thermistor over temperature. In order to read out the thermistor value, it is biased from GPO1 through a pull-up resistor RPU. see next section for details. at the CHRGLED pin for an LED connected to CHRGRAW. can be forced on. In software controlled charging, the LED is under full control of this CHRGLEDEN bit. Table 73. Battery Thermistor Check Main Characteristics Table 74. Charge LED Drivers Main Characteristics

1. Above conditions represent respecti vely a USB and a collapsed charger case

Table 75. Charge LED Driver Control

CHRGSE1BI is generated. No specific debounce is applied to the CHRGSE1B detector. pull-down resistor should be placed at VBUS. CHGAUTOVIB bit is set. Note that the power limiter can be programmed independent of this bit being set. is described further in this chapter. will not be powered up, and the same charging scheme is followed as for single path. Table 76. Charger Detector Characteristics

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is a fault condition and is flagged to the processor by the CHGFAULTI interrupt, and the CHGFAULTS[1:0] bits are set to 10. software restart can also be initiated by setting the self clearing CHGRESTART bit. can force the LED driver on. cases of single path, the pin BATTFET must be left floating. state machine will be re-initiated again when the temperature drops below this threshold. removal, a charger over-voltage detection and excessive power dissipation in M1/M2. BPON) while M3 is open, the charger control logic will immediately close M3 under the condition that BATT > BATTMIN. Table 77. Charger Timer Characteristics Table 78. Charger Fault Conditions

In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field. during the attach, see Connectivity. the power limiter are disabled. are enabled, while only the charger timer and power limiter function are disabled. CHGAUTOB bit the factory mode is exited. PCB board, as shown in Table 79.

1. First step: detect a potential low power b oot condition, and qualify if it is enabled.

will proceed with LPB sequence. If any are false, LPBS = 0.

1. If LPBS = 0, then a normal booting of the system will take place as follows:

low power boot mode, so it powers up normally. when entering watchdog phase from warm start.

1. If LPBS = 1, then the system will boot in low power as follows:

stay within 100 mA USB budget. The startup sequence and defaults as defined in the startup table will be followed. Since VBUS is present the USB supplies will be enabled. The charge LED driver is maintained off. the total loading stays below the un-negotiated 100 mA limit. during the watchdog phase. The processor detects this and starts up in a Low Power mode at low clock speed. d) The application processor will enable the PHY in serial FS mode for enumeration. will transition to USB trickle recover, LPBS reset to 0. Table 79. MODE Pin Programming

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• When the SPI is activated, the LPB interrupt LPBI can be cleared; other unmasked interrupts may now become active. When leaving watchdog phase for the On mode, the interrupts will work 'normally' even if LPBI is not cleared.
• The SPI bit ACKLPB bit is set to enable the internal trickle charger. The charge LED gets activated. When the battery crosses the BATTMIN threshold the M3.transistor is automatically closed and the battery is charged with the current not taken by the application.
• When BP exceeds BPON, the charger state machine will succe ssfully exit the trickle charge mode. This will make LPBS = 0 which generates a LPBI. This interrupt will inform the processor that a full turn on is allowed. Once this happens the application code is allowed to run full speed. BATTERY THERMISTOR CHECK OPERATION By default, the battery thermistor value is taken into account for charging the battery. Upon detection of a supply at CHRGRAW, the core circuitry powers up including VCORE. As soon as VCORE is ready, the output GPO1 is made active high, independently of the state of GPO1EN bit. The resulting voltage at ADIN5 is compared to the corresponding temperature thresholds. If the voltage at ADIN5 is within range, the charging will behave as described thus far, however if out of range the charger state machine will go to a wait state, pause the charge timers, and no current will be sourced to the battery. When the temperature comes back in range, charging is continued again. The actual behavior depends on the configuration the charger circuitry at the moment the temperature range is exceeded. The battery thermistor check can be disabled by setting the THCHKB bit. This is useful in applications where battery packs without thermistor may be used. This bit defaults to '0', which means that initial power up only can be achieved with an already charged battery pack or on a charger, but not on a USB Host without low power boot support. Alternatively, one can bias ADIN5 to get within the temperature window. Setting the SPI bit to disable the thermistor check will also inhibit the automatic enabling of the GPO1 output. The GPO1 output still remains controllable through GPO1EN. As an additional feature, the charger state machine will end up in an out of temperature state when the die temperature is below -20 °C, independent of the setting of the THCHKB bit. Notes:
• When using the battery charger as the only source of power, as in a battery-less application, the following precautions should be observed:
• It is still necessary to connect ADIN5 to either VCOREDIG or a midpoint of a divider from GPIO1 to ground since the battery charger will still interpret this voltage as the battery pack thermistor by default.
• Very careful budgeting of the total current consumption and voltage standoff from CHRGRAW to BPSNS must be made, since the power limiter is operational by default, and a battery less system won't have a source of current if the power dissipation limit is reached.
• If operating from a USB host the unit load limit (100 mA max.) must still be observed.
• If operating from a “wall charger”, and if there is no battery, there is an period of approximately 85 ms after RESETB is released, but before the current limit is set to a nominal 560 mA. If the total current demand is greater than this limit, the voltage may collapse and RESETB may pulse a few times (depending in part in the system load and dependence on RESETB.) Therefore, at the end of this time, RESETB may or may not be active. It may be necessary to use one of the other turn on events (such as PWRONx) to turn it back on.

Table 80. Battery Thermistor Check Charger States

ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. depending on this time base. The ADC has 8 input channels. Table 81 gives an overview of the attributes of the A to D channels. the battery current are indirectly read out by the voltage drop over the resistor in the charge path and battery path respectively. For details on scaling see the dedicated readings section. offset, but will not impact INL and DNL numbers except for input voltages close to zero. Table 81. ADC Inputs

1. Equivalent to -3.0 to +3.0 A of current with a 20 mOhm sense resistor
2. Equivalent to -3.0 to +3.0 A of current with a 100 mOhm sense resistor

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masked with the ADCDONEM bit. the ASC bit high during the conversions. selected with the ADA1[2:0] setting. This setting is not taken into account in multiple channel mode. performed before a first utilization of the ADC after a cold start. between each of the conversions by setting the ATOX bit. by ADA1[2:0], and ADD2[9:0] will contain the conversion value indexed by ADA2[2:0]. should therefore be reprogrammed. Table 82. ADC Input Specification

between BATT and BATTISNSCC. This function is enabled by setting BATTICON = 1. available in 4 pairs of battery voltage and current reading as shown in Table 84. If the BATTICON bit is not set, the ADC will return a 0 reading for channel 1. The voltage difference between BATT and BATTISNS is first amplified to fit the ADC input range as V(BATT-BATTISNS)*20. correspond to the current flow out of the battery, and negative readings to the current flowing into the battery. Table 83. Battery Voltage Reading Coding Table 84. Battery Current Reading Sequence

0 BATT, BATT – BATTISNSCC BATT Channel 0 BATT

2 BATT, BATT – BATTISNSCC BATT Channel 2 BATT

4 BATT, BATT – BATTISNSCC BATT Channel 4 BATT

6 BATT, BATT – BATTISNSCC BATT Channel 6 BATT

Table 85. Battery Current Reading Coding

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that excessively high values can impact the operating life of the device due to extra voltage drop across the sense resistor. between CHRGISNS and BPSNS. The voltage difference is first amplified to fit the ADC input range as V(CHRGISNS-BPSNS)*4. the ADC will return a 0 reading for channel 4. but also the charge current levels. It is therefore advised not to select another value than 100 mOhm. Table 86. Battery Current Reading Specification Table 87. Application Supply Voltage Reading Coding Table 88. Charger Voltage Reading Coding Table 89. Charge Current Reading Coding

particular when the thermistor check function is used, see Battery Thermistor Check Circuitry. BATTDETBS is made high and after a debounce the BATTDETBI interrupt is generated. On channel 6, ADIN6 may be used as a general purpose unscaled input. at LICELL can still be read through the ADC. application, an ambient light sensor is connected here. can be scaled by setting the ADIN7DIV bit. In the application, a second ambient light sensor is supposed to be connected here. Note that the GPO4 will have to be configured to allow for the proper routing of GPO4 to the ADC, see General Purpose Outputs. ID line exceeds the input voltage range of the ADC, the UID voltage is first scaled as V(UID)/2. Table 90. Battery Removal Detect Specification

1. This is equivalent to a 10 kOhm pull-up and a 10 kOhm thermistor at -35 °C.

Table 91. Coin Cell Voltage Reading Coding Table 92. UID Voltage Reading Coding

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store both their results as shown in Figure 27. This allows two independent pieces of software to perform ADC requests. Figure 27. ADC Request Handling functions as an extended address bit. By setting this bit to a 1, the control bits which follow are destined for the 'ADC BIS'. 'ADC' and 'ADC BIS' conversions are available in two separate registers. The following diagram schematically shows how the ADC control and result registers are set-up. Table 93. Die Temperature Voltage Reading Table 94. ADC Channel 7 Scaling Selection

Figure 28. ADC Register Set for ADC BIS Access conversion, and can be masked. directly after the conversions of the first request are finished. Figure 29. TRIGMASK Functional Diagram by setting the ADONESHOT bit to a one. In that case, only at the first following conversion, an ADTRIG trigger event is accepted. be cleared. Note that this bit is available for each of the conversion requests 'ADC' or 'ADC BIS', so can be set independently. the 'ADC BIS' conversion. Note that the ADONESHOT is also taken into account. conversion results, it is preferable to make ADEN = 0.

8 Bit Address Header 24 Bit Data

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a reference. Several readout possibilities are offered. for touch screen readings as well as for general purpose reading on the same inputs. The touch screen operating modes are configured via the TSMOD[2:0] bits show in the following table. mapped on ADC channels 4, 5, 6, and 7. to the processor. This detection does not make use of the ADC core or the TSREF regulator, so both can remain disabled. In touch screen mode, the XY coordinate pairs and the contact resistance are read. screen is touched with a finger or stylus. touch screen readings are repeated in the readout sequence. the change in touch screen plate polarity and will read out as '0'. Table 95. Touch Screen Operating Mode Table 96. Touch Screen Reading Sequence

0 X position 000

1 X position 001

2 Dummy 010

3 Y position 011

4 Y position 100

5 Dummy 101

6 Contact resistance 110

7 Contact resistance 111

1. Address as indicated by ADA1[2:0] and ADA2[2:0]

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the pins CFP and CFM, see Figure 31. Figure 31. Coulomb Counter Block Diagram to 72C. However, since the resolution of the A to D converter is much finer than 1C, the internal counts are first to be rescaled. CCOUT[15:0] with R1 = 20 mOhm. so when restarting the CC with STARTCC, the count will continue. CC is by default permanently corrected for offset and gain errors. This function can be disabled by setting the CCCALDB bit. However, this is not advisable. should remain enabled, so the CCCALDB bit should not be set. Table 98. Coulomb Counter Characteristics

Analog Integrated Circuit Device Data Freescale Semiconductor 109 13892 FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM As follows from the previous description, using the CC requires a number of programming steps. A typical programming example is given below. 1. SPI Access 1: Initialize

• Reg 9: Write STARTCC = 1, RSTCC = 1, CCCALA = 1, CCDITHER = 1, CCCALDB = 0
• RSTCC will be self clearing
• Register 10 is NOT to be programmed since by default the ONEC[14:0] scaler is set to 1 2. Wait for analog calibration period 3. SPI Access 2: Set scaler
• Reg 10: Write ONEC to desired value for CC use, for instance 2621DEC 4. SPI Access 3: Read analog offset and reset CC
• Reg 9: Write STARTCC = 1, RSTCC = 1, CCCALA = 0, CCDITHER = 1, CCCALDB = 0
• During the write access, on the MISO read line the most recent CCOUT[15:0] is available
• RSTCC will be self clearing From this point on the ACC is running properly and CCOUT[15:0] reflects the accumulated charge. In order to be sure the contents of the CCOUT[15:0] are valid, a CCFAULT bit is available. CCFAULT will be set '1' if the CCOUT content is no longer valid, this means the bit gets set when a fault condition occurs and stays latched till cleared by software. There is no interrupt associated to this bit. The following fault conditions are covered. Counter roll over: CCOUT[15:0] = 8000HEX This occurs when the contents of CCOUT[15:0] go from a negative to a positive value or vice versa. Software may interpret incorrectly the battery charge by this change in polarity. When CCOUT[15:0] becomes equal to 8000HEX the CCFAULT is set. The counter stays counting so its contents can still be exploited. Battery removal: 'BP<UVDET' When removing and replacing the battery, the contents of the counter are no longer valid. A battery removal is characterized by the input supply to the IC dropping below the under voltage detect threshold, so BP<UVDET. To avoid false detection due to short power cuts, the CCFAULT is set only after a long debounce of 1 second. Battery removal when charging: BATTDETBS = 1 The battery removal detection as described previously, is not applicable when charging, since the charger will continue to supply the application and the BP will not drop below UVDET. To still detect a battery removal, one can use the battery detect function as described in the channel description earlier in this chapter. When the sense bit BATTDETBS becomes a 1, the CCFAULT is set only after a long debounce of 1 second.

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be used for portable product battery charging (refer to Battery Interface and Control for more details on the charging system). Finally included are comparators/detectors for VBUS and ID detection. The USB interface is illustrated in the following diagram. Figure 32. USB Interface host in the case of host mode operation, or by the integrated VBUS generation circuit, in the case of USB OTG mode operation. discharge range of the main battery. operation. The VUSBIN SPI bit is used to make the selection between host or OTG mode operation as defined in Table 99.

The VBUSEN pin along with the VUSBIN SPI bit shown in Table 99, control switching SWBST to drive VBUS in OTG mode. bit OTGSWBSTEN = 1). In OTG mode, VUSB and VUSB2 will be automatically enabled by setting the SPI bit VUSBIN to a 1. setting the CHGAUTOB = 1, and the charge current set to 0 prior to enabling the SWBST to supply the UVBUS pin. processor to determine what type of device is connected, either a USB host or a wall charger, and take appropriate action. to off. If UVBUS is detected later, the VUSB regulator will be automatically be enabled and supplied from the UVBUS pin. up sequence shown in Power Control System. following tables show the USB supplies. should always be connected to BP even in cases where the regulators are not used by the application. Table 99. VUSB Input Source Control

0 Powered by Host: UVBUS powers VUSB

1 OTG mode: SWBST internally switched to supply the VUSB regulator, and SWBST will drive VBUS from the

1. Note that (VUSBIN = 1 and VBUSEN = 1) only closes the switch between the VINUSB and UVBUS pins, but does not enable the

SWBST boost switcher (which should be enabled with OTGSWBSTEN = 1).

1. VUSBIN SPI bit initialized by PUMS2 pin configuration at cold start

Table 100. VUSB2 Voltage Control

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grounded, or factory mode condition on the UID pin. There are also dedicated maskable interrupts for each UID condition as well. voltage can be read out via the ADC channel ADIN7, see ADC Subsystem. custom vendor applications by evaluation of the ADIN7 conversion reading. Table 101. USB Detect Specifications Table 102. ID Detection Thresholds master or no device) is attached.

1. UID maximum voltage is 5.25 V

Table 103. USB OTG Specifications

1. Note that the UID Pull-ups are not mut ually exclusive of each other; they are independently controlled by their enable bits and thus

multiple pull-ups can be engaged simultaneously.

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configured in series. Three additional drivers are provided for RGB or general purpose signaling. startup time is longer than one half the minimum of the period of the backlight drivers. application, the switching edges of the output drivers are softened. Table 104. Backlight Drivers Current Programming

1. “x“ Represents MD, AD and KP

Table 105. Backlight Drivers Duty Cycle Programming

1. “x” represents MD, AD, or KP

116 Freescale Semiconductor

Figure 34. Serial LED Configurations through the main display backlight LEDs and 30 mA through the keypad backlights LEDs. LED intensity can be adjusted. By driving LEDs of different colors, color mixing can be achieved. Table 107. Signaling LED Drivers Current Programming

1. “x” represents for R, G and B

Table 108. Signaling LED Drivers Duty Cycle Programming

1. “x” represents R, G and B

12 LED Keypad Arrangement

2 LED Reduced Keypad Option

6 LED Main Display

9 LED Keypad6 LED Main Display

3 LED Aux Display

details on the boost switcher and its control, see Supplies. hardware. Ramp patterns for each of the drivers is accessed with the corresponding LEDxRAMP bit. 32/32 will take 500 ms while going to from 8/32 to 16/32 takes 125 ms. when LEDxRAMP = 0, then the change is immediate rather than spread out over a PWM sweep. that the intensity is set through the PWM duty cycle. and dimming patterns cannot be applied. signaling or as generic PWM generator outputs. For the maximum voltage ratings. Table 109. Signal LED Drivers Period Control Table 110. Signaling LED Driver Characteristics

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The complete SPI bitmap is given in Table 111 with one register per row for a general overview. A color coding is applied which indicates the type of reset for the bits. Table 111. SPI Bitmap

0 Interrupt

1 Interrupt

2 Interrupt

3 Interrupt

4 Interrupt

5 Interrupt

7 Identificatio

8 Unused R/W 0 0 1 0 0 0 0

9 Unused R/W 0 0 1 0 0 1 0 CCOUT[15:0] CCFAULT Reserved Reserved CCCALA CCCALDB CCDITHER RSTCC STARTCC

10 Unused R/W 0 0 1 0 1 0 0 ONEC[14:0]

11 Unused R/W 0 0 1 0 1 1 0

12 Unused R/W 0 0 1 1 0 0 0

13 Power

14 Power

15 Power

16 Unused R/W 0 1 0 0 0 0 0

17 Unused R/W 0 1 0 0 0 1 0

18 Memory A R/W 0 1 0 0 1 0 0 MEMA[23:0]

19 Memory B R/W 0 1 0 0 1 1 0 MEMB[23:0]

20 RTC Time R/W 0 1 0 1 0 0 0 RTCCALMODE[1:0] RTCCAL[4:0] TOD[16:0]

21 RTC Alarm R/W 0 1 0 1 0 1 0 RTCDIS Spare TODA[16:0]

22 RTC Day R/W 0 1 0 1 1 0 0 DAY[14:0]

23 RTC Day

24 Switchers 0 R/W 0 1 1 0 0 0 0 SW1HI SW1SIDMIN[3:0] SW1SIDMAX[3:0] SW1STBY[4:0] SW1DVS[4:0] SW1[4:0]

25 Unused R/W 0 1 1 0 0 1 0 SW2HI SW2SIDMIN[3:0] SW2SIDMAX[3:0] SW2STBY[4:0] SW2DVS[4:0] SW2[4:0]

26 Switchers 2 R/W 0 1 1 0 1 0 0 SW3HI Reserved SW3STBY[4:0] Spare SW3[4:0]

27 Unused R/W 0 1 1 0 1 1 0 SW4HI SW4STBY[4:0] Spare SW4[4:0]

28 Switchers 4 R/W 0 1 1 1 0 0 0 Reserve

29 Switchers 5 R/W 0 1 1 1 0 1 0 SWBSTEN SW4UOMOD

30 Regulator

31 Regulator

32 Regulator

33 Regulator

35 Unused R/W 1 0 0 0 1 1 0

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36 Audio Rx 0 R/W 1 0 0 1 0 0 0

37 Audio Rx 1 R/W 1 0 0 1 0 1 0

38 Audio Tx R/W 1 0 0 1 1 0 0

39 SSI

40 Audio

42 Unused R/W 1 0 1 0 1 0 0

43 ADC 0 R/W 1 0 1 0 1 1 0 ADCBIS

0 Spare ADINC2 ADINC1 CHRGRA

44 ADC 1 R/W 1 0 1 1 0 0 0 ADCBIS

1 ADONESHOT ADTRIGIGN ASC ATOX ATO[7:0] ADA2[2:0] ADA1[2:0] TRIGMASK ADSEL ADCCAL RAND ADEN

45 ADC 2 R 1 0 1 1 0 1 0 ADD2[9:0] Spare Spare ADD1[9:0] Spare Spare

46 ADC 3 R/W 1 0 1 1 1 0 0 Reserve

47 ADC 4 R 1 0 1 1 1 1 0 ADDBIS2[9:0] Spare Spare ADDBIS1[9:0] Spare Spare

48 Charger 0 R/W 1 1 0 0 0 0 0 CHGAUT

49 USB 0 R/W 1 1 0 0 0 1 0 Reserve

50 Charger

51 LED

52 LED

53 LED

54 LED

55 Unused R/W 1 1 0 1 1 1 0

56 Unused R/W 1 1 1 0 0 0 0

57 FSL Use

58 FSL Use

59 FSL Use

60 FSL Use

61 FSL Use

62 FSL Use

63 FSL Use

122 Freescale Semiconductor

available in the design. Reserved bits are not implemented in the design, but are used on other PMIC's.

• R is read access
• W is write access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
• RWM is read and write access while the device can modify the bit Reset: Resetting signal
• RESETB, which is the same signal as the RESETB pin (so bit is held in reset as long as RESETB is low)
• RTCPORB which is the reset signal of the RTC module (so bit is no longer held in reset once RTC power is good)
• OFFB which is an internal signal generated when transitioning into the Off state
• NONE. There is no reset signal for hardwired bits nor for the bits of which the state is determined by the power up mode settings Default: The value after reset as noted in the Default column of the SPI map.
• Fixed defaults are explicitly declared as 0 or 1.
• * corresponds to Read / Write bits that are initialized at startup based on power up mode settings (board level pin connections) validated at the beginning of Cold or Warm Start. Bits are subsequently SPI modifiable.
• S corresponds to Read only sense bits that continuous ly monitor an input signal (sense signal is not latched).
• L corresponds to Read only sense bits that are latched at startup.
• X indicates that the state does not have an explicitly defined default value which can be specified. For instance, some bits default to a value which is dependent on the version of the IC. Description: A short description of the bit function, in some cases additional information is included The following tables are intended to give a summarized overview, for details on the bit description, see the individual chapters.

Table 112. Register 0, Interrupt Status 0

Table 113. Register 1, Interrupt Mask 0 Table 114. Register 2, Interrupt Sense 0

124 Freescale Semiconductor

Table 115. Register 3, Interrupt Status 1 Table 116. Register 4, Interrupt Mask 1

Table 117. Register 5, Interrupt Sense 1

126 Freescale Semiconductor

Table 118. Register 6, Power Up Mode Sense

1. CHRGSSS will latch an updated sens e value when the charger is enabled.

Table 119. Register 7, Identification

Table 120. Register 8, Unused Table 121. Register 9, ACC 0

128 Freescale Semiconductor

Table 122. Register 10, ACC 1 Table 123. Register 11, Unused Table 124. Register 12, Unused Table 125. Register 13, Power Control 0

1. On the 13892A, the default value is 0, while it is 1 on the 13892B.

Table 126. Register 14, Power Control 1 Table 127. Register 15, Power Control 2

130 Freescale Semiconductor

Table 128. Register 16, Unused Table 129. Register 17, Unused

Table 130. Register 18, Memory A

132 Freescale Semiconductor

Table 131. Register 19, Memory B Table 132. Register 20, RTC Time

Table 133. Register 21, RTC Alarm Table 134. Register 22, RTC Day

134 Freescale Semiconductor

Table 135. Register 23, RTC Day Alarm Table 136. Register 24, Switchers 0

Table 137. Register 25, Switchers 1

136 Freescale Semiconductor

Table 138. Register 26, Switchers 2 Table 139. Register 27, Switchers 3

Table 140. Register 28, Switchers 4

1. SWxMODE[3:0] bits will be reset to t heir default values by the startup sequencer based on PUMS settings. An enabled switcher will

default to PWM mode (no pulse skipping) for both Normal and Standby operation. Table 141. Register 29, Switchers 5

138 Freescale Semiconductor

1. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer based on PUMS settings. An enabled switcher will

default to PWM mode (no pulse skipping) for both Normal and Standby operation. Table 142. Register 30, Regulator Setting 0

Table 143. Register 31, Regulator Setting 1 Table 144. Register 32, Regulator Mode 0

140 Freescale Semiconductor

Table 145. Register 33, Regulator Mode 1 Table 146. Register 34, Power Miscellaneous

Table 147. Register 35, Unused Table 148. Register 36, Unused Table 149. Register 37, Unused Table 150. Register 38, Unused Table 151. Register 39, Unused Table 152. Register 40, Unused Table 153. Register 41, Unused Table 154. Register 42, Unused

142 Freescale Semiconductor

Table 155. Register 43, ADC 0 Table 156. Register 44, ADC 1

Table 157. Register 45, ADC 2 Table 158. Register 46, ADC 3

144 Freescale Semiconductor

Table 159. Register 47, ADC 4

Table 160. Register 48, Charger 0 Table 161. Register 49, USB 0

146 Freescale Semiconductor

Table 162. Register 50, Charger USB 1 Table 163. Register 51, LED Control 0

Table 164. Register 52, LED Control 1 Table 165. Register 53, LED Control 2

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Table 166. Register 54, LED Control 3

Table 167. Register 55, Not Used Table 168. Register 56, Not Used Table 169. Register 57, FSL Use Only Table 170. Register 58, FSL Use Only Table 171. Register 59, FSL Use Only Table 172. Register 60, FSL Use Only Table 173. Register 61, FSL Use Only Table 174. Register 62, FSL Use Only Table 175. Register 63, FSL Use Only

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customer’s responsibility to validate their application. Figure 35. 13892 Typical Application

32.768 KHz

PA thermistor, Light Sensor, Etc.

Analog Integrated Circuit Device Data Freescale Semiconductor 151 13892 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. VK SUFFIX 139-PIN 98ASA10820D REVISION 0

Analog Integrated Circuit Device Data

152 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 153 13892 PACKAGING PACKAGE DIMENSIONS VL SUFFIX 186-PIN 98ASA10849D REVISION 0

Analog Integrated Circuit Device Data

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Table 176. Additional Documentation

Analog Integrated Circuit Device Data

156 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 157 13892 ADDITIONAL DOCUMENTATION

Analog Integrated Circuit Device Data

158 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 159 13892 ADDITIONAL DOCUMENTATION

Analog Integrated Circuit Device Data

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