1340A1-18

DS1340_06 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Enhanced Second Source for the ST M41T00 ♦ Available in a Surface-Mount Package with an Integrated Crystal (DS1340C) ♦ Fast (400kHz) I 2C Interface ♦ Software Clock Calibration ♦ RTC Counts Seconds, Minutes, Hours, Day, Date, Month, and Year ♦ Automatic Power-Fail Detect and Switch Circuitry ♦ Trickle-Charge Capability ♦ Low Timekeeping Voltage Down to 1.3V ♦ Three Operating Voltage Ranges (1.8V, 3V, and 3.3V) ♦ Oscillator Stop Flag ♦ Available in 8-Pin µSOP or SO Packages ♦ Underwriters Laboratory (UL) Recognized DS1340 I2C RTC with Trickle Charger

Ordering Information

V CC C1RPU RPU CRYSTAL FT/OUT VBACKUP R PU = tR / CB DS1340 Typical Operating Circuit Rev 4; 3/06 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE TOP MARK† DS1340Z-18 -40°C to +85°C 8 SO (0.150in) D1340-18 DS1340Z-3 -40°C to +85°C 8 SO (0.150in) DS1340-3 DS1340Z-33 -40°C to +85°C 8 SO (0.150in) D1340-33 DS1340U-18 -40°C to +85°C 8 µSOP 1340A1-18 DS1340U-3 -40°C to +85°C 8 µSOP 1340A1-3 DS1340U-33 -40°C to +85°C 8 µSOP 1340A1-33 DS1340C-18 -40°C to +85°C 16 SO 1340C-18 DS1340C-3 -40°C to +85°C 16 SO 1340C-3 DS1340C-33 -40°C to +85°C 16 SO 1340C-33 DS1340Z-18+ -40°C to +85°C 8 SO (0.150in) D1340-18 DS1340Z-3+ -40°C to +85°C 8 SO (0.150in) DS1340-3 DS1340Z-33+ -40°C to +85°C 8 SO (0.150in) D1340-33 DS1340U-18+ -40°C to +85°C 8 µSOP 1340A1-18 DS1340U-3+ -40°C to +85°C 8 µSOP 1340A1-3 DS1340U-33+ -40°C to +85°C 8 µSOP 1340A1-33 DS1340C-18# -40°C to +85°C 16 SO 1340C-18 DS1340C-3# -40°C to +85°C 16 SO 1340C-3 DS1340C-33# -40°C to +85°C 16 SO 1340C-33 *Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I 2C Patent Rights to use these com- ponents in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Pin Configurations appear at end of data sheet. + Denotes a lead-free/RoHS-compliant device. # Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and lead- free soldering processes. † A "+" anywhere on the top mark denotes a lead-free device. A "#" denotes a RoHS-compliant device.

I2C RTC with Trickle Charger ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on SDA, SCL, and FT/OUT J-STD-020 Specification AC ELECTRICAL CHARACTERISTICS (VCC = VCC MIN to VCC MAX, TA = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard mode 0 100SCL Clock Frequency f SCL Fast mode 100 400 kHz Standard mode 4.7Bus Free Time Between STOP and START Conditions tBUF Fast mode 1.3 µs Standard mode 4.0Hold Time (Repeated) START Condition (Note 2) tHD:STA Fast mode 0.6 µs Standard mode 4.7Low Period of SCL Clock t LOW Fast mode 1.3 µs Standard mode 4.0High Period of SCL Clock t HIGH Fast mode 0.6 µs Standard mode 0 0.9Data Hold Time (Notes 3, 4) tHD:DAT Fast mode 0 0.9 µs Standard mode 250Data Setup Time (Note 5) tSU:DAT Fast mode 100 ns Standard mode 4.7START Setup Time t SU:STA Fast mode 0.6 µs Standard mode 20 + 0.1CB 1000Rise Time of SDA and SCL Signals (Note 6) tR Fast mode 20 + 0.1CB 300 ns Standard mode 20 + 0.1CB 300Fall Time of SDA and SCL Signals (Note 6) tF Fast mode 20 + 0.1CB 300 ns Standard mode 4.7Setup Time for STOP Condition tSU:STO Fast mode 0.6 µs Capacitive Load for Each Bus Line CB (Note 6) 400 pF I/O Capacitance (SCL, SDA) C I/O 10 pF Pulse Width of Spikes that Must be Suppressed by the Input Filter tSP Fast mode 30 ns Oscillator Stop Flag (OSF) Delay tOSF (Note 7) 100 ms

I2C RTC with Trickle Charger RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC MIN to VCC MAX, TA = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = 3.3V, T A = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DS1340-18 1.71 1.8 1.89 DS1340-3 2.7 3.0 3.3Supply Voltage (Note 8) V CC DS1340-33 2.97 3.3 5.5 V Input Logic 1 (SDA, SCL) V IH (Note 8) 0.7 x VCC VCC + 0.3 V Input Logic 0 (SDA, SCL) V IL (Note 8) -0.3 +0.3 x V CC V Supply Voltage, Pullup (FT/OUT, SDA, SCL), VCC = 0V VPU (Note 8) 5.5 V DS1340-18 1.3 3.7 DS1340-3 1.3 3.7Backup Supply Voltage (Note 8) VBACKUP DS1340-33 1.3 5.5 V R1 (Notes 9, 10) 250 R2 (Note 11) 2000Trickle-Charge Current-Limiting Resistors R3 (Note 12) 4000 Ω DS1340-18 1.51 1.6 1.71 DS1340-3 2.45 2.6 2.7Power-Fail Voltage (Note 8) V PF DS1340-33 2.70 2.88 2.97 V Input Leakage (SCL, CLK) I LI -1 +1 µA I/O Leakage (SDA, FT/OUT) I LO -1 +1 µA VCC > 2V; VOL = 0.4V 3.0 1.7V < VCC < 2V; VOL = 0.2 x VCC 3.0 mAFT/OUT Logic 0 Output I OLSQW 1.3V < VCC < 1.7V; VOL = 0.2x VCC 250 µA DS1340-18 72 150 DS1340-3 108 200Active Supply Current (Note 13) I CCA DS1340-33 192 300 µA DS1340-18 60 100 DS1340-3 81 125Standby Current (Note 14) I CCS DS1340-33 100 150 µA VBACKUP Leakage Current IBACKUPLKG VBACKUP = 3.7V 100 nA DC ELECTRICAL CHARACTERISTICS (VCC = 0V, VBACKUP = 3.7V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IBACKUP1 OSC ON, FT = 0 (Note 15) 800 1150 IBACKUP2 OSC ON, FT = 1 (Note 15) 850 1250 VBACKUP Current IBACKUP3 OSC ON, FT = 0, VBACKUP = 3.0V, TA = +25°C (Notes 15, 16) 800 1000 nA VBACKUP Data-Retention Current IBACKUPDR OSC OFF 25.0 100 nA

WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: After this period, the first clock pulse is generated. signal) to bridge the undefined region of the falling edge of SCL. Note 4: The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal. before the SCL line is released. Note 6: CB—total capacitance of one bus line in pF. VCCMAX and 1.3V ≤ VBAT ≤ 3.7V range. Note 8: All voltages are referenced to ground. Note 9: Measured at VCC = typ, VBACKUP = 0V, register 08h = A5h. Note 10: The use of the 250Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled. Note 11: Measured at VCC = typ, VBACKUP = 0V, register 08h = A6h. Note 12: Measured at VCC = typ, VBACKUP = 0V, register 08h = A7h. Note 13: ICCA—SCL clocking at max frequency = 400kHz. Note 14: Specified with I2C bus inactive. Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins. Note 16: Limits at +25°C are guaranteed by design and not production tested. Figure 1. Data Transfer on I2C Serial Bus

Figure 2. Power-Up/Power-Down Timing

ures and automatically switches to the backup supply. above VPF, read and write access is allowed tREC. X2, is floated if an external oscillator is connected to X1. result in improper operation. VBACKUP can be as high as 5.5V on the 3.3V device. to ensure against reverse charging when used with a lithium battery (www.maxim-ic.com/qa/info/ul). and requires an external pullup resistor. either VCC or VBACKUP applied. w r i tes ar e i nhi b i ted . H ow ever , the ti m ekeep i ng functi on conti nues unaffected b y the l ow er i np ut vol tag e. — 4–13 N.C. No Connection. Must be connected to ground. Table 1. Power Control

main registers update during a read. enabled. The initial power-up value of EOSC is 0. isters must be written within one second. charger, and oscillator flag output. Table 3. Address Map Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.

and 0 if OUT = 0. The initial power-up OUT value is 1. to 0, the OUT bit controls the state of the FT/OUT pin. The initial power-up value of FT is 0. operation. The initial power-up value of S is 0. no diode is selected; if DS is 10, a diode is selected. and the diode selected by the diode select (DS) bits.

1 OF 16 SELECT

1 OF 2

1 OF 3

Figure 6. Trickle Charger Functional Diagram

1) The first time power is applied. are insufficient to support oscillation. to logic 1 leaves the value unchanged. ing counts slows the clock down. bration. Calibration occurs within a 64-minute cycle. to +5.5 or -2.75 minutes per month. loaded in the S bit and the five calibration bits. the control register resets the divider chain. Table 4. Trickle-Charge Register

are defined. The DS1340 works in both modes.

• Data transfer can be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are inter- preted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. START data transfer: A change in the data line’s state from high to low, while the clock line is high, defines a START condition. STOP data transfer: A change in the data line’s state from low to high, while the clock line is high, defines a STOP condition. Data valid: The data line’s state represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condi- tion and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowl- edge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. DS1340 I2C RTC with Trickle Charger STOP CONDITION OR REPEATED START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED ACKSTART CONDITION ACK ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SLAVE ADDRESS MSB SCL SDA R/W DIRECTION BIT 12 6 7 8 9 1 2 89 3–7

Figure 7. I2C Data Transfer Overview

Handling, PC Board Layout, and Assembly The DS1340C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Exposure to reflow is limited to 2 times maximum. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connect- ed to ground. The leaded 16-pin SO package may be reflowed as long as the peak temperature does not exceed 240°C. Peak reflow temperature ( ≥ 230°C) duration should not exceed 10 seconds, and the total time above 200°C should not exceed 40 seconds (30 seconds nominal). The RoHS and lead-free/RoHS packages may be reflowed using a reflow profile that complies with JEDEC J-STD-020. Moisture-sensitive packages are shipped from the facto- ry dry-packed.Handling instructions listed on the pack- age label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. DS1340 I2C RTC with Trickle Charger VCC FT/OUT SCL SDA VBACKUP GND TOP VIEW DS1340 SO, µSOP DS1340C SCL SDA GND V BACKUP N.C. N.C. N.C. N.C. N.C. SO (300 mils) FT/OUT VCC N.C. N.C. N.C. N.C. N.C. Pin Configurations

I2C RTC with Trickle Charger Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.

Package Information

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Chip Information TRANSISTOR COUNT: 10,930 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND Thermal Information Theta-JA: +170°C/W (0.150in SO) Theta-JC: +40°C/W (0.150in SO) Theta-JA: +221°C/W (µSOP) Theta-JC: +39°C/W (µSOP) Theta-JA: +89.6°C/W (0.300in SO) Theta-JC: +24.8°C/W (0.300in SO) PACKAGE DOCUMENT NUMBER 8-pin SO (150 mils) 56-G2008-001 8-pin µSOP 56-G2018-001 16-pin SO (300 mils) 56-G4009-001