STW12NK90Z STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 1.1 Protection features of gate-to-source zener diodes
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

N-channel 900V - 0.72Ω - 11A - TO-247 Zener-protected SuperMESH™ Power MOSFET General features ■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Very good manufacturing repeatibility

Description

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products.

Applications

■ Switching application Internal schematic diagram Type V DSS RDS(on) ID pW STW12NK90Z 900V <0.88 Ω 11A 230W TO-247 Order codes Part number Marking Package Packaging STW12NK90Z W12NK90Z TO-247 Tube

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Pulse width limited by safe operating area.
  2. ISD ≤11A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.

Table 2. Thermal data Table 3. Avalanche characteristics Table 4. Gate-source zener diode

1.1 Protection features of gate-to-source zener diodes

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

2 Electrical characteristics

Table 5. On/off states Table 6. Dynamic

  1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
  2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

increases from 0 to 80% VDSS.

Table 7. Source drain diode

  1. Pulse width limited by safe operating area.
  2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

2.1 Electrical characteristi cs (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

3 Test circuit

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test

Figure 17. Unclamped inductive wavefo rm Figure 18. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 0.620 e5 . 4 5 0 . 2 1 4 L 14.20 14.80 0.560 0.582 L1 3.70 4.30 0.14 0.17 L2 18.50 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S5 . 5 0 0 . 2 1 6 TO-247 MECHANICAL DATA

5 Revision history

Table 8. Revision history