Microcontroller

12F615

Microchip Technology

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers 2006

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PIC12F609 MICROCHIP | Alldatasheet

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© 2006 Microchip Technology Inc. Preliminary DS41302A PIC12F609/HV609 PIC12F615/HV615 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers foreign patents and applications may be issued or pending.

© 2006 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

Only 35 instructions to learn: - All single-cycle instructions except branches
Operating speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle
Interrupt capability
8-level deep hardware stack
Direct, Indirect and Relative Addressing modes Special Microcontroller Features:
Precision Internal Oscillator: - Factory calibrated to ±1%, typical - Software selectable frequency: 4 MHz or

8 MHz

Power-Saving Sleep mode
Voltage range: - PIC12F609/615: 2.0V to 5.5V - PIC12HV609/615: 2.0V to user defined maximum (see note)
Industrial and Extended Temperature range
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Brown-out Reset (BOR)
Watchdog Timer (WDT) with independent oscillator for reliable operation
Multiplexed Master Clear with pull-up/input pin
Programmable code protection
High Endurance Flash: - 100,000 write Flash endurance - Flash retention: > 40 years Low-Power Features:
Standby Current: - 50 nA @ 2.0V, typical
Operating Current: - 11 μA @ 32 kHz, 2.0V, typical - 260 μA @ 4 MHz, 2.0V, typical
Watchdog Timer Current: - 1 μA @ 2.0V, typical Note: Voltage across the shunt regulator should not exceed 5V. Peripheral Features:
Shunt Voltage Regulator (PIC12HV609/615 only): - 5 volt regulation - 4 mA to 50 mA shunt range
5 I/O pins and 1 input only
High current source/sink for direct LED drive - Interrupt-on-pin change or pins - Individually programmable weak pull-ups
Analog Comparator module with: - One analog comparator - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and output externally accessible - Built-In Hysteresis (software selectable)
Timer0: 8-bit timer/counter with 8-bit programmable prescaler
Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected - Option to use system clock as Timer1
In-Circuit Serial ProgrammingTM (ICSPTM) via two pins PIC12F615/HV615 ONLY:
Enhanced Capture, Compare, PWM module: - 16-bit Capture, max. resolution 12.5 ns - Compare, max. resolution 200 ns - 10-bit PWM with 1 or 2 output channels, 1 output channel programmable “dead time”, max. frequency 20 kHz, auto-shutdown
A/D Converter: - 10-bit resolution and 4 channels, samples internal voltage references
Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

© 2006 Microchip Technology Inc. 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, TSSOP, DFN) TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN) Device Program Memory Data Memory I/O 10-bit A/D (ch) Comparators Timers 8/16-bit Voltage Range Flash (words) SRAM (bytes) PIC12F609 1024 2.0V-5.5V PIC12HV609 1024 2.0V-user defined PIC12F615 1024 2.0V-5.5V PIC12HV615 1024 2.0V-user defined I/O Pin Comparators Timer Interrupts Pull-ups Basic GP0 CIN+ IOC Y ICSPDAT GP1 CIN0- IOC Y ICSPCLK GP2 COUT T0CKI INT/IOC Y GP3(1) IOC Y(2) MCLR/VPP GP4 CIN1- T1G IOC Y OSC2/CLKOUT GP5 T1CKI IOC Y OSC1/CLKIN VDD VSS Note 1: Input only. Only when pin is configured for external MCLR. PIC12F609/ HV609 VSS GP0/CIN+/ICSPDAT GP1/CIN0-/ICSPCLK GP2/T0CKI/INT/COUT VDD GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/VPP

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 3 PIC12F609/615/12HV609/615 8-Pin Diagram, PIC12F615/HV615 (PDIP, SOIC, TSSOP, DFN) TABLE 2: PIC12F615/HV615 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN) I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic GP0 AN0 CIN+ P1B IOC Y ICSPDAT GP1 AN1 CIN0- IOC Y ICSPCLK/VREF GP2 AN2 COUT T0CKI CCP1/P1A INT/IOC Y GP3(1) T1G* IOC Y(2) MCLR/VPP GP4 AN3 CIN1- T1G P1B* IOC Y OSC2/CLKOUT GP5 T1CKI P1A* IOC Y OSC1/CLKIN VDD VSS Alternate pin function. Note 1: Input only. Only when pin is configured for external MCLR. PIC12F615/ HV615 VSS GP0/AN0/CIN+/P1B/ICSPDAT GP1/AN1/CIN0-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/P1A VDD GP5/T1CKI/P1A*/OSC1/CLKIN GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT GP3/T1G*/MCLR/VPP Alternate pin function.

© 2006 Microchip Technology Inc. Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

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© 2006 Microchip Technology Inc. Preliminary DS41302A-page 5 PIC12F609/615/12HV609/615 1.0 DEVICE OVERVIEW The PIC12F609/615/12HV609/615 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC, TSSOP and DFN packages. Block Diagrams and pinout descriptions of the devices are as follows:

PIC12F609/HV609 (Figure 1-1, Table 1-1)
PIC12F615/HV615 (Figure 1-2, Table 1-2) FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM Flash Program Memory Data Bus Program Bus Instruction Reg Program Counter RAM File Registers Direct Addr RAM Addr Addr MUX Indirect Addr FSR Reg STATUS Reg MUX ALU W Reg Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT GPIO 8-Level Stack

64 Bytes

(13-Bit) Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer MCLR VSS Brown-out Reset Timer0 Timer1 GP0 GP1 GP2 GP3 GP4 GP5 Analog Comparator T0CKI INT T1CKI Configuration Internal Oscillator and Reference T1G VDD Block CIN+ CIN0- CIN1- COUT Comparator Voltage Reference Absolute Voltage Reference Shunt Regulator (PIC12HV609 only)

© 2006 Microchip Technology Inc. FIGURE 1-2: PIC12F615/HV615 BLOCK DIAGRAM Flash Program Memory Data Bus Program Bus Instruction Reg Program Counter RAM File Registers Direct Addr RAM Addr Addr MUX Indirect Addr FSR Reg STATUS Reg MUX ALU W Reg Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT GPIO 8-Level Stack (13-Bit) Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer MCLR VSS Brown-out Reset Timer0 Timer1 GP0 GP1 GP2 GP3 GP4 GP5 Analog Comparator T0CKI INT T1CKI Configuration Internal Oscillator VREF and Reference T1G VDD Timer2 Block Shunt Regulator (PIC12HV615 only) Analog-To-Digital Converter AN0 AN1 AN2 AN3 CIN+ CIN0- CIN1- COUT ECCP CCP1/P1A P1B P1A* P1B* Comparator Voltage Reference Absolute Voltage Reference Alternate pin function. T1G*

Description

General purpose I/O with prog. pull-up and interrupt-on-change CIN+ AN Comparator non-inverting input ICSPDAT ST CMOS Serial Programming Data I/O GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change CIN0- AN Comparator inverting input ICSPCLK ST Serial Programming Clock GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change T0CKI ST Timer0 clock input INT ST External Interrupt COUT CMOS Comparator output GP3/MCLR/VPP GP3 TTL General purpose input with interrupt-on-change MCLR ST Master Clear w/internal pull-up VPP HV Programming voltage GP4/CIN1-/T1G/OSC2/ CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change CIN1- AN Comparator inverting input T1G ST Timer1 gate (count enable) OSC2 XTAL Crystal/Resonator CLKOUT CMOS FOSC/4 output GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change T1CKI ST Timer1 clock input OSC1 XTAL Crystal/Resonator CLKIN ST External clock input/RC oscillator connection VDD VDD Power Positive supply VSS VSS Power Ground reference Legend: AN = Analog input or output CMOS = CMOS compatible input or output HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal

© 2006 Microchip Technology Inc. TABLE 1-2: PIC12F615/HV615 PINOUT DESCRIPTION Name Function Input Type Output Type General purpose I/O with prog. pull-up and interrupt-on- change AN0 AN A/D Channel 0 input CIN+ AN Comparator non-inverting input P1B CMOS PWM output ICSPDAT ST CMOS Serial Programming Data I/O GP1/AN1/CIN0-/VREF/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on- change AN1 AN A/D Channel 1 input CIN0- AN Comparator inverting input VREF AN External Voltage Reference for A/D ICSPCLK ST Serial Programming Clock GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on- change AN2 AN A/D Channel 2 input T0CKI ST Timer0 clock input INT ST External Interrupt COUT CMOS Comparator output CCP1 ST CMOS Capture input/Compare input/PWM output P1A CMOS PWM output GP3/T1G*/MCLR/VPP GP3 TTL General purpose input with interrupt-on-change T1G* ST Timer1 gate (count enable), alternate pin MCLR ST Master Clear w/internal pull-up VPP HV Programming voltage GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on- change AN3 AN A/D Channel 3 input CIN1- AN Comparator inverting input T1G ST Timer1 gate (count enable) P1B* CMOS PWM output, alternate pin OSC2 XTAL Crystal/Resonator CLKOUT CMOS FOSC/4 output GP5/T1CKI/P1A*/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on- change T1CKI ST Timer1 clock input P1A* CMOS PWM output, alternate pin OSC1 XTAL Crystal/Resonator CLKIN ST External clock input/RC oscillator connection VDD VDD Power Positive supply VSS VSS Power Ground reference Alternate pin function. Legend: AN = Analog input or output CMOS=CMOS compatible input or output HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL= Crystal

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 9 PIC12F609/615/12HV609/615 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F609/615/12HV609/615 has a 13-bit pro- gram counter capable of addressing an 8K x 14 pro- gram memory space. Only the first 1K x 14 (0000h- 03FFh) for the PIC12F609/615/12HV609/615 is physi- cally implemented. Accessing a location above these boundaries will cause a wraparound within the first 1K x 14 space. The Reset vector is at 0000h and the inter- rupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC12F609/615/12HV609/615 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. The RP0 bit of the STATUS register is the bank select bit. RP0 Bank 0 is selected Bank 1 is selected 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the PIC12F609/615/12HV609/615. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. PC<12:0> 0000h 0004h 0005h 03FFh 0400h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory CALL, RETURN RETFIE, RETLW Stack Level 2 Wraps to 0000h-07FFh Note: The IRP and RP1 bits of the STATUS register are reserved and should always be maintained as ‘0’s.

© 2006 Microchip Technology Inc. FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F609/HV609 FIGURE 2-3: DATA MEMORY MAP OF THE PIC12F615/HV615 Indirect Addr.(1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note Not a physical register. General Purpose Registers Indirect Addr.(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h FFh Bank 1 ANSEL Accesses 70h-7Fh F0h VRCON CMCON0 OSCTUNE 40h 3Fh CMCON1 EFh T1CON Indirect Addr.(1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note Not a physical register. General Purpose Registers Indirect Addr.(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h FFh Bank 1 ADRESH ADCON0 ADRESL ANSEL Accesses 70h-7Fh F0h TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS VRCON CMCON0 OSCTUNE PR2 40h 3Fh CMCON1 EFh APFCON

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 11 PIC12F609/615/12HV609/615 TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 100 01h TMR0 Timer0 Module’s Register xxxx xxxx 41, 100 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 100 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 15, 100 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 100 05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 100 06h Unimplemented 07h Unimplemented 08h Unimplemented 09h Unimplemented 0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 100 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 100 0Ch PIR1 CMIF TMR1IF ---- 0--0 19, 100 0Dh Unimplemented 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 100 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 100 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 49, 100 11h Unimplemented 12h Unimplemented 13h Unimplemented 14h Unimplemented 15h Unimplemented 16h Unimplemented 17h Unimplemented 18h Unimplemented 19h VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101 1Ah CMCON0 CMON COUT CMOE CMPOL CMR CMCH 0000 -0-0 58, 101 1Bh 1Ch CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 59, 101 1Dh Unimplemented 1Eh Unimplemented 1Fh Unimplemented Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note IRP and RP1 bits are reserved, always maintain these bits clear.

© 2006 Microchip Technology Inc. TABLE 2-2: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101 01h TMR0 Timer0 Module’s Register xxxx xxxx 41, 101 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 15, 101 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101 05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 101 06h Unimplemented 07h Unimplemented 08h Unimplemented 09h Unimplemented 0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 101 0Ch PIR1 ADIF CCP1IF CMIF TMR2IF TMR1IF -00- 0-00 19, 101 0Dh Unimplemented 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 49, 101 11h TMR2 Timer2 Module Register 0000 0000 51, 101 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 101 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 76, 101 14h CCPR1H Capture/Compare/PWM Register 1 High Byte XXXX XXXX 76, 101 15h CCP1CON P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 75, 101 16h PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 91, 101 17h ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 88, 101 18h Unimplemented 19h VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101 1Ah CMCON0 CMON COUT CMOE CMPOL CMR CMCH 0000 -0-0 58, 101 1Bh 1Ch CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 59, 101 1Dh Unimplemented 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 71, 101 1Fh ADCON0 ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 70, 101 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note IRP and RP1 bits are reserved, always maintain these bits clear.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 13 PIC12F609/615/12HV609/615 TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16, 101 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 15, 101 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101 85h TRISIO TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 31, 101 86h Unimplemented 87h Unimplemented 88h Unimplemented 89h Unimplemented 8Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 17, 101 8Ch PIE1 CMIE TMR1IE ---- 0--0 18, 101 8Dh Unimplemented 8Eh PCON POR BOR ---- --qq 20, 101 8Fh Unimplemented 90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 101 91h Unimplemented 92h Unimplemented 93h Unimplemented 94h Unimplemented 95h WPU(2) WPU5 WPU4 WPU2 WPU1 WPU0 --11 -111 34, 101 96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 101 97h Unimplemented 98h Unimplemented 99h Unimplemented 9Ah Unimplemented 9Bh Unimplemented 9Ch Unimplemented 9Dh Unimplemented 9Eh Unimplemented 9Fh ANSEL ANS3 ANS1 ANS0 ---- 1-11 33, 101 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note IRP and RP1 bits are reserved, always maintain these bits clear. GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. TRISIO3 always reads as ‘1’ since it is an input only pin.

© 2006 Microchip Technology Inc. TABLE 2-4: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16, 101 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 15, 101 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101 85h TRISIO TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 31, 101 86h Unimplemented 87h Unimplemented 88h Unimplemented 89h Unimplemented 8Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 17, 101 8Ch PIE1 ADIE CCP1IE CMIE TMR2IE TMR1IE -00- 0-00 18, 101 8Dh Unimplemented 8Eh PCON POR BOR ---- --qq 20, 101 8Fh Unimplemented 90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 29, 101 91h Unimplemented 92h PR2 Timer2 Module Period Register 1111 1111 51, 101 93h APFCON T1GSEL P1BSEL P1ASEL ---0 --00 18, 101 94h Unimplemented 95h WPU(2) WPU5 WPU4 WPU2 WPU1 WPU0 --11 -111 34, 101 96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 101 97h Unimplemented 98h Unimplemented 99h Unimplemented 9Ah Unimplemented 9Bh Unimplemented 9Ch Unimplemented 9Dh Unimplemented 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 71, 101 9Fh ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 33, 101 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note IRP and RP1 bits are reserved, always maintain these bits clear. GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. TRISIO3 always reads as ‘1’ since it is an input only pin.

the arithmetic status of the ALU
the Reset status
the bank select bits for data memory (RAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affect- ing any Status bits, see the Section 13.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F609/615/ 12HV609/615 and should be maintained as clear. Use of these bits is not recom- mended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 2-1: STATUS: STATUS REGISTER Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h – FFh) 0 = Bank 0 (00h – 7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

Timer0/WDT prescaler
External GP2/INT interrupt
Timer0
Weak pull-ups on GPIO Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 BIT VALUE TIMER0 RATE WDT RATE

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 17 PIC12F609/615/12HV609/615 2.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE GPIE T0IF INTF GPIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt bit 3 GPIE: GPIO Change Interrupt Enable bit(1) 1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow bit 1 INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur bit 0 GPIF: GPIO Change Interrupt Flag bit 1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state Note 1: IOC register must also be enabled. T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit.

© 2006 Microchip Technology Inc. 2.2.2.4 PIE1 Register The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-4. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(1) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit(1) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 19 PIC12F609/615/12HV609/615 2.2.2.5 PIR1 Register The PIR1 register contains the Peripheral Interrupt flag bits, as shown in Register 2-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Interrupt Flag bit(1) 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit 1 = Comparator output has changed (must be cleared in software) 0 = Comparator output has not changed bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1) 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 21 PIC12F609/615/12HV609/615 2.2.2.7 APFCON Register (PIC12F615/HV615 only) The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins. The APFCON register bits are shown in Register 2-7. REGISTER 2-7: APFCON: POWER CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 T1GSEL P1BSEL P1ASEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1GSEL: TMR1 Input Pin Select bit 1 = T1G function is on GP3/T1G(2)/MCLR/VPP 0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT bit 3-2 Unimplemented: Read as ‘0’ bit 1 P1BSEL: P1B Output Pin Select bit 1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT bit 0 P1ASEL: P1A Output Pin Select bit 1 = P1A function is on GP5/T1CKI/P1A(2)/OSC1/CLKIN 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Note 1: PIC12F615/HV615 only. Alternate pin function.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 23 PIC12F609/615/12HV609/615 FIGURE 2-5: DIRECT/INDIRECT ADDRESSING PIC12F609/615/12HV609/615 Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. Accesses in this area are mirrored back into Bank 0 and Bank 1. Data Memory Indirect Addressing Direct Addressing Bank Select Location Select RP1(1) RP0 From Opcode IRP(1) File Select Register Bank Select Location Select 180h 1FFh 00h 7Fh Bank 0 Bank 1 Bank 2 Bank 3 NOT USED(2) For memory map detail, see Figure 2-2.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 25 PIC12F609/615/12HV609/615 3.0 OSCILLATOR MODULE 3.1 Overview The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured with a choice of two selectable speeds: internal or external system clock source. The Oscillator module can be configured in one of eight clock modes. EC – External clock with I/O on OSC2/CLKOUT. LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS – High Gain Crystal or Ceramic Resonator mode. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. RCIO – External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The Internal Oscillator module provides a selectable system clock mode of either 4 MHz (Postscaler) or 8 MHz (INTOSC). FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM (CPU and Peripherals) OSC1 OSC2 Sleep External Oscillator LP, XT, HS, RC, RCIO, EC System Clock MUX FOSC<2:0> (Configuration Word Register) Internal Oscillator INTOSC

4 MHz

IOSCFS<7>

External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator mod- ules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.
Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two selectable clock frequencies:

4 MHz and 8 MHz

The system clock can be selected between external or internal clock sources via the FOSC<2:0> bits of the Configuration Word register. 3.3 External Clock Modes 3.3.1 OSCILLATOR START-UP TIMER (OST) If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1. TABLE 3-1: OSCILLATOR DELAY EXAMPLES 3.3.2 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION Switch From Switch To Frequency Oscillator Delay Sleep/POR INTOSC 125 kHz to 8 MHz Oscillator Warm-Up Delay (TWARM) Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles Sleep/POR LP, XT, HS 32 kHz to 20 MHz

1024 Clock Cycles (OST)

OSC2/CLKOUT(1) I/O Clock from Ext. System PIC® MCU Note Alternate pin functions are listed in the Section 1.0 “Device Overview”.

© 2006 Microchip Technology Inc. 3.3.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections. FIGURE 3-5: EXTERNAL RC MODES In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are:

threshold voltage variation
component tolerances
packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. 3.4 Internal Clock Modes The Oscillator module provides a selectable system clock source of either 4 MHz or 8 MHz. The selectable frequency is configured through the IOSCFS bit of the Configuration Word. The frequency of the internal oscillator can be trimmed with a calibration value in the OSCTUNE register. 3.4.1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 11.0 “Special Features of the CPU” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. OSC2/CLKOUT(1) CEXT REXT PIC® MCU OSC1/CLKIN FOSC/4 or Internal Clock VDD VSS Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V 3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V CEXT > 20 pF, 2-5V Note Alternate pin functions are listed in Section 1.0 “Device Overview”. Output depends upon RC or RCIO Clock mode. I/O(2)

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 29 PIC12F609/615/12HV609/615 3.4.1.1 OSCTUNE Register The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = 10000 = Minimum frequency Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets(1) CONFIG(2) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (Register 11-1) for operation of all register bits.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 31 PIC12F609/615/12HV609/615 4.0 I/O PORT There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.1 GPIO and the TRISIO Registers GPIO is a 6-bit wide port with 5 bidirectional and 1 input-only pin. The corresponding data direction register is TRISIO (Register 4-2). Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., disable the output driver). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is GP3, which is input only and its TRIS bit will always read as ‘1’. Example 4-1 shows how to initialize GPIO. Reading the GPIO register (Register 4-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1. The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. EXAMPLE 4-1: INITIALIZING GPIO Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. BANKSEL GPIO CLRF GPIO ;Init GPIO BANKSEL ANSEL CLRF ANSEL ;digital I/O, ADC clock ;setting ‘don’t care’ MOVLW 0Ch ;Set GP<3:2> as inputs MOVWF TRISIO ;and set GP<5:4,1:0> ;as outputs REGISTER 4-1: GPIO: GPIO REGISTER U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0 GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GP<5:0>: GPIO I/O Pin bit 1 = GPIO pin is > VIH 0 = GPIO pin is < VIL REGISTER 4-2: TRISIO: GPIO TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note TRISIO<3> always reads ‘1’. TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

© 2006 Microchip Technology Inc. 4.2 Additional Pin Functions Every GPIO pin on the PIC12F609/615/12HV609/615 has an interrupt-on-change option and a weak pull-up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. 4.2.2 WEAK PULL-UPS Each of the GPIO pins, except GP3, has an individually configurable internal weak pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 4-5. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit of the OPTION register). A weak pull-up is automatically enabled for GP3 when configured as MCLR and disabled when GP3 is an I/O. There is no software control of the MCLR pull-up. 4.2.3 INTERRUPT-ON-CHANGE Each GPIO pin is individually configurable as an inter- rupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register 4-6. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO. The ‘mismatch’ outputs of the last read are OR’d together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the inter- rupt by: Any read of GPIO AND Clear flag bit GPIF. This will end the mismatch condition; OR Any write of GPIO AND Clear flag bit GPIF will end the mismatch condition; A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 33 PIC12F609/615/12HV609/615 REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609) U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 ANS3 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS3: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. bit 2 Unimplemented: Read as ‘0’ bit 1 ANS1: Analog Select Between Analog or Digital Function on Pins GP1 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. bit 0 ANS0: Analog Select Between Analog or Digital Function on Pins GP0 0 = Digital I/O. Pin is assigned to port or special function. 1 = Analog input. Pin is assigned as analog input.(1) Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 4-4: ANSEL: ANALOG SELECT REGISTER (PIC12F615/HV615) U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 ANS<3:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

© 2006 Microchip Technology Inc. REGISTER 4-5: WPU: WEAK PULL-UP GPIO REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 WPU5 WPU4 WPU2 WPU1 WPU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPU<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. WPU<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. REGISTER 4-6: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. IOC<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

© 2006 Microchip Technology Inc. TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL ADCS2(1) ADCS1(1) ADCS0(1) ANS3 ANS2(1) ANS1 ANS0 -000 1111 -000 1111 CMCON0 CMON COUT CMOE CMPOL CMR CMCH 0000 -0-0 0000 -0-0 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 --u0 u000 TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 WPU WPU5 WPU4 WPU2 WPU1 WPU0 --11 -111 --11 -111 T1CON T1OSCEN ---- 0--- CCP1CON CCP1M3 CCP1M2 CCP1M1 CCP1M0 ---- 0000 APFCON T1GSEL P1BSEL P1ASEL ---0 --00 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. Note PIC12F615/HV615 only.

8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow Figure 5-1 is a block diagram of the Timer0 module. 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 5.1.1 8-BIT TIMER MODE When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. 5.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. T0CKI T0SE pin TMR0 Watchdog Timer WDT Time-out PS<2:0> WDTE Data Bus Set Flag bit T0IF on Overflow T0CS Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. WDTE bit is in the Configuration Word register. 8-bit Prescaler FOSC/4 PSA PSA PSA Sync

2 TCY

© 2006 Microchip Technology Inc. 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. 5.1.3.1 Switching Prescaler Between Timer0 and WDT Modules As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 5-1, must be executed. EXAMPLE 5-1: CHANGING PRESCALER (TIMER0 →WDT) When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2). EXAMPLE 5-2: CHANGING PRESCALER (WDT →TIMER0) 5.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. 5.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 15.0 “Electrical Specifications”. BANKSEL TMR0 CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and ;prescaler BANKSEL OPTION_REG BSF OPTION_REG,PSA ;Select WDT CLRWDT MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. CLRWDT ;Clear WDT and ;prescaler BANKSEL OPTION_REG MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 43 PIC12F609/615/12HV609/615 TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 BIT VALUE TMR0 RATE WDT RATE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.

16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
3-bit prescaler
Optional LP oscillator
Synchronous or asynchronous operation
Timer1 gate (count enable) via comparator or T1G pin
Interrupt on overflow
Wake-up on overflow (external clock, Asynchronous mode only)
Time base for the Capture/Compare function
Special Event Trigger (with ECCP)
Comparator output synchronization to Timer1 clock Figure 6-1 is a block diagram of the Timer1 module. 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally. Clock Source TMR1CS T1ACS FOSC/4 FOSC T1CKI pin x

© 2006 Microchip Technology Inc. FIGURE 6-1: TIMER1 BLOCK DIAGRAM TMR1H TMR1L Oscillator T1SYNC T1CKPS<1:0> FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronized clock input Set flag bit TMR1IF on Overflow TMR1(2) TMR1GE TMR1ON T1OSCEN COUT T1GSS T1GINV To Comparator Module Timer1 Clock TMR1CS OSC2/T1G OSC1/T1CKI Note ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. Alternate pin function. PIC12F615/HV615 only. (1) EN INTOSC Without CLKOUT T1ACS FOSC T1GSEL(2) GP3/T1G(4, 5) Synchronize(3) det

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 47 PIC12F609/615/12HV609/615 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions:

Timer1 is enabled after POR or BOR Reset
A write to TMR1H or TMR1L
T1CKI is high when Timer1 is disabled and when Timer1 is reenabled T1CKI is low. See Figure 6-2. 6.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 6.4 Timer1 Oscillator A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscilla- tor start-up. TRISIO5 and TRISIO4 bits are set when the Timer1 oscillator is enabled. GP5 and GP4 bits read as ‘0’ and TRISIO5 and TRISIO4 bits read as ‘1’. 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). 6.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair. 6.6 Timer1 Gate Timer1 gate source is software configurable to be the T1G pin (or the alternate T1G pin) or the output of the Comparator. This allows the device to directly time external events using T1G or analog events using the Comparator. See the CMCON1 Register (Register 8-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or the Comparator output. This configures Timer1 to measure either the active-high or active-low time between events. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment. Note: TMR1GE bit of the T1CON register must be set to use either T1G or COUT as the Timer1 gate source. See Register 8-2 for more information on selecting the Timer1 gate source.

© 2006 Microchip Technology Inc. 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits:

Timer1 interrupt enable bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. 6.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). 6.9 ECCP Capture/Compare Time Base (PIC12F615/HV615 only) The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 10.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)”. 6.10 ECCP Special Event Trigger (PIC12F615/HV615 only) If a ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L regis- ter pair effectively becomes the period register for Timer1. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write will take precedence. For more information, see Section 10.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/HV615 only)”. 6.11 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. FIGURE 6-2: TIMER1 INCREMENTING EDGE Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 49 PIC12F609/615/12HV609/615 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. LP oscillator is disabled. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source.

© 2006 Microchip Technology Inc. TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets APFCON(1) T1GSEL P1BSEL P1ASEL ---0 --00 ---0 --00 CMCON0 CMON COUT CMOE CMPOL CMR CMCH 0000 -0-0 0000 -0-0 CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 ---0 0-10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note PIC12F615/HV615 only.

8-bit timer register (TMR2)
8-bit period register (PR2)
Interrupt on TMR2 match with PR2
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16) See Figure 7-1 for a block diagram of Timer2. 7.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen:
TMR2 is reset to 00h on the next increment cycle.
The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when:
A write to TMR2 occurs.
A write to T2CON occurs.
Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). FIGURE 7-1: TIMER2 BLOCK DIAGRAM Note: TMR2 is not cleared when T2CON is written. Comparator TMR2 Sets Flag TMR2 Output Reset Postscaler Prescaler PR2 FOSC/4 1:1 to 1:16 1:1, 1:4, 1:16 EQ bit TMR2IF TOUTPS<3:0> T2CKPS<1:0>

© 2006 Microchip Technology Inc. TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 PR2 Timer2 Module Period Register 1111 1111 1111 1111 TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note For PIC12F615/HV615 only.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 55 PIC12F609/615/12HV609/615 8.3 Comparator Control The comparator has two control and Configuration reg- isters: CMCON0 and CMCON1. The CMCON1 register is used for controlling the interaction with Timer1 and simultaneously reading the comparator output. The CMCON0 register (Register 8-1) contain the control and Status bits for the following:

Enable
Input selection
Reference selection
Output selection
Output polarity 8.3.1 COMPARATOR ENABLE Setting the CMON bit of the CMCON0 register enables the comparator for operation. Clearing the CMON bit disables the comparator for minimum current consumption. 8.3.2 COMPARATOR INPUT SELECTION The CMCH bit of the CMCON0 register directs one of four analog input pins to the comparator inverting input. 8.3.3 COMPARATOR REFERENCE SELECTION Setting the CMR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 8.10 “Comparator Voltage Reference” for more information on the internal voltage reference module. 8.3.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by reading either the COUT bit of the CMCON0 register. In order to make the output available for an external connection, the following conditions must be true:
CMOE bit of the CMxCON0 register must be set
Corresponding TRIS bit must be cleared
CMON bit of the CMCON0 register must be set. 8.3.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register. Clear- ing CMPOL results in a non-inverted output. A com- plete table showing the output state versus input conditions and the polarity bit is shown in Table 8-1. TABLE 8-1: OUTPUT STATE VS. INPUT CONDITIONS 8.4 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the compara- tor differs from the settling time of the voltage refer- ence. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See Section 15.0 “Electrical Specifications” for more details. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. Note 1: The CMOE bit overrides the PORT data latch. Setting the CMON has no impact on the port override. The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. Input Conditions CMPOL COUT CMVIN- > CMVIN+ CMVIN- < CMVIN+ CMVIN- > CMVIN+ CMVIN- < CMVIN+ Note: COUT refers to both the register bit and output pin.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 57 PIC12F609/615/12HV609/615 8.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by clearing the CMON bit of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CMIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.7 Effects of a Reset A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state.

© 2006 Microchip Technology Inc. REGISTER 8-1: CMCON0: COMPARATOR CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 CMON COUT CMOE CMPOL CMR CMCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CMON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COUT: Comparator Output bit If C1POL = 1 (inverted polarity): COUT = 0 when CMVIN+ > CMVIN- COUT = 1 when CMVIN+ < CMVIN- If C1POL = 0 (non-inverted polarity): COUT = 1 when CMVIN+ > CMVIN- COUT = 0 when CMVIN+ < CMVIN- bit 5 CMOE: Comparator Output Enable bit 1 = COUT is present on the COUT pin(1) 0 = COUT is internal only bit 4 CMPOL: Comparator Output Polarity Select bit 1 = COUT logic is inverted 0 = COUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CMR: Comparator Reference Select bit (non-inverting input) 1 = CMVIN+ connects to CMVREF output 0 = CMVIN+ connects to CIN+ pin bit 1 Unimplemented: Read as ‘0’ bit 0 CMCH: Comparator C1 Channel Select bit 00 = CMVIN- pin of the Comparator connects to CIN0- 01 = CMVIN- pin of the Comparator connects to CIN1- Note 1: Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corresponding port TRIS bit = 0.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 59 PIC12F609/615/12HV609/615 8.8 Comparator Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details. It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the compara- tor is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. 8.9 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 8-2) and the Timer1 Block Diagram (Figure 6-1) for more information. REGISTER 8-2: CMCON1: COMPARATOR CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-0 T1ACS CMHYS T1GSS CMSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1ACS: Timer1 Alternate Clock Select bit 1 = Timer 1 Clock Source is System Clock (FOSC) 0 = Timer 1 Clock Source is Instruction Clock (FOSC\\4) bit 3 CMHYS: Comparator Hysteresis Select bit 1 = Comparator Hysteresis enabled 0 = Comparator Hysteresis disabled bit 2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer 1 Gate Source is comparator output bit 0 CMSYNC: Comparator Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. Refer to Figure 8-2.

© 2006 Microchip Technology Inc. 8.10 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the com- parators. The following features are available:

Independent from Comparator operation
16-level voltage range
Output clamped to VSS
Ratiometric with VDD
Fixed Reference (0.6) The VRCON register (Register 8-3) controls the Volt- age Reference module shown in Register 8-6. 8.10.1 INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference. 8.10.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is con- trolled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON reg- ister. The CVREF output voltage is determined by the following equations: EQUATION 8-1: CVREF OUTPUT VOLTAGE The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 8-6. 8.10.3 OUTPUT CLAMPED TO VSS The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows:
VREN = 0
VRR = 1
VR<3:0> = 0000 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current. 8.10.4 OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 15.0 “Electrical Specifications”. 8.10.5 FIXED VOLTAGE REFERENCE The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be enabled by setting the FVREN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 8.10.6 FIXED VOLTAGE REFERENCE STABILIZATION PERIOD When the Fixed Voltage Reference module is enabled, it will require some time for the reference and its ampli- fier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See Section 15.0 “Electrical Specifications” for the minimum delay requirement. 8.10.7 VOLTAGE REFERENCE SELECTION Multiplexers on the output of the Voltage Reference module enable selection of either the CVREF or fixed voltage reference for use by the comparators. Setting the CMVREN bit of the VRCON register enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by the Compar- ator. Clearing the CMVREN bit selects the fixed voltage for use by the Comparator. When the CMVREN bit is cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral. VRR 1 (low range): VRR 0 (high range): CVREF (VDD/4) + CVREF (VR<3:0>/24) VDD (VR<3:0> VDD/32)

16 Stages

CVREF(1) Reference EN FVREN Sleep HFINTOSC enable 0.6V FixedRef To Comparators and ADC Module To Comparators and ADC Module Note 1: Care should be taken to ensure CVREF remains within the comparator common mode input range. See Section 15.0 “Electrical Specifications” for more detail.

© 2006 Microchip Technology Inc. REGISTER 8-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMVREN VRR FVREN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CMVREN: Comparator Voltage Reference Enable bit(1, 2) 1 = CVREF circuit powered on and routed to CVREF input of the Comparator 0 = 0.6 Volt constant reference routed to CMVREF input of the Comparator bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 FVREN: 0.6V Reference Enable bit(2) 1 = Enabled 0 = Disabled bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Note 1: When CMVREN is low, the CVREF circuit is powered down and does not contribute to IDD current. When CMVREN is low and the FVREN bit is low, the CMVREF signal should provide Vss to the comparator.

© 2006 Microchip Technology Inc. TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CMCON0 CMON COUT CMOE CMPOL CMR CMCH 0000 -000 0000 -000 CMCON1 T1ACS CMHYS T1GSS CMSYNC 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 GPIO GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 0-00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note For PIC12F615/HV615 only.

Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding port section for more information. 9.1.2 CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 9.2 “ADC Operation” for more information. 9.1.3 ADC VOLTAGE REFERENCE The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference. 9.1.4 CONVERSION CLOCK The source of the conversion clock is software select- able via the ADCS bits of the ANSEL register. There are seven possible clock options:
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 9-3. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 15.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 67 PIC12F609/615/12HV609/615 TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES 9.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 9.1.5 “Interrupts” for more information. ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0>

20 MHz

1 MHz

100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs 8.0 μs(3) FOSC/16 101 800 ns(2) 2.0 μs 4.0 μs 16.0 μs(3) FOSC/32 010 1.6 μs 4.0 μs 8.0 μs(3) 32.0 μs(3) FOSC/64 110 3.2 μs 8.0 μs(3) 16.0 μs(3) 64.0 μs(3) FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 Set GO/DONE bit Holding Capacitor is Disconnected from Analog Input (typically 100 ns) TAD10 TAD11 TCY to TAD Conversion Starts ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 69 PIC12F609/615/12HV609/615 9.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: Configure Port:

Disable pin output driver (See TRIS register)
Configure pin as analog Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Select result format
Turn on ADC module Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 9-1: A/D CONVERSION Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. See Section 9.3 “A/D Acquisition Requirements”. ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ;Conversion start & polling for completion ; are included. BANKSEL TRISIO BSF TRISIO,0 ;Set GP0 to input BANKSEL ANSEL MOVLW B’01110001’ ;ADC Frc clock, IORWF ANSEL ; and GP0 as analog BANKSEL ADCON0 MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;Store in GPR space BANKSEL ADRESL MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space

© 2006 Microchip Technology Inc. 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VSS bit 5 Unimplemented: Read as ‘0’ bit 4-2 CHS<2:0>: Analog Channel Select bits 000 = Channel 00 (AN0) 001 = Channel 01 (AN1) 010 = Channel 02 (AN2) 011 = Channel 03 (AN3) 100 = CVREF 101 = 0.6V Reference 110 = 1.2V Reference 111 = Reserved. Do not use. bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: When the CHS<2:0> bits change to select the 1.2V or 0.6V reference, the reference output voltage will have a transient. If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 71 PIC12F609/615/12HV609/615 REGISTER 9-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY) R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Unimplemented: Read as ‘0’ REGISTER 9-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY) U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 9-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result

© 2006 Microchip Technology Inc. 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4. The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. EQUATION 9-1: ACQUISITION TIME EXAMPLE TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient TAMP TC TCOFF 2µs TC Temperature - 25°C ) 0.05µs/°C TC CHOLD RIC RSS RS ) ln(1/2047) 10pF 1kΩ 7kΩ 10kΩ ln(0.0004885) 1.37 µs TACQ 2µS 1.37µS 50°C- 25°C ) 0.05µS/°C 4.67µS VAPPLIED 1 e Tc RC VAPPLIED 1 2047 VAPPLIED 1 2047 VCHOLD VAPPLIED 1 e TC RC VCHOLD ;[1] VCHOLD charged to within 1/2 lsb ;[2] VCHOLD charge response to VAPPLIED ;combining [1] and [2] The value for TC can be approximated with the following equations: Solving for TC: Therefore: Temperature 50°C and external impedance of 10kΩ 5.0V VDD Assumptions: Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. The charge holding capacitor (CHOLD) is not discharged after each conversion. The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 73 PIC12F609/615/12HV609/615 FIGURE 9-4: ANALOG INPUT MODEL FIGURE 9-5: ADC TRANSFER FUNCTION CPIN VA Rs ANx 5 pF VDD VT = 0.6V VT = 0.6V I LEAKAGE RIC ≤ 1k Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF- Sampling Switch 5 6 7 8 9 10 11 (kΩ) VDD ± 500 nA Legend: CPIN VT I LEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage current at the pin due to = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance various junctions RSS 3FFh 3FEh ADC Output Code 3FDh 3FCh 004h 003h 002h 001h 000h Full-Scale 3FBh

1 LSB ideal

© 2006 Microchip Technology Inc. TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000 ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 --x0 x000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note For PIC12F615/HV615 only.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 75 PIC12F609/615/12HV609/615 10.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTO- SHUTDOWN AND DEAD BAND) MODULE (PIC12F615/HV615 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table 10-1 shows the timer resources required by the ECCP module. TABLE 10-1: ECCP MODE – TIMER RESOURCES REQUIRED ECCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 REGISTER 10-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 P1M: PWM Output Configuration bits x = P1A assigned as Capture/Compare input; P1B assigned as port pins If CCP1M<3:2> = 11: 0 = Single output; P1A modulated; P1B assigned as port pins 1 = Half-Bridge output; P1A, P1B modulated with dead-band control bit 6 Unimplemented: Read as ‘0’ bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 and starts an A/D conversion, if the ADC module is enabled) 1100 = PWM mode; P1A active-high; P1B active-high 1101 = PWM mode; P1A active-high; P1B active-low 1110 = PWM mode; P1A active-low; P1B active-high 1111 = PWM mode; P1A active-low; P1B active-low

© 2006 Microchip Technology Inc. 10.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register:

Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (see Figure 10-1). 10.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. FIGURE 10-1: CAPTURE MODE OPERATION BLOCK DIAGRAM 10.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 10.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode. 10.1.4 CCP PRESCALER There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (see Example 10-1). EXAMPLE 10-1: CHANGING BETWEEN CAPTURE PRESCALERS Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition. CCPR1H CCPR1L TMR1H TMR1L Set Flag bit CCP1IF (PIR1 register) Capture Enable CCP1CON<3:0> Prescaler ÷ 1, 4, 16 and Edge Detect pin CCP1 System Clock (FOSC) BANKSEL CCP1CON ;Set Bank bits to point ;to CCP1CON CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 77 PIC12F609/615/12HV609/615 TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCP1CON P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture. Note For PIC12F615/HV615 only.

© 2006 Microchip Technology Inc. 10.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may:

Toggle the CCP1 output.
Set the CCP1 output.
Clear the CCP1 output.
Generate a Special Event Trigger.
Generate a Software Interrupt. The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt. FIGURE 10-2: COMPARE MODE OPERATION BLOCK DIAGRAM 10.2.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. 10.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. 10.2.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register). 10.2.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following:
Resets Timer1
Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch. CCPR1H CCPR1L TMR1H TMR1L Comparator Q S R Output Logic Special Event Trigger Set CCP1IF Interrupt Flag (PIR1) Match TRIS CCP1CON<3:0> Mode Select Output Enable Pin Special Event Trigger will: Clear TMR1H and TMR1L registers. NOT set interrupt flag bit TMR1IF of the PIR1 register. Set the GO/DONE bit to start the ADC conversion. CCP1 Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 79 PIC12F609/615/12HV609/615 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets CCP1CON P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR2 Timer2 Module Register 0000 0000 0000 0000 TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare. Note For PIC12F615/HV615 only.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 81 PIC12F609/615/12HV609/615 10.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 10-1. EQUATION 10-1: PWM PERIOD When TMR2 is equal to PR2, the following three events occur on the next increment cycle:

TMR2 is cleared
The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPR1L into CCPR1H. 10.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 10-2 is used to calculate the PWM pulse width. Equation 10-3 is used to calculate the PWM duty cycle ratio. EQUATION 10-2: PULSE WIDTH EQUATION 10-3: DUTY CYCLE RATIO The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure 10-3). 10.3.3 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 10-4. EQUATION 10-4: PWM RESOLUTION TABLE 10-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) TABLE 10-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) Note: The Timer2 postscaler (see Section 7.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. PWM Period PR2 TOSC (TMR2 Prescale Value) Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. Pulse Width CCPR1L:CCP1CON<5:4> TOSC (TMR2 Prescale Value) Duty Cycle Ratio CCPR1L:CCP1CON<5:4>

4 PR2

( ) log PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 6.6 PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits)

© 2006 Microchip Technology Inc. 10.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 10.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 3.0 “Oscillator Module” for additional details. 10.3.6 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 10.3.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: Disable the PWM pin (CCP1) output drivers by setting the associated TRIS bit. Set the PWM period by loading the PR2 register. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. Set the PWM duty cycle by loading the CCPR1L register and DC1B bits of the CCP1CON register. Configure and start Timer2:

Clear the TMR2IF interrupt flag bit of the PIR1 register.
Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register.
Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output after a new PWM cycle has started:
Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set).
Enable the CCP1 pin output driver by clear- ing the associated TRIS bit.

© 2006 Microchip Technology Inc. 10.4.2 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each PWM output pin (P1A and P1B). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A and P1B output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external cir- cuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 87 PIC12F609/615/12HV609/615 10.4.3 ENHANCED PWM AUTO- SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPASx bits of the ECCPAS register. A shutdown event may be generated by:

A logic ‘0’ on the INT pin
Comparator
Setting the ECCPASE bit in firmware A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. Refer to Figure 1. When a shutdown event occurs, two things happen: The ECCPASE bit is set to ‘1’. The ECCPASE will remain set until cleared in firmware or an auto-restart occurs (see Section 10.4.4 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and PSSBD bits of the ECCPAS register. Each pin pair may be placed into one of three states:
Drive logic ‘1’
Drive logic ‘0’
Tri-state (high-impedance) FIGURE 10-10: AUTO-SHUTDOWN BLOCK DIAGRAM PSSAC<1> TRISx P1A P1A_DRV PSSAC<0> PSSBD<1> TRISx P1B PSSBD<0> P1B_DRV 000 001 010 011 100 101 110 111 From Comparator ECCPAS<2:0> R D Q S ECCPASE From Data Bus Write to ECCPASE PRSEN INT

© 2006 Microchip Technology Inc. REGISTER 10-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 = Auto-Shutdown is disabled 001 = Comparator output change 010 = Auto-Shutdown is disabled 011 = Comparator output change(1) 100 = VIL on INT pin 101 = VIL on INT pin or Comparator change 110 = VIL on INT pin(1) 111 = VIL on INT pin or Comparator change bit 3-2 PSSAC<1:0>: Pin P1A Shutdown State Control bits 00 = Drive pin P1A to ‘0’ 01 = Drive pin P1A to ‘1’ 1x = Pin P1A tri-state bit 1-0 PSSBD<1:0>: Pin P1B Shutdown State Control bits 00 = Drive pin P1B to ‘0’ 01 = Drive pin P1B to ‘1’ 1x = Pin P1B tri-state Note 1: If CMSYNC is enabled, the shutdown will be delayed by Timer1. Note 1: The auto-shutdown condition is a level- based signal, not an edge-based signal. As long as the level is present, the auto- shutdown will persist. Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 91 PIC12F609/615/12HV609/615 TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM REGISTER 10-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets APFCON T1GSEL P1BSEL P1ASEL CCP1CON P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CMCON0 CMON COUT CMOE CMPOL CMR CMCH 0000 -0-0 0000 -0-0 CMCON1 T1ACS CMHYS T1GSS ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR2 Timer2 Module Register 0000 0000 0000 0000 TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. Note For PIC12F615/HV615 only.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 93 PIC12F609/615/12HV609/615 11.0 SPECIAL FEATURES OF THE CPU The PIC12F609/615/12HV609/615 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection. These features are:

Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Oscillator selection
Sleep
Code protection
ID Locations
In-Circuit Serial Programming The PIC12F609/615/12HV609/615 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power- up Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through:
External Reset
Watchdog Timer Wake-up
An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 11-1). 11.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 11-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h- 3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information.

© 2006 Microchip Technology Inc. REGISTER 11-1: CONFIG: CONFIGURATION WORD REGISTER BOREN1(1) BOREN0(1) bit 15 bit 8 IOSCFS CP(2) MCLRE(3) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 0x = BOR disabled bit 7 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz 0 = 4 MHz bit 6 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: MCLR Pin Function Select bit(3) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 95 PIC12F609/615/12HV609/615 11.2 Calibration Bits The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2009h). The Calibration Word is not erased when using the specified bulk erase sequence in the “PIC12F6XX/16F6XX Memory Pro- gramming Specification” (DS41204) and thus, does not require reprogramming. 11.3 Reset The PIC12F609/615/12HV609/615 device differenti- ates between various kinds of Reset: Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on:

Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 11-2. Software can use these bits to determine the nature of the Reset. See Table 11-5 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 11-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 “Electrical Specifications” for pulse-width specifications. FIGURE 11-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT S R Q External Reset MCLR/VPP pin VDD OSC1/ WDT Module VDD Rise Detect OST/PWRT On-Chip WDT Time-out Power-on Reset OST 10-bit Ripple Counter PWRT Chip_Reset 11-bit Ripple Counter Reset Enable OST Enable PWRT Sleep Brown-out(1) Reset BOREN CLKIN pin Note Refer to the Configuration Word register (Register 11-1). RC OSC

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 97 PIC12F609/615/12HV609/615 11.3.4 BROWN-OUT RESET (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. One mode has been added to allow control of the BOR enable for lower current during Sleep. By selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. See Register 11-1 for the Configuration Word definition. A brown-out occurs when VDD falls below VBOR for greater than parameter TBOR (see Section 15.0 “Electrical Specifications”). The brown-out condition will reset the device. This will occur regardless of VDD slew rate. A Brown-out Reset may not occur if VDD falls below VBOR for less than parameter TBOR. On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 11-3). If enabled, the Power- up Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. 11.3.5 BOR CALIBRATION The PIC12F609/615/12HV609/615 stores the BOR calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified bulk erase sequence in the “PIC12F6XX/16F6XX Memory Pro- gramming Specification” (DS41204) and thus, does not require reprogramming. FIGURE 11-3: BROWN-OUT SITUATIONS Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register. Note: Address 2008h is beyond the user pro- gram memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Program- ming Specification” (DS41204) for more information. 64 ms(1) VBOR VDD Internal Reset VBOR VDD Internal Reset 64 ms(1) < 64 ms 64 ms(1) VBOR VDD Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

PWRT time-out is invoked after POR has expired.
OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 11-4, Figure 11-5 and Figure 11-6 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 11-5). This is useful for testing purposes or to synchronize more than one PIC12F609/615/ 12HV609/615 device operating in parallel. Table 11-6 shows the Reset conditions for some special registers, while Table 11-5 shows the Reset conditions for all the registers. 11.3.7 POWER CONTROL (PCON) REGISTER The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. Bit 0 is BOR (Brown-out). BOR is unknown on Power- on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subse- quent Reset, if POR is ‘0’, it will indicate that a Power- on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 11.3.4 “Brown-out Reset (BOR)”. TABLE 11-1: TIME-OUT IN VARIOUS SITUATIONS TABLE 11-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Oscillator Configuration Power-up Brown-out Reset Wake-up from Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC RC, EC, INTOSC TPWRT TPWRT POR BOR TO PD Condition x Power-on Reset u Brown-out Reset u u u WDT Reset u u WDT Wake-up u u u u MCLR Reset during normal operation u u MCLR Reset during Sleep Legend: u = unchanged, x = unknown Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets(1) PCON POR BOR ---- --qq ---- --uu STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

© 2006 Microchip Technology Inc. TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609) Register Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out W xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --x0 x000 --u0 u000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch ----- 0--0 ---- 0--0 ---- u--u(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu VRCON 19h 0-00 0000 0-00 0000 u-uu uuuu CMCON0 1Ah 0000 -0-0 0000 -0-0 uuuu -u-u CMCON1 1Ch ---0 0-10 ---0 0-10 ---u u-qu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch ----- 0--0 ---- 0--0 ---- u--u PCON 8Eh ---- --0x ---- --uu(1, 5) ---- --uu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu WPU 95h --11 -111 --11 -111 --uu -uuu IOC 96h --00 0000 --00 0000 --uu uuuu ANSEL 9Fh ---- 1-11 ---- 1-11 ---- q-qq Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 11-6 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 101 PIC12F609/615/12HV609/615 TABLE 11-5: INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/HV615) Register Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out W xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --x0 x000 --u0 u000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch -000 0-00 -000 0-00 -uuu u-uu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2(1) 11h 0000 0000 0000 0000 uuuu uuuu T2CON(1) 12h -000 0000 -000 0000 -uuu uuuu CCPR1L(1) 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H(1) 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON(1) 15h 0-00 0000 0-00 0000 u-uu uuuu PWM1CON(1) 16h 0000 0000 0000 0000 uuuu uuuu ECCPAS(1) 17h 0000 0000 0000 0000 uuuu uuuu VRCON 19h 0-00 0000 0-00 0000 u-uu uuuu CMCON0 1Ah 0000 -0-0 0000 -0-0 uuuu -u-u CMCON1 1Ch ---0 0-10 ---0 0-10 ---u u-qu ADRESH(1) 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0(1) 1Fh 00-0 0000 00-0 0000 uu-u uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch -00- 0-00 -00- 0-00 -uu- u-uu PCON 8Eh ---- --0x ---- --uu(1, 5) ---- --uu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu PR2 92h 1111 1111 1111 1111 1111 1111 APFCON 93h ---0 --00 ---0 --00 ---u --uu WPU 95h --11 -111 --11 -111 --uu -uuu IOC 96h --00 0000 --00 0000 --uu uuuu ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ANSEL 9Fh -000 1111 -000 1111 -uuu qqqq Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 11-6 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

© 2006 Microchip Technology Inc. TABLE 11-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

© 2006 Microchip Technology Inc. 11.4.2 TIMER0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. 11.4.3 GPIO INTERRUPT-ON-CHANGE An input change on GPIO sets the GPIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the GPIE bit of the INTCON register. Plus, individual pins can be configured through the IOC register. FIGURE 11-7: INTERRUPT LOGIC Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. TMR1IF TMR1IE CMIF CMIE T0IF T0IE INTF INTE GPIF GPIE GIE PEIE Wake-up (If in Sleep mode)(1) Interrupt to CPU ADIF ADIE IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR2IF TMR2IE CCP1IF CCP1IE Note Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 11.7.1 “Wake-up from Sleep”. (615 only) (615 only) (615 only)

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 105 PIC12F609/615/12HV609/615 FIGURE 11-8: INT PIN INTERRUPT TIMING TABLE 11-7: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 PIR1 ADIF(1) CCP1IF(1) CMIF TMR2IF(1) TMR1IF PIE1 ADIE(1) CCP1IE(1) CMIE TMR2IE(1) TMR1IE Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC12F615/HV615 only. OSC1 CLKOUT INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Interrupt Latency PC PC + 1 PC + 1 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (PC) Inst (PC + 1) Inst (PC – 1) Inst (0004h) Dummy Cycle Inst (PC) Note 1: INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”. INTF is enabled to be set any time during the Q4-Q1 cycles. (1) (2) (3) (4) (5) (1)

© 2006 Microchip Technology Inc. 11.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-2). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example 11-1 can be used to:

Store the W register
Store the STATUS register
Execute the ISR code
Restore the Status (and Bank Select Bit register)
Restore the W register EXAMPLE 11-1: SAVING STATUS AND W REGISTERS IN RAM 11.6 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin and INTOSC. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction). During normal oper- ation, a WDT time out generates a device Reset. If the device is in Sleep mode, a WDT time out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by program- ming the Configuration bit, WDTE, as clear (Section 11.1 “Configuration Bits”). 11.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out. Note: The PIC12F609/615/12HV609/615 does not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR. MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register :(ISR) ;Insert user code here SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 107 PIC12F609/615/12HV609/615 11.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst- case conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time out occurs. FIGURE 11-2: WATCHDOG TIMER BLOCK DIAGRAM TABLE 11-9: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER TABLE 11-8: WDT STATUS Conditions WDT WDTE = 0 Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 CONFIG IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 Legend: Shaded cells are not used by the Watchdog Timer. Note See Register 11-1 for operation of all Configuration Word register bits. T0CKI T0SE pin CLKOUT TMR0 Watchdog Timer WDT Time-Out PS<2:0> WDTE Data Bus Set Flag bit T0IF on Overflow T0CS Note T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. SYNC 2 Cycles 8-bit Prescaler (= FOSC/4) PSA PSA PSA

WDT will be cleared but keeps running.
PD bit in the STATUS register is cleared.
TO bit is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are high- impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull- ups on GPIO should be considered. The MCLR pin must be at a logic high level. 11.7.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from GP2/INT pin, GPIO change or a peripheral interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: Timer1 interrupt. Timer1 must be operating as an asynchronous counter. ECCP Capture mode interrupt. A/D conversion (when A/D clock source is RC). Comparator output changes state. Interrupt-on-change. External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 11.7.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:
If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared.
If the interrupt occurs during or after the execution of a SLEEP instruction, the device will Immediately wake-up from Sleep. The SLEEP instruction is executed. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 11-9 for more details. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. Note: If the global interrupts are disabled (GIE is cleared) and any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wake-up from Sleep.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 109 PIC12F609/615/12HV609/615 FIGURE 11-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT 11.8 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. 11.9 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC – 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(3) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Dummy Cycle PC + 2 0004h 0005h Dummy Cycle TOST(2) PC + 2 Note XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes. GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. Note: The entire Flash program memory will be erased when the code protection is turned off. See the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information.

© 2006 Microchip Technology Inc. 11.10 In-Circuit Serial Programming™ The PIC12F609/615/12HV609/615 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for:

clock
data
power
ground
programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the micro- controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the “PIC12F6XX/ 16F6XX Memory Programming Specification” (DS41204) for more information. GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 11-10. FIGURE 11-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION 11.11 In-Circuit Debugger Since in-circuit debugging requires access to three pins, MPLAB® ICD 2 development with an 14-pin device is not practical. A special 28-pin PIC12F609/615/ 12HV609/615 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F609/615/12HV609/615 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F609/615/12HV609/

615 ICD device is held low, the In-Circuit Debugger

functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 11-10 shows which features are consumed by the background debugger. TABLE 11-10: DEBUGGER RESOURCES For more information, see “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). Note: To erase the device VDD must be above the Bulk Erase VDD minimum given in the “PIC12F609/615/12HV609/615 Memory Programming Specification” (DS41284) External Connector Signals To Normal Connections To Normal Connections PIC12F615/12HV615 VDD VSS MCLR/VPP/GP3 GP1 GP0 +5V VPP CLK Data I/O * Isolation devices (as required) PIC12F609/12HV609 Resource ICDCLK, ICDDATA Stack 1 level Program Memory Address 0h must be NOP 700h-7FFh

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 111 PIC12F609/615/12HV609/615 12.0 VOLTAGE REGULATOR The PIC12HV609/HV615 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). 12.1 Regulator Operation A shunt regulator generates a specific supply voltage by creating a voltage drop across a pass resistor RSER. The voltage at the VDD pin of the microcontroller is monitored and compared to an internal voltage refer- ence. The current through the resistor is then adjusted, based on the result of the comparison, to produce a voltage drop equal to the difference between the supply voltage VUNREG and the VDD of the microcontroller. See Figure 12-1 for voltage regulator schematic. FIGURE 12-1: VOLTAGE REGULATOR An external current limiting resistor, RSER, located between the unregulated supply, VUNREG, and the VDD pin, drops the difference in voltage between VUNREG and VDD. RSER must be between RMAX and RMIN as defined by Equation 12-1. EQUATION 12-1: RSER LIMITING RESISTOR 12.2 Regulator Considerations The supply voltage VUNREG and load current are not constant. Therefore, the current range of the regulator is limited. Selecting a value for RSER must take these three factors into consideration. Since the regulator uses the band gap voltage as the regulated voltage reference, this voltage reference is permanently enabled in the PIC12HV609/HV615 device. The shunt regulator will still consume current when below operating voltage range for the shunt regulator. 12.3 Design Considerations For more information on using the shunt regulator and managing current load, see Application Note AN1035, “Designing with HV Microcontrollers” (DS01035). Feedback VDD VSS CBYPASS RSER VUNREG ISUPPLY ISHUNT ILOAD Device RMAX = (VUMIN - 5V) 1.05 • (4 MA + ILOAD) RMIN = (VUMAX - 5V) 0.95 • (50 MA) Where: RMAX = maximum value of RSER (ohms) RMIN = minimum value of RSER (ohms) VUMIN = minimum value of VUNREG VUMAX= maximum value of VUNREG VDD = regulated voltage (5V nominal) ILOAD = maximum expected load current in mA including I/O pin currents and external circuits connected to VDD. 1.05 = compensation for +5% tolerance of RSER 0.95 = compensation for -5% tolerance of RSER

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 113 PIC12F609/615/12HV609/615 13.0 INSTRUCTION SET SUMMARY The PIC12F609/615/12HV609/615 instruction set is highly orthogonal and is comprised of three basic cate- gories:

Byte-oriented operations
Bit-oriented operations
Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. Table 13-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 μs. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 13.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, and the result is stored according to either the instruc- tion or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended conse- quence of clearing the condition that set the GPIF flag. TABLE 13-1: OPCODE FIELD DESCRIPTIONS FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Field

f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit Byte-oriented file register operations 13 8 7 6 0 d = 0 for destination W OPCODE d f (FILE #) d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value General CALL and GOTO instructions only

© 2006 Microchip Technology Inc. TABLE 13-2: PIC12F609/615/12HV609/615 INSTRUCTION SET Mnemonic, Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1(2) 1(2) 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C, DC, Z Z Z Z Z Z Z Z Z C C C, DC, Z Z 1, 2 1, 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C, DC, Z Z TO, PD Z TO, PD C, DC, Z Z Note When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 115 PIC12F609/615/12HV609/615 13.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. ADDWF Add W and f Syntax: [ label ] ADDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) → (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. BCF Bit Clear f Syntax: [ label ] BCF f,b Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.

© 2006 Microchip Technology Inc. BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 127 0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Call Subroutine Syntax: [ label ] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1 → Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1 → Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. COMF Complement f Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination) Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 117 PIC12F609/615/12HV609/615 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a two-cycle instruction. GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0> Status Affected: None Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f Syntax: [ label ] INCF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination) Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a two-cycle instruction. IORLW Inclusive OR literal with W Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Status Affected: Z Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .OR. (f) → (destination) Status Affected: Z Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.

© 2006 Microchip Technology Inc. MOVF Move f Syntax: [ label ] MOVF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself. d = 1 is useful to test a file register since Status flag Z is affected. Words: Cycles: Example: MOVF FSR, After Instruction W value in FSR register Z MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Description: The eight-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Words: Cycles: Example: MOVLW 0x5A After Instruction W 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None Description: Move data from W register to register ‘f’. Words: Cycles: Example: MOVW F OPTION Before Instruction OPTION = 0xFF W 0x4F After Instruction OPTION = 0x4F W 0x4F NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Description: No operation. Words: Cycles: Example: NOP

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 119 PIC12F609/615/12HV609/615 RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None Operation: TOS → PC, 1 → GIE Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: Cycles: Example: RETFIE After Interrupt PC = TOS GIE = RETLW Return with literal in W Syntax: [ label ] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W); TOS → PC Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: Cycles: Example: TABLE DONE CALL TABLE;W contains ;table offset ;value GOTO DONE ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 RETLW kn ;End of table Before Instruction W 0x07 After Instruction W value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS → PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction.

© 2006 Microchip Technology Inc. RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: Cycles: Example: RLF REG1,0 Before Instruction REG1 1110 0110 C After Instruction REG1 1110 0110 W 1100 1100 C RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Register f C Register f C SLEEP Enter Sleep mode Syntax: [ label ] SLEEP Operands: None Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SUBLW Subtract W from literal Syntax: [ label ] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition C = 0 W > k C = 1 W ≤ k DC = 0 DC = 1

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 121 PIC12F609/615/12HV609/615 SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. C = 0 W > f C = 1 W ≤ f DC = 0 DC = 1 XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 123 PIC12F609/615/12HV609/615 14.0 DEVELOPMENT SUPPORT The PIC® microcontrollers are supported with a full range of hardware and software development tools:

Integrated Development Environment - MPLAB® IDE Software
Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library
Simulators - MPLAB SIM Software Simulator
Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator
In-Circuit Debugger - MPLAB ICD 2
Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer
Low-Cost Demonstration and Development Boards and Evaluation Kits 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows® operating system-based application that contains:
A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately)
A full-featured editor with color-coded context
A multiple project manager
Customizable data windows with direct edit of

High-level source code debugging
Visual device initializer for easy register initialization
Mouse over variable inspection
Drag and drop variables from source to watch windows
Extensive on-line help
Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to:
Edit your source files (either assembly or C)
One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information)
Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.

© 2006 Microchip Technology Inc. 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include:

Integration into MPLAB IDE projects
User-defined macros to streamline assembly code
Conditional assembly for multi-purpose source files
Directives that allow complete control over the assembly process 14.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 family of microcontrollers and the dsPIC30, dsPIC33 and PIC24 family of digital signal controllers. These compilers provide powerful integra- tion capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include:
Efficient linking of single libraries instead of many smaller files
Enhanced code maintainability by grouping related modules together
Flexible creation of libraries with easy module listing, replacement, deletion and extraction 14.5 MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include:
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility 14.6 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 125 PIC12F609/615/12HV609/615 14.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC micro- controllers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Inte- grated Development Environment, which allows edit- ing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 14.8 MPLAB ICE 4000 High-Performance In-Circuit Emulator The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PIC MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed perfor- mance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost- effective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.

14.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.

© 2006 Microchip Technology Inc. 14.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.

14.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost programmer with an easy-to-use interface for pro- gramming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping develop- ment board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® micro- controllers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers.

14.13 Demonstration, Development and

A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully func- tional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demon- stration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart® battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 127 PIC12F609/615/12HV609/615 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 129 PIC12F609/615/12HV609/615 15.1 DC Characteristics: PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions VDD Supply Voltage 2.0 5.5 V FOSC < = 8 MHz: INTOSC, EC D001 PIC12F609/615 2.0 5.5 V FOSC < = 4 MHz D001 PIC12HV609/615 2.0 —(2) V FOSC < = 4 MHz D001B PIC12F609/F615 2.0 5.5 V FOSC < = 8 MHz: INTOSC, EC D001B PIC12HV609/615 2.0 —(2) V FOSC < = 8 MHz: INTOSC, EC D001C PIC12F609/615 3.0 5.5 V FOSC < = 10 MHz D001C PIC12HV609/615 3.0 —(2) V FOSC < = 10 MHz D001D PIC12F609/615 4.5 5.5 V FOSC < = 20 MHz D001D PIC12HV609/615 4.5 —(2) V FOSC < = 20 MHz D002* VDR RAM Data Retention Voltage(1) 1.5 V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal VSS V See Section 11.3.1 “Power-on Reset (POR)” for details. D004* SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 V/ms See Section 11.3.1 “Power-on Reset (POR)” for details. These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. User defined. Voltage across the shunt should not exceet 5V.

© 2006 Microchip Technology Inc. 15.2 DC Characteristics: PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D010 Supply Current (IDD)(1, 2) μA 2.0 FOSC = 32 kHz LP Oscillator mode μA 3.0 μA 5.0 D011* 140 240 μA 2.0 FOSC = 1 MHz XT Oscillator mode 220 380 μA 3.0 380 550 μA 5.0 D012 260 360 μA 2.0 FOSC = 4 MHz XT Oscillator mode 420 650 μA 3.0 0.8 1.1 mA 5.0 D013* 130 220 μA 2.0 FOSC = 1 MHz EC Oscillator mode 215 360 μA 3.0 360 520 μA 5.0 D014 220 340 μA 2.0 FOSC = 4 MHz EC Oscillator mode 375 550 μA 3.0 0.65 1.0 mA 5.0 D016* 340 450 μA 2.0 FOSC = 4 MHz INTOSC mode 500 700 μA 3.0 0.8 1.2 mA 5.0 D017 410 650 μA 2.0 FOSC = 8 MHz INTOSC mode 700 950 μA 3.0 1.30 1.65 mA 5.0 D018 230 400 μA 2.0 FOSC = 4 MHz EXTRC mode(3) 400 680 μA 3.0 0.63 1.1 mA 5.0 D019 2.6 3.25 mA 4.5 FOSC = 20 MHz HS Oscillator mode 2.8 3.35 mA 5.0 These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 131 PIC12F609/615/12HV609/615 15.3 DC Characteristics: PIC12F615/HV615 - I (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020 Power-down Base Current(IPD)(2) 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and T1OSC disabled 0.15 1.5 μA 3.0 PIC12F609/615 0.35 1.8 μA 5.0 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C PIC12HV609/HV615 350 μA 2.0 350 μA 3.0 200 nA 5.0 D021 1.0 2.2 μA 2.0 WDT Current(1) 2.0 4.0 μA 3.0 3.0 7.0 μA 5.0 D022 μA 3.0 BOR Current(1) 122 μA 5.0 D023 μA 2.0 Comparator Current(1), both comparators enabled μA 3.0 120 160 μA 5.0 D024 μA 2.0 CVREF Current(1) (high range) μA 3.0 μA 5.0 D025* μA 2.0 CVREF Current(1) (low range) μA 3.0 124 μA 5.0 D026 4.5 7.0 μA 2.0 T1OSC Current(1), 32.768 kHz 5.0 8.0 μA 3.0 6.0 μA 5.0 D027 0.30 1.6 μA 3.0 A/D Current(1), no conversion in progress 0.36 1.9 μA 5.0 These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

© 2006 Microchip Technology Inc. 15.4 DC Characteristics: PIC12F609/615/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020E Power-down Base Current (IPD)(2) 0.05 μA 2.0 WDT, BOR, Comparators, VREF and T1OSC disabled 0.15 μA 3.0 0.35 μA 5.0 PIC12HV609/HV615 350 μA 2.0 350 μA 3.0 200 nA 5.0 D021E 17.5 μA 2.0 WDT Current(1) μA 3.0 μA 5.0 D022E μA 3.0 BOR Current(1) 127 μA 5.0 D023E μA 2.0 Comparator Current(1), both comparators enabled μA 3.0 120 160 μA 5.0 D024E μA 2.0 CVREF Current(1) (high range) μA 3.0 120 μA 5.0 D025E* μA 2.0 CVREF Current(1) (low range) 117 μA 3.0 156 μA 5.0 D026E 4.5 μA 2.0 T1OSC Current(1), 32.768 kHz μA 3.0 μA 5.0 D027E 0.30 μA 3.0 A/D Current(1), no conversion in progress 0.36 μA 5.0 These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 133 PIC12F609/615/12HV609/615 15.5 DC Characteristics: PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions VIL Input Low Voltage I/O port: D030 with TTL buffer Vss 0.8 V 4.5V ≤ VDD ≤ 5.5V D030A Vss

0.15 VDD

V 2.0V ≤ VDD ≤ 4.5V D031 with Schmitt Trigger buffer Vss

0.2 VDD

V 2.0V ≤ VDD ≤ 5.5V D032 MCLR, OSC1 (RC mode)(1) VSS V D033 OSC1 (XT and LP modes) VSS 0.3 V D033A OSC1 (HS mode) VSS

0.3 VDD

V VIH Input High Voltage I/O ports: D040 with TTL buffer 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25 VDD + 0.8 VDD V 2.0V ≤ VDD ≤ 4.5V D041 with Schmitt Trigger buffer

0.8 VDD

V 2.0V ≤ VDD ≤ 5.5V D042 MCLR V D043 OSC1 (XT and LP modes) 1.6 VDD V D043A OSC1 (HS mode)

0.7 VDD

V D043B OSC1 (RC mode)

0.9 VDD

V (Note 1) IIL Input Leakage Current(2) D060 I/O ports ± 0.1 ± 1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR(3) ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration D070* IPUR GPIO Weak Pull-up Current 250 400 μA VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) VOH Output High Voltage(4) D090 I/O ports VDD – 0.7 V IOH = -3.0 mA, VDD = 4.5V (Ind.) These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.

© 2006 Microchip Technology Inc. D100 Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins pF Program Flash Memory D130 EP Cell Endurance 10K 100K E/W -40°C ≤ TA ≤ +85°C D130A ED Cell Endurance 10K E/W D131 VPR VDD for Read VMIN 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 5.5 V D133 TPEW Erase/Write cycle time 2.5 ms D134 TRETD Characteristic Retention Year Provided no other specifications are violated 15.5 DC Characteristics: PIC12F609/615/12HV609/615-I (Industrial) PIC12F609/615/12HV609/615-E (Extended) (Continued) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 135 PIC12F609/615/12HV609/615 15.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Sym Characteristic Typ Units Conditions TH01 θJA Thermal Resistance Junction to Ambient 84.6* C/W 8-pin PDIP package 163* C/W 8-pin SOIC package 124* C/W 8-pin TSSOP package 44* C/W 8-pin DFN 4x4mm package TH02 θJC Thermal Resistance Junction to Case 41.2* C/W 8-pin PDIP package 38.8* C/W 8-pin SOIC package 36.6* C/W 8-pin TSSOP package 3.0* C/W 8-pin DFN 3x3mm package TH03 TDIE Die Temperature 150* C TH04 PD Power Dissipation W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation W PINTERNAL = IDD x VDD (NOTE 1) TH06 PI/O I/O Power Dissipation W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH)) TH07 PDER Derated Power W PDER = PDMAX (TDIE - TA)/θJA (NOTE 2) These parameters are characterized but not tested. Note 1: IDD is current to run the chip alone without driving any load on the output pins.

© 2006 Microchip Technology Inc. 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: FIGURE 15-3: LOAD CONDITIONS 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in T0CKI io I/O Port T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance VSS CL Legend: CL = 50 pF for all pins 15 pF for OSC2 output Load Condition Pin

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 137 PIC12F609/615/12HV609/615 15.8 AC Characteristics: PIC12F609/615/12HV609/615 (Industrial, Extended) FIGURE 15-4: CLOCK TIMING TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Sym Characteristic Min Typ† Max Units Conditions OS01 FOSC External CLKIN Frequency(1) DC kHz LP Oscillator mode DC MHz XT Oscillator mode DC MHz HS Oscillator mode DC MHz EC Oscillator mode Oscillator Frequency(1) 32.768 kHz LP Oscillator mode 0.1 MHz XT Oscillator mode MHz HS Oscillator mode DC MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) μs LP Oscillator mode 250 ns XT Oscillator mode ns HS Oscillator mode ns EC Oscillator mode Oscillator Period(1) 30.5 μs LP Oscillator mode 250 10,000 ns XT Oscillator mode 1,000 ns HS Oscillator mode 250 ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TOSH, TOSL External CLKIN High, External CLKIN Low μs LP oscillator 100 ns XT oscillator ns HS oscillator OS05* TOSR, TOSF External CLKIN Rise, External CLKIN Fall ns LP oscillator ns XT oscillator ns HS oscillator These parameters are characterized but not tested. Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. OSC1/CLKIN OSC2/CLKOUT OS02 OS03 OS04 OS04 OSC2/CLKOUT (LP,XT,HS Modes) (CLKOUT Mode)

© 2006 Microchip Technology Inc. TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature Param No. Sym Characteristic Freq. Tolerance Min Typ† Max Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) TOSC Slowest clock OS08 INTOSC Internal Calibrated INTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C ±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V, 0°C ≤ TA ≤ +85°C ±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +85°C (Ind.), -40°C ≤ TA ≤ +125°C (Ext.) OS10* TIOSC ST INTOSC Oscillator Wake- up from Sleep Start-up Time 5.5 μs VDD = 2.0V, -40°C to +85°C 3.5 μs VDD = 3.0V, -40°C to +85°C μs VDD = 5.0V, -40°C to +85°C These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. By design.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 139 PIC12F609/615/12HV609/615 FIGURE 15-5: CLKOUT AND I/O TIMING FOSC CLKOUT I/O pin (Input) I/O pin (Output) OS11 OS19 OS13 OS15 OS18, OS19 OS20 OS21 OS17 OS16 OS14 OS12 OS18 Old Value New Value Write Fetch Read Execute Cycle TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions OS11 TOSH2CKL FOSC↑ to CLKOUT↓ (1) ns VDD = 5.0V OS12 TOSH2CKH FOSC↑ to CLKOUT↑ (1) ns VDD = 5.0V OS13 TCKL2IOV CLKOUT↓ to Port out valid(1) ns OS14 TIOV2CKH Port input valid before CLKOUT↑(1) TOSC + 200 ns ns OS15 TOSH2IOV FOSC↑ (Q1 cycle) to Port out valid 70* ns VDD = 5.0V OS16 TOSH2IOI FOSC↑ (Q2 cycle) to Port input invalid (I/O in hold time) ns VDD = 5.0V OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle) (I/O in setup time) ns OS18 TIOR Port output rise time(2) ns VDD = 2.0V VDD = 5.0V OS19 TIOF Port output fall time(2) ns VDD = 2.0V VDD = 5.0V OS20* TINP INT pin input high or low time ns OS21* TRAP GPIO interrupt-on-change new input level time TCY ns These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 141 PIC12F609/615/12HV609/615 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature Param No. Sym Characteristic Min Typ† Max Units Conditions TMCL MCLR Pulse Width (low) μs μs VDD = 5V, -40°C to +85°C VDD = 5V, -60°C to +125°C TWDT Watchdog Timer Time-out Period (No Prescaler) ms ms VDD = 5V, -40°C to +85°C VDD = 5V, -40°C to +125°C TOST Oscillation Start-up Timer Period(1, 2) 1024 TOSC (NOTE 3) 33* TPWRT Power-up Timer Period 140 ms 34* TIOZ I/O High-impedance from MCLR Low or Watchdog Timer Reset 2.0 μs VBOR Brown-out Reset Voltage 2.0 2.2 V (NOTE 4) 36* VHYST Brown-out Reset Hysteresis mV 37* TBOR Brown-out Reset Minimum Detection Period 100 μs VDD ≤ VBOR These parameters are characterized but not tested. Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.

© 2006 Microchip Technology Inc. FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature Param No. Sym Characteristic Min Typ† Max Units Conditions 40* TT0H T0CKI High Pulse Width No Prescaler

0.5 TCY + 20

41* TT0L T0CKI Low Pulse Width No Prescaler 42* TT0P T0CKI Period Greater of: 20 or TCY + 40 N ns N = prescale value (2, 4, ..., 256) 45* TT1H T1CKI High Time Synchronous, No Prescaler Synchronous, with Prescaler ns Asynchronous ns 46* TT1L T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler ns Asynchronous ns 47* TT1P T1CKI Input Period Synchronous Greater of: 30 or TCY + 40 N ns N = prescale value (1, 2, 4, 8) Asynchronous ns FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 32.768 kHz 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment

2 TOSC

7 TOSC

These parameters are characterized but not tested. Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. T0CKI T1CKI TMR0 or TMR1

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 143 PIC12F609/615/12HV609/615 FIGURE 15-9: PIC12F615/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP) TABLE 15-6: PIC12F615/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature Param No. Sym Characteristic Min Typ† Max Units Conditions CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 ns With Prescaler ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 ns With Prescaler ns CC03* TccP CCP1 Input Period 3TCY + 40 N ns N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Refer to Figure 15-3 for load conditions. (Capture mode) CC01 CC02 CC03 CCP1

© 2006 Microchip Technology Inc. TABLE 15-7: COMPARATOR SPECIFICATIONS TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS TABLE 15-9: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature Param No. Sym Characteristics Min Typ† Max Units Comments CM01 VOS Input Offset Voltage ± 5.0 ± 10 mV (VDD - 1.5)/2 CM02 VCM Input Common Mode Voltage VDD – 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 dB CM04* TRT Response Time Falling 150 600 ns (NOTE 1) Rising 200 1000 ns CM05* TMC2COV Comparator Mode Change to Output Valid μs CM06* VHYS Input Hysteresis Voltage mV These parameters are characterized but not tested. Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV. Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Sym Characteristics Min Typ† Max Units Comments CV01* CLSB Step Size(2) VDD/24 VDD/32 V V Low Range (VRR = 1) High Range (VRR = 0) CV02* CACC Absolute Accuracy ± 1/2 ± 1/2 LSb LSb Low Range (VRR = 1) High Range (VRR = 0) CV03* CR Unit Resistor Value (R) Ω CV04* CST Settling Time(1) μs These parameters are characterized but not tested. Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. See Section 8.10 “Comparator Voltage Reference” for more information. VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Symbol Characteristics Min Typ Max Units Comments VR01 VP6OUT VP6 voltage output 0.55 0.6 0.65 V VR02 V1P2OUT V1P2 voltage output 1.200 V VR03 TSTABLE Settling Time μs These parameters are characterized but not tested.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 145 PIC12F609/615/12HV609/615 TABLE 15-10: SHUNT REGULATOR SPECIFICATIONS (PIC12HV609/615 only) TABLE 15-11: PIC12F615/HV615 A/D CONVERTER (ADC) CHARACTERISTICS: SHUNT REGULATOR CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Symbol Characteristics Min Typ Max Units Comments SR01 VSHUNT Shunt Voltage 4.75 5.25 V SR02 ISHUNT Shunt Current mA SR03* TSETTLE Settling Time 150 ns To 1% of final value SR04 CLOAD Load Capacitance 0.01 μF Bypass capacitor on VDD pin SR05 ΔISNT Regulator operating current 180 μA Includes band gap reference current Legend: TBD = To Be Determined These parameters are characterized but not tested. Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Sym Characteristic Min Typ† Max Units Conditions AD01 NR Resolution 10 bits bit AD02 EIL Integral Error LSb VREF = 5.12V AD03 EDL Differential Error LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error 1.5 LSb VREF = 5.12V AD07 EGN Gain Error LSb VREF = 5.12V AD06 AD06A VREF Reference Voltage(3) 2.2 2.5 VDD V Absolute minimum to ensure 1 LSb accuracy AD07 VAIN Full-Scale Range VSS VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source kΩ AD09* IREF VREF Input Current(3) 1000 μA During VAIN acquisition. Based on differential of VHOLD to VAIN. μA During A/D conversion cycle. These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module.

© 2006 Microchip Technology Inc. TABLE 15-12: PIC12F615/HV615 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature Param No. Sym Characteristic Min Typ† Max Units Conditions AD130* TAD A/D Clock Period 1.6 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 9.0 μs TOSC-based, VREF full range(3) A/D Internal RC Oscillator Period 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 μs At VDD = 5.0V AD131 TCNV Conversion Time (not including Acquisition Time)(1) TAD Set GO/DONE bit to new data in A/D Result register AD132* TACQ Acquisition Time 11.5 μs AD133* TAMP Amplifier Settling Time μs AD134 TGO Q4 to A/D Clock Start TOSC/2 TOSC/2 + TCY If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. These parameters are characterized but not tested. Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. See Section 9.3 “A/D Acquisition Requirements” for minimum conditions. Full range for PIC12HV609/HV615 powered by the shunt regulator is the 5V regulated voltage.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 147 PIC12F609/615/12HV609/615 FIGURE 15-10: PIC12F615/HV615 A/D CONVERSION TIMING (NORMAL MODE) FIGURE 15-11: PIC12F615/HV615 A/D CONVERSION TIMING (SLEEP MODE) AD131 AD130 BSF ADCON0, GO A/D CLK A/D Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.

1 TCY

(TOSC/2(1)) BSF ADCON0, GO A/D CLK A/D Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. AD134 (TOSC/2 + TCY(1))

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 151 PIC12F609/615/12HV609/615 17.0 PACKAGING INFORMATION 17.1 Package Marking Information Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e 8-Lead TSSOP XXXX YYWW NNN Example /ST 0610 017 XXXXXNNN 8-Lead PDIP XXXXXXXX YYWW 017 Example XXFXXX/P 0610 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN Example PICXXCXX /SN0610 017 XXXXXX 8-Lead DFN (4x4 mm) YYWW NNN Example XXXXXX XXXXXX 0610 017 XXXX e e e e

© 2006 Microchip Technology Inc. 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging B A L p α E eB β c n D Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 § Significant Characteristic

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 153 PIC12F609/615/12HV609/615 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Foot Angle φ β Mold Draft Angle Bottom α Mold Draft Angle Top 0.51 0.42 0.33 .020 .017 .013 B Lead Width 0.25 0.23 0.20 .010 .009 .008 c Lead Thickness 0.76 0.62 0.48 .030 .025 .019 L Foot Length 0.51 0.38 0.25 .020 .015 .010 h Chamfer Distance 5.00 4.90 4.80 .197 .193 .189 D Overall Length 3.99 3.91 3.71 .157 .154 .146 Molded Package Width 6.20 6.02 5.79 .244 .237 .228 E Overall Width 0.25 0.18 0.10 .010 .007 .004 Standoff 1.55 1.42 1.32 .061 .056 .052 Molded Package Thickness 1.75 1.55 1.35 .069 .061 .053 A Overall Height 1.27 .050 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units D n p B E h L β c 45° φ α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 § Significant Characteristic

© 2006 Microchip Technology Inc. 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E D e n b c L A ϕ β α MILLIMETERS* MIN NOM MAX 1.20 1.05 0.15 4.50 3.10 0.75 0.20 0.30 1.00 4.40 3.00 0.60 0.80 0.05 4.30 2.90 0.45 0.09 0.19 INCHES MIN NOM MAX .039 .173 .118 .024 .047 .041 .006 .177 .122 .030 .008 .012 .031 .002 .169 .114 .018 .004 .007 .026 BSC

0.65 BSC

.252 BSC

6.40 BSC

12° REF 12° REF 12° REF 12° REF Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Notes: 1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M Drawing No. C04-086 Revised 7-25-06 n e A E D L ϕ c b α β

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 155 PIC12F609/615/12HV609/615 8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x09 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Exposed Pad Width Overall Width Exposed Pad Length Contact Width Contact Length § Contact-to-Exposed Pad § Units Dimension Limits N e A D E b L K 0.80 0.00 0.00 0.00 0.25 0.30 0.20

0.80 BSC

0.90 0.02

0.20 REF

4.00 BSC

2.20 3.00 0.30 0.55 1.00 0.05 2.80 3.60 0.35 0.65 MIN NOM MAX MILLIMETERS Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. § Significant Characteristic 4. Package is saw singulated 5. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–131, Sept. 8, 2006 A NOTE 2 TOP VIEW BOTTOM VIEW NOTE 1 NOTE 1 EXPOSED PAD E D N K b e N L

REVISION HISTORY

This is a new data sheet. APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices. B.1 PIC12F675 to PIC12F609/615/ 12HV609/615 TABLE B-1: FEATURE COMPARISON Feature PIC12F675 PIC12F609/ 615/ 12HV609/615 Max Operating Speed Memory (Words) 1024 1024 SRAM (bytes) A/D Resolution 10-bit 10-bit (615 only) Timers (8/16-bit) 2/1 (615) 1/1 (609) Oscillator Modes Brown-out Reset Y Y Internal Pull-ups RA0/1/2/4/5 GP0/1/2/4/5, MCLR Interrupt-on-change Comparator 1 w/hysteresis ECCP N Y (615) INTOSC Frequencies N Y (PIC12HV609/ 615) Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 159 PIC12F609/615/12HV609/615 INDEX A A/D AC Characteristics ADC Analog-to-Digital Converter. See ADC Assembler B Block Diagrams C C Compilers Capture Module. See Enhanced Capture/Compare/PWM (ECCP) Capture/Compare/PWM (CCP) Example PWM Frequencies and Example PWM Frequencies and Clock Sources Code Examples

© 2006 Microchip Technology Inc. Comparator Voltage Reference (CVREF) Comparators Compare Module. See Enhanced Capture/Compare/PWM (ECCP) D DC Characteristics E ECCP. See Enhanced Capture/Compare/PWM Effects of Reset Enhanced Capture/Compare/PWM (ECCP) Output Relationships (Active-High and Enhanced Capture/Compare/PWM F Fuses. See Configuration Bits G I

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 161 PIC12F609/615/12HV609/615 Internal Oscillator Block INTOSC L M MPLAB ICE 2000 High-Performance Universal MPLAB ICE 4000 High-Performance Universal MPLAB Integrated Development Environment Software .. 123 O Operational Amplifier (OPA) Module Oscillator Oscillator Start-up Timer (OST) P P1A/P1B/P1C/P1D.See Enhanced Pin Diagram Pinout Descriptions Prescaler R Registers ECCPAS (Enhanced CCP Auto-shutdown Control) ... 88 Special Register Summary (PIC12F609/HV609) . 11, 13 Special Register Summary (PIC12F615/HV615) . 12, 14

© 2006 Microchip Technology Inc. S Sleep T ECCP Special Event Trigger Timer1 Gate Timers Timer1 Timer2 Timing Diagrams PWM Auto-shutdown Time-out Sequence V Voltage Reference (VR) Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References VREF. SEE ADC Reference Voltage W

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 163 PIC12F609/615/12HV609/615 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com

© 2006 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS41302A PIC12F609/615/12HV609/615 What are the best features of this document? How does this document meet your hardware and software development needs? Do you find the organization of this document easy to follow? If not, why? What additions to the document do you think would enhance the structure and subject? What deletions from the document could be made without affecting the overall usefulness? Is there any incorrect or misleading information (what and where)? How would you improve this document?

© 2006 Microchip Technology Inc. Preliminary DS41302A-page 165 PIC12F609/615/12HV609/615 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Pattern Package Temperature Range Device Device: PIC12F609, PIC12F609T(1), PIC12HV609, PIC12HV609T(1), PIC12F615, PIC12F615T(1)), PIC12HV615, PIC12HV615T(1) VDD range 2.0V to 5.5V (F devices only) Temperature Range: I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package: P Plastic DIP MD 8-lead Plastic Dual Flat, No Lead (4x4x0.9mm) SN 8-lead Small Outline (150 mil) ST Thin Shrink Small Outline (4.4 mm) Pattern: QTP, SQTP or ROM Code; Special Requirements (blank otherwise) Examples: PIC12F615-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC12F615-I/SN = Industrial Temp., SOIC package, 20 MHz Note 1: T in tape and reel TSSOP and SOIC packages only.

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Product Information

12F615 specifications and overview.

Summary

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers 2006

Description

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers 2006

Source title 12F615 Datasheet(PDF) - Microchip Technology

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