HFA3046_05 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 13

Technical content

Features

  • Complete Isolation Between Transistors
  • Pin Compatible with Indu stry Standard 3XXX Series Arrays
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • VHF/UHF Amplifiers
  • V H F / U H F M i x e r s
  • IF Converters
  • Synchronous Detectors

Ordering Information

PART NUMBER* PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HFA3046B HFA3046B -55 to 125 14 Ld SOIC M14.15 HFA3046BZ (Note) HFA3046BZ -55 to 125 14 Ld SOIC (Pb-free) M14.15 HFA3096B HFA3096B -55 to 125 16 Ld SOIC M16.15 HFA3096BZ (Note) HFA3096BZ -55 to 125 16 Ld SOIC (Pb-free) M16.15 HFA3127B HFA3127B -55 to 125 16 Ld SOIC M16.15 HFA3127BZ (Note) HFA3127BZ -55 to 125 16 Ld SOIC (Pb-free) M16.15 HFA3127R 127 -55 to 125 16 Ld 3x3 QFN L16.3x3 HFA3127RZ (Note) 127Z -55 to 125 16 Ld 3x3 QFN (Pb-free) L16.3x3 HFA3128B HFA3128B -55 to 125 16 Ld SOIC M16.15 HFA3128BZ (Note) HFA3128BZ -55 to 125 16 Ld SOIC (Pb-free) M16.15 HFA3128R 128 -55 to 125 16 Ld 3x3 QFN L16.3x3 HFA3128RZ (Note) 128Z -55 to 125 16 Ld 3x3 QFN (Pb-free) L16.3x3 *Add “96” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. December 21, 2005

2 FN3076.13 December 21, 2005 Pinouts HFA3046 TOP VIEW HFA3096 TOP VIEW HFA3127 TOP VIEW HFA3128 TOP VIEW HFA3127, HFA3128 TOP VIEW Q5 14 NC Q5 14 Q3 Q4 NC Q3 Q4 NC Q2E Q2B NC Q3C Q2C Q1C Q1E Q1B 16 14 13 657 8 Q5B Q5E Q5C Q4C Q3E Q3B Q4B Q4E HFA3046, HFA3096, HFA3127, HFA3128

3 FN3076.13 December 21, 2005 Absolute Maximum Ratings Thermal Information J = 150°C 34mA at TJ = 125°C 37mA at TJ = 110°C Operating Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications TA = 25°C PARAMETER TEST CONDITIONS DIE SOIC, QFN UNITSMIN TYP MAX MIN TYP MAX DC NPN CHARACTERISTICS Collector to Base Breakdown Voltage, V(BR)CBO IC = 100µA, IE = 0 12 18 - 12 18 - V Collector to Emitter Breakdown Voltage, V(BR)CEO IC = 100µA, IB = 0 8 12 - 8 12 - V Collector to Emitter Breakdown Voltage, V(BR)CES IC = 100µA, Base Shorted to Emitter 10 20 - 10 20 - V Emitter to Base Breakdown Voltage, V(BR)EBO IE = 10µA, IC = 0 5.5 6 - 5.5 6 - V Collector-Cutoff-Current, ICEO VCE = 6V, IB = 0 - 2 100 - 2 100 nA Collector-Cutoff-Current, ICBO VCB = 8V, IE = 0 - 0.1 10 - 0.1 10 nA Collector to Emitter Saturation Voltage, VCE(SAT) IC = 10mA, IB = 1mA - 0.3 0.5 - 0.3 0.5 V Base to Emitter Voltage, VBE IC = 10mA - 0.85 0.95 - 0.85 0.95 V DC Forward-Current Transfer Ratio, hFE IC = 10mA, VCE = 2V 40 130 - 40 130 - Early Voltage, VA IC = 1mA, VCE = 3.5V 20 50 - 20 50 - V Base to Emitter Voltage Drift I C = 10mA - -1.5 - - -1.5 - mV/°C Collector to Collector Leakage - 1 - - 1 - pA Electrical Specifications TA = 25°C PARAMETER TEST CONDITIONS DIE SOIC, QFN UNITSMIN TYP MAX MIN TYP MAX DYNAMIC NPN CHARACTERISTICS Noise Figure f = 1.0GHz, V CE = 5V, IC = 5mA, ZS = 50Ω - 3.5 - - 3.5 - dB fT Current Gain-Bandwidth Product IC = 1mA, VCE = 5V - 5.5 - - 5.5 - GHz IC = 10mA, VCE = 5V - 8 - - 8 - GHz HFA3046, HFA3096, HFA3127, HFA3128

4 FN3076.13 December 21, 2005 Power Gain-Bandwidth Product, fMAX IC = 10mA, VCE = 5V - 6 - - 2.5 - GHz Base to Emitter Capacitance V BE = -3V - 200 - - 500 - fF Collector to Base Capacitance V CB = 3V - 200 - - 500 - fF Electrical Specifications TA = 25°C (Continued) PARAMETER TEST CONDITIONS DIE SOIC, QFN UNITSMIN TYP MAX MIN TYP MAX Electrical Specifications TA = 25°C PARAMETER TEST CONDITIONS DIE SOIC, QFN UNITSMIN TYP MAX MIN TYP MAX DC PNP CHARACTERISTICS Collector to Base Breakdown Voltage, V(BR)CBO IC = -100µA, IE = 0 10 15 - 10 15 - V Collector to Emitter Breakdown Voltage, V(BR)CEO IC = -100µA, IB = 0 8 15 - 8 15 - V Collector to Emitter Breakdown Voltage, V(BR)CES IC = -100µA, Base Shorted to Emitter 10 15 - 10 15 - V Emitter to Base Breakdown Voltage, V(BR)EBO IE = -10µA, IC = 0 4.5 5 - 4.5 5 - V Collector Cutoff Current, ICEO VCE = -6V, IB = 0 - 2 100 - 2 100 nA Collector Cutoff Current, ICBO VCB = -8V, IE = 0 - 0.1 10 - 0.1 10 nA Collector to Emitter Saturation Voltage, VCE(SAT) Base to Emitter Voltage, VBE IC = -10mA - 0.85 0.95 - 0.85 0.95 V DC Forward-Current Transfer Ratio, hFE IC = -10mA, VCE = -2V 20 60 - 20 60 - Early Voltage, VA IC = -1mA, VCE = -3.5V 10 20 - 10 20 - V Base to Emitter Voltage Drift I C = -10mA - -1.5 - - -1.5 - mV/°C Collector to Collector Leakage - 1 - - 1 - pA Electrical Specifications TA = 25°C PARAMETER TEST CONDITIONS DIE SOIC, QFN UNITSMIN TYP MAX MIN TYP MAX DYNAMIC PNP CHARACTERISTICS Noise Figure f = 1.0GHz, V CE = -5V, IC = -5mA, ZS = 50Ω - 3.5 - - 3.5 - dB fT Current Gain-Bandwidth Product IC = -1mA, VCE = -5V - 2 - - 2 - GHz IC = -10mA, VCE = -5V - 5.5 - - 5.5 - GHz Power Gain-Bandwidth Product IC = -10mA, VCE = -5V - 3 - - 2 - GHz Base to Emitter Capacitance V BE = 3V - 200 - - 500 - fF Collector to Base Capacitance V CB = -3V - 300 - - 600 - fF HFA3046, HFA3096, HFA3127, HFA3128

5 FN3076.13 December 21, 2005 DIFFERENTIAL PAIR MATCHING CHARACTERISTICS FOR THE HFA3046 Input Offset Voltage I C = 10mA, VCE = 5V - 1.5 5.0 - 1.5 5.0 mV Input Offset Current I C = 10mA, VCE = 5V - 5 25 - 5 25 µA Input Offset Voltage TC I C = 10mA, VCE = 5V - 0.5 - - 0.5 - µV/°C S-Parameter and PSPICE model data is available from Intersil Sales Offices, and Intersil Corporation’s web site. Electrical Specifications TA = 25°C (Continued) PARAMETER TEST CONDITIONS DIE SOIC, QFN UNITSMIN TYP MAX MIN TYP MAX Common Emitter S-Parameters of NPN 3µm x 50µm Transistor FREQ. (Hz) |S 11| PHASE(S 11)| S 21| PHASE(S 21)| S 12| PHASE(S 12)| S 22|P H A S E ( S 22) VCE = 5V and IC = 5mA HFA3046, HFA3096, HFA3127, HFA3128

6 FN3076.13 December 21, 2005 VCE = 5V and IC = 10mA Common Emitter S-Parameters of PNP 3µm x 50µm Transistor FREQ. (Hz) |S 11| PHASE(S 11)| S 21| PHASE(S 21)| S 12| PHASE(S 12)| S 22|P H A S E ( S 22) VCE = -5V and IC = -5mA Common Emitter S-Parameters of NPN 3µm x 50µm Transistor (Continued) FREQ. (Hz) |S 11| PHASE(S 11)| S 21| PHASE(S 21)| S 12| PHASE(S 12)| S 22|P H A S E ( S 22) HFA3046, HFA3096, HFA3127, HFA3128

7 FN3076.13 December 21, 2005 V CE = -5V, IC = -10mA Common Emitter S-Parameters of PNP 3µm x 50µm Transistor (Continued) FREQ. (Hz) |S 11| PHASE(S 11)| S 21| PHASE(S 21)| S 12| PHASE(S 12)| S 22|P H A S E ( S 22) HFA3046, HFA3096, HFA3127, HFA3128

10 FN3076.13 December 21, 2005 Die Characteristics DIE DIMENSIONS: 53 mils x 52 mils x 19 mils 1340µm x 1320µm x 483µm METALLIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: 8k Å ±0.4kÅ Type: Metal 2: AlCu(2%) Thickness: Metal 2: 16k Å ±0.8kÅ PASSIVATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ PROCESS: UHF-1 SUBSTRATE POTENTIAL: (POWERED UP) Unbiased Metallization Mask Layout HFA3096, HFA3127, HFA3128 HFA3046 Pad numbers correspond to SOIC pinout. 78 9 1 0 1516 1320µm (52 mils) 1340µm (53 mils) 78 9 1314 1320µm (52 mils) 1340µm (53 mils) HFA3046, HFA3096, HFA3127, HFA3128

11 FN3076.13 December 21, 2005 HFA3046, HFA3096, HFA3127, HFA3128 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 4 1 4 7 α 0° 8° 0° 8° - Rev. 0 12/93

12 FN3076.13 December 21, 2005 HFA3046, HFA3096, HFA3127, HFA3128 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0° 8° 0° 8° - Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3076.13 December 21, 2005 HFA3046, HFA3096, HFA3127, HFA3128 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) INDEX D1/2 D/2 D E1/2 E/2 E A 0.15 B C

0.10 BAMC

A N SEATING PLANE N e 0.08 FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE CC SECTION "C-C" NX b C C0.15 0.15 B REF. (Nd-1)Xe (Ne-1)Xe REF. 4X P A C C 4X P B AC0.15 E2/2 TERMINAL TIP SIDE VIEW TOP VIEW BOTTOM VIEW CL CL e e NX k NX b NX L AREA 4X 0.10 C/ / (DATUM B) (DATUM A) AREA INDEX AREA N 9 CORNER OPTION 4X L10 L1 L10 L16.3x3

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 9 A3 0.20 REF 9 b 0.18 0.23 0.30 5, 8 D 3.00 BSC - D1 2.75 BSC 9 D2 1.35 1.50 1.65 7, 8, 10 E 3.00 BSC - E1 2.75 BSC 9 E2 1.35 1.50 1.65 7, 8, 10 e 0.50 BSC - k0 . 2 0 - - - L 0.30 0.40 0.50 8 N1 6 2 Nd 4 3 Ne 4 3 P- -0 . 6 0 9 θ -- 1 2 9 Rev. 1 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are prov ided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension.