128M-DDR1-AS4C8M16D1

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AS4ϴDϭϲϭ- ϲϬ-ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet DĂLJ201ϱ 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\ $OOLDQFH0HPRU\\,QF7D\\ORU:D\\6DQ&DUORV&$ 7(/ )$; $OOLDQFH0HPRU\\,QFUHVHUYHVWKHULJKWWRFKDQJHSURGXFWVRUVSHFLILFDWLRQZLWKRXWQRWLFH

)HDWXUHV ¥ Fast clock rate: 250/200MHz

• Operating temperature: - Commercial (0°C~70°C) - Industrial (-40°C~85°C) ¥ Differential Clock CK & CK input ¥ Bi-directional DQS ¥ DLL enable/disable by EMRS ¥ Fully synchronous operation ¥ Internal pipeline architecture ¥ Four internal banks, 2M x 16-bit for each bank ¥ Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved ¥ Individual byte write mask control ¥ DM Write Latency = 0 ¥ Auto Refresh and Self Refresh ¥ 4096 refresh cycles / 64ms ¥ Precharge & active power down ¥ Power supplies: VDD & VDDQ = 2.5V ± 0.2V ¥ Interface: SSTL_2 I/O Interface ¥ Package: 60-Ball, 8x13x1.2 mm (max) FBGA - Pb free and Halogen free 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7DEOH2UGHULQJ,QIRUPDWLRQ 3DUW1XPEHU 2UJ 7HPSHUDWXUH 3DFNDJH $6&0'%,1 EDOO)%*$ [ ,QGXVWULDOƒ&WRƒ& 0D[&ORFN 0+] 2YHUYLHZ The 128Mb DDR SDRAM is a high -speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 D RAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK DQG&. Read and write accesses to the SDRAM are burst oriented; accesses sta rt at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The device provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self -timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, 128Mb DDR features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidt h and high performance . 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

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CK, CK Input 'LIIHUHQWLDO&ORFN CK, CK are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. Both CK and CK increment the internal burst counter and controls the output registers. CKE Input &ORFN(QDEOH CKE activates ( HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When al l banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0, BA1 Input %DQN $FWLYDWH BA 0 and B A1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. A0-A11 Input $GGUHVV,QSXWV A0-A11 are sampled during the BankActivate command (row address A0 - A11) and Read/Write command (column address A0 -A8 with A10 defining Auto Precharge). CS Input &KLS6HOHFW CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS Input 5RZ$GGUHVV6WUREH The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latch ed at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by B A is turned on to the active state. When the WE is asserted "LOW," the Precharge comm and is selected and the bank designated by B A is switched to the idle state after the precharge operation. CAS Input &ROXPQ$GGUHVV6WUREH The CAS signal defines the operation commands in conjunction with t he RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGHÓ or ÒLOW". WE Input :ULWH(QDEOH The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command . LDQS, UDQS Input / Output %LGLUHFWLRQDO'DWD6WUREH Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. LDM, UDM Input 'DWD,QSXW0DVN Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8 -DQ15. DQ0 - DQ15 Input / Output 'DWD ,2 The DQ0 -DQ15 input and output data are synchronized with positive and negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes. VDD Supply 3RZHU6XSSO\\ +2.5V ± 0.2V VSS Supply *URXQG VDDQ Supply '43RZHU +2.5V ± 0.2V. Provide isolated power to DQs for improved noise immunity. VSSQ Supply '4*URXQG Provide isolated ground to DQs for improved noise immunity. VREF Supply 5HIHUHQFH9ROWDJHIRU,QSXWV +0.5*VDDQ NC - 1R&RQQHFW No internal connection, t hese pins suggest to be left unconnected. 3LQ'HVFULSWLRQV 7DEOH3LQ'HWDLOV 6\\PERO 7\\SH 'HVFULSWLRQ 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY0D\\

Fully synchronous operati ons are performed to latch the command s at the positive edges of CK. Table 3 shows the truth table for the operation commands. 7DEOH7UXWK7DEOH 1RWH &RPPDQG 6WDWH &.(Q &.(Q '0 %$ $ $ &6 5$6&$6 :( BankActivate Idle(3) H X X V Row address L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X L L H L Write Active(3) H X X V L Column address (A0 ~ A8) L H L L Write and AutoPrecharge Active(3) H X X V H L H L L Read Active(3) H X X V L Column address (A0 ~ A8) L H L H Read and Autoprecharge Active(3) H X X V H L H L H Mode Register Set Idle H X X OP code L L L L Extended MRS Idle H X X OP code L L L L No-Operation Any H X X X X X L H H H Burst Stop Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X (SelfRefresh) L H H H Precharge Power Down Mode Entry Idle H L X X X X H X X X L H H H Precharge Power Down Mode Exit Any L H X X X X H X X X (PowerDown) L H H H Active Power Down Mode Entry Active H L X X X X H X X X L V V V Active Power Down Mode Exit Any L H X X X X H X X X (PowerDown) L H H H Data Input Mask Disable Active H X L X X X X X X X Data Input Mask Enable(5) Active H X H X X X X X X X 1RWH 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by B A signal. 4. Device state is 2, 4, and 8 burst operation. 5. LDM and UDM can be enable d respectively. 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low on CS, RAS, CAS, WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of ad dress pins A0~A11 and BA0, BA1 in the same cycle in which CS, RAS, CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for va rious burst lengths, burst types and CAS latencies. 7DEOH0RGH5HJLVWHU%LWPDS BA1 B A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0 0 0 T.M. CAS Latency BT Burst Length Mode Register A8 A7 Test Mode A6 A5 A4 CAS Latency A3 Burst Type A2 A1 A0 Burst Length 0 0 Normal mode 0 0 0 Reserved 0 Sequential 0 0 0 Reserved 1 0 DLL Reset 0 0 1 Reserved 1 Interleave 0 0 1 2 X 1 Test mode 0 1 0 2 0 1 0 4 0 1 1 3 0 1 1 8 1 0 0 Reserved 1 0 0 Reserved BA0 Mode 1 0 1 Reserved 1 0 1 Reserved 0 MRS 1 1 0 2.5 1 1 0 Reserved

1 EMRS 1 1 1 Reserved 1 1 1 Reserved

¥ Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, and 8. 7DEOH%XUVW/HQJWK A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

¥ Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4, and 8. 7DEOH$GGUHVVLQJ0RGH A3 Addressing Mode

0 Sequential

1 Interleave

¥ Burst Definition, Addressing Sequence of Sequential and Interleave Mode 7DEOH%XUVW$GGUHVVRUGHULQJ Burst Length Start Address Sequential InterleaveA2 A1 A0

2 X X 0 0, 1 0, 1

X X 1 1, 0 1, 0 X 0 0 0, 1, 2, 3 0, 1, 2, 3 X 0 1 1, 2, 3, 0 1, 0, 3, 2 X 1 0 2, 3, 0, 1 2, 3, 0, 1 X 1 1 3, 0, 1, 2 3, 2, 1, 0 ¥ CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ! CAS Latency X tCK 7DEOH&$6/DWHQF\\ A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 clocks 1 1 1 Reserved 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

¥ Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. 7DEOH 7HVW0RGH A8 A7 Test Mode 0 0 Normal mode 1 0 DLL Reset X 1 Test mode ¥ (BA0, BA1) 7DEOH056(056 BA1 BA0 A11 ~ A0 RFU 0 MRS Cycle RFU 1 Extended Functions (EMRS) ([WHQGHG0RGH5HJLVWHU6HW (056 The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is w ritten by asserting low on CS, RAS, CAS, and WE . The state of A0, A2 ~ A5, A7 ~ A11and B A1 is written in the mode register in the same cycle as CS,RAS, CAS, and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for set ting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on B A0 is used for EMRS. Refer to the table for specific codes. 7DEOH([WHQGHG0RGH5HJLVWHU%LWPDS BA1 B A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 0 1 RFU must be set to Ò0Ó DS1 RFU must be set to Ò0Ó DS0 DLL Extended Mode Register BA0 Mode A6 A1 Drive Strength Comment A0 DLL

0 MRS 0 0 Full 0 Enable

1 EMRS 0 1 W eak 1 Disable

1 0 RFU Reserved For Futur e 1 1 Matched impedance Output driver matches impedance 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7DEOH$EVROXWH0D[LPXP5DWLQJ 6\\PERO ,WHP 5DWLQJ 8QLW VIN, VOUT I/O Pins Voltage - 0.5~VDDQ + 0.5 V VIN VREF and Inputs Voltage - 1~3.6 V VDD, VDDQ Power Supply Voltage - 1~3.6 V TA Ambient Temperature Commercial 0~70 !C Industrial -40~85 !C TSTG Storage Temperature - 55~150 !C PD Power Dissipation 1 W IOS Short Circuit Output Cu rrent 50 mA Note1: Stress greater than those listed under ÒAbsolute Maximum Ratings Ó may cause permanent damage of the devices Note2: These voltages are relative to Vss 7DEOH5HFRPPHQGHG'&2SHUDWLQJ&RQGLWLRQV 6\\PERO 3DUDPHWHU 0LQ 0D[ 8QLW VDD Power Supply Voltage 2.3 2.7 V VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.7 V VREF Input Reference Voltage 0.49 * VDDQ 0.51 * VDDQ V VTT Termination Voltage VREF - 0.04 V REF + 0.04 V VIH (DC) Input High Voltage (DC) VREF + 0.15 V DDQ + 0.3 V VIL (DC) Input Low Voltage (DC) -0.3 VREF - 0.15 V VIN (DC) Input Voltage Level, CK and CK inputs -0.3 VDDQ + 0.3 V II Input Leakage current, Any input 0V " VIN " VDD (All other pins not under test = 0 V) -2 2 µA IOZ Output Leakage current -5 5 µA IOH Output High Current (VOUT = 1.95V) -16.2 mA IOL Output Low Current (VOUT = 0.35V) 16.2 mA 7DEOH&DSDFLWDQFH 9'' 9I 0+]7$ ¡& 6\\PERO 3DUDPHWHU 0LQ 0D[ 8QLW CIN1 Input Capacitance ( CK, CK) 2 3 pF CIN2 Input Capacitance ( All other input-only pins) 2 3 pF CI/O DQ, DQS, DM Input/Output Capacitance 4 5 pF Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7DEOH'&&KDUDFWHULVWLFV 9'' 9“97$ a¡& 3DUDPHWHU 7HVW&RQGLWLRQ 6\\PERO 8QLW0D[ 23(5$7,1*&855(17 One bank; Active-Precharge; tRC=tRC (min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs chang ing once every two clock cycles. IDD0 60 55 mA 23(5$7,1*&855(17 One bank; Active-Read-Precharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing once per clock cycle IDD1 75 65 mA All banks idle; power-down mode; tCK=tCK(min); CKE=LOW IDD2P 5 5 mA ,'/(67$1'/<&855(17 CKE = HIGH; CS=HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM IDD2N 30 30 mA one bank active; power - down mode; CKE=LOW; t CK=tCK(min) IDD3P 17 17 mA CS=HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and c ontrol inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle IDD3N 40 40 mA BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer IDD4R 120 100 mA BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer IDD4W 120 100 mA $8725()5(6+&855(17 tRC=tRFC(min); tCK=tCK(min) IDD5 80 70 mA 6(/)5()5(6+&855(17 Self Refresh Mode ; CKE 0.2V;tCK=tCK(min) IDD6 2 2 mA %856723(5$7,1*&855(17EDQNRSHUDWL RQ Four bank interleaving READs; BL=4; with Auto Precharge; t RC=tRC(min); tCK=tCK(min); Address and control inputs change only during Active, READ , or WRITE command IDD7 160 140 mA )LJXUH 7LPLQJ:DYHIRUPIRU,''0HDVXUHPHQWDW0+]&.2SHUDWLRQ CK CK ADDRESS COMMAND tRCD ACT READ AP ACT READ AP ACT READ AP ACT ACTREAD AP Bank 0 Row d Bank 3 Col c Bank 1 Row e Bank 0 Col d Bank 2 Row f Bank 1 Col e Bank 3 Row g Bank 0 Row h Bank 2 Col f DQS DQ CL=3 D0 a D0 a D0 b D0 b D0 b D0 b D0 c D0 c D0 c D0 c D0 d D0 d D0 d D0 d D0 e D0 e D0 e D0 e D0 f D0 fD0 a D0 a 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7DEOH(OHFWULFDO$&&KDUDFWHULVWLFV 9'' 9“97$ a¡& 6\\PERO 3DUDPHWHU 8QLW0LQ 0D[ 0LQ 0D[ CL=2 - - 7.5 12 ns tCK Clock cycle time CL=2.5 - - 6 12 ns CL = 3 4 12 5 12 ns tCH Clock high level width 0.45 0.55 0.45 0.55 t CK tCL Clock low level width 0.45 0.55 0.45 0.55 t CK tDQSCK DQS-out access time from CK, CK -0.7 0.7 - 0.6 0.6 ns tAC Output access time from CK, CK -0.7 0.7 - 0.7 0.7 ns tDQSQ DQS-DQ Skew - 0.4 - 0.4 ns tRPRE Read preamble 0.9 1.1 0.9 1.1 t CK tRPST Read postamble 0.4 0.6 0.4 0.6 t CK tDQSS CK to valid DQS-in 0.8 1.2 0.72 1.25 t CK tWPRES DQS-in setup time 0 - 0 - ns tWPRE DQS write preamble 0.25 - 0.25 - t CK tWPST DQS write postamble 0.4 0.6 0.4 0.6 t CK tDQSH DQS in high level pulse width 0.35 - 0.35 - t CK tDQSL DQS in low level pulse width 0.35 - 0.35 - t CK tIS Address and Control input setup time 0.7 - 0.7 - ns tIH Address and Control input hold time 0.7 - 0.7 - ns tDS DQ & DM setup time to DQS 0.4 - 0.4 - ns tDH DQ & DM hold time to DQS 0.4 - 0.4 - ns tHP Clock half period tCLMIN or tCHMIN - tCLMIN or tCHMIN - ns tQH DQ/DQS output hold time from DQS tHP - tQHS - t HP - tQHS - ns tRC Row cycle time 52 - 55 - ns tRFC Refresh row cycle time 70 - 70 - ns tRAS Row active time 36 70K 40 70K ns tRCD Active to Read or Write delay 16 - 15 - ns tRP Row precharge time 16 - 15 - ns tRRD Row active to Row active delay 8 - 10 - ns tWR Write recovery time 12 - 15 - ns tMRD Mode register set cycle time 2 - 2 - t CK tDAL Auto precharge write recovery + Precharge time t WR + tRP - t WR + tRP - t CK tXSRD Self refresh exit to read command delay 200 - 200 - t CK tREFI Refresh interval time - 15.6 - 15.6 µs tIPW Co ntrol and Address input pulse width 2.2 - 2.2 - ns tDIPW DQ & DM input pulse width (for each input) 1.75 - 1.75 - ns tHZ Data-out high-impedance window from CK, CK - 0.7 - 0.7 ns tLZ Data-out low-impedance window from CK, CK -0.7 0.7 - 0.7 0.7 ns tQHS Data Hold Skew Factor - 0.5 - 0.5 ns tDSS DQS falling edge to CK rising Ð setup time 0.2 - 0.2 - t CK tDSH DQS falling edge to CK rising Ð hold time 0.2 - 0.2 - t CK tWTR Internal Write to Read c ommand delay 2 - 2 - t CK tXSNR Exit Self-Refresh to non-Read command 75 - 75 - ns 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7DEOH5HFRPPHQGHG$&2SHUDWLQJ&RQGLWLRQV 9'' 9“97$ a¡& 6\\PERO 3DUDPHWHU 0LQ 0D[ 8QLW VIH (AC) Input High Voltage (AC) VREF + 0.31 - V VIL (AC) Input Low Voltage (AC) - VREF Ð 0.31 V VID (AC) Input Different Voltage, CK and CK inputs 0.7 VDDQ + 0.6 V VIX (AC) Input Crossing Point Voltage, CK and CK inputs 0.5 * VDDQ-0.2 0.5 * VDDQ+0.2 V 1RWH 1. All voltages are referenced to V SS. 2. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during t CK. 3. Power-up sequence is described in Note 5. 4. A.C. Test Conditions 7DEOH667/B,QWHUIDFH Reference Level of Output Signals (V REF) 0.5 * VDDQ Output Load Reference to the Test Load Input Signal Levels(VIH / VIL) VREF+0.31 V / VREF-0.31V Input Signals Slew Rate 1 V/ns Reference Level of Input Signals 0.5 * VDDQ )LJXUH667/B$&7HVW/RDG '4'46 = ȍ ȍ 9''4 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

1. 3RZHUXS6HTXHQFH Power up must be performed in the following sequence. 1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held "NOP" state and maintain CKE ÒLOWÓ. 2) Start clock and maintain stable condition for minimum 200 µs. 3) Issue a ÒNOPÓ command and keep CKE ÒHIGHÓ 4) Issue a ÒPrecharge AllÓ command. 5) Issue EMRS Ð enable DLL. 6) Issue MRS Ð reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS Ð with A8 to low to initialize the mode register. 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7LPLQJ:DYHIRUPV )LJXUH$FWLYDWLQJD6SHFLILF5RZLQD6SHFLILF%DQN CK CK CKE CS RAS CAS WE RAAddress BABA0,1 DonÕt Care HIGH RA=Row Address BA=Bank Address 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

BA0,BA1 ACT NOPCOMMAND NOP ACT NOP NOP RD/WR NOP Row Row Col Bank A Bank B Bank B tRRD tRCD DonÕt Care )LJXUH5($'&RPPDQG CK CK CKE CS RAS CAS WE CA A0 - A8 A10 DonÕt Care HIGH EN AP DIS AP BABA0,1 CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge )LJXUHW5&'DQGW55''HILQLWLRQ 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5HDG%XUVW5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP NOP NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=2 DonÕt Care DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n DO n 5HDG%XUVW5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP NOP NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=2.5 DonÕt Care DO n=Data Out from column n DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

n CK CK COMMAND READ NOP NOP NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 DonÕt Care DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n 5HDG%XUVW5HTXLUHG&$6/DWHQFLHV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH &RQVHFXWLYH5HDG%XUVWV5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=2 DO n DonÕt Care Bank, Col o DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 DonÕt Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n &RQVHFXWLYH5HDG%XUVWV5HTXLUHG&$6/DWHQFLHV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

&RQVHFXWLYH5HDG%XUVWV5HTXLUHG&$6/DWHQFLHV DO o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=3 DonÕt Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH1RQ&RQVHFXWLYH5HDG%XUVWV5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2 DonÕt Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO o DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

1RQ&RQVHFXWLYH5HDG%XUVWV5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 DonÕt Care Bank, Col o NOP DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO n DO o 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

1RQ&RQVHFXWLYH5HDG%XUVWV5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 DonÕt Care Bank, Col o NOP DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO o DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5DQGRP5HDG$FFHVVHV5HTXLUHG&$6/DWHQFLHV DO p DO DO o DO DO DO q CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2 DonÕt Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n ' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

p DO DO o DO DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 DonÕt Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n ' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n 5DQGRP5HDG$FFHVVHV5HTXLUHG&$6/DWHQFLHV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

5DQGRP5HDG$FFHVVHV5HTXLUHG&$6/DWHQFLHV DO p DO DO o DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 DonÕt Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n ' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH7HUPLQDWLQJD5HDG%XUVW5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=2 DonÕt Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=2.5 DonÕt Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n 7HUPLQDWLQJD5HDG%XUVW5HTXLUHG&$6/DWHQFLHV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

7HUPLQDWLQJD5HDG%XUVW5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 DonÕt Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5HDGWR:ULWH5HTXLUHG&$6/DWHQFLHV READ BST NOP WRITE NOP NOP Bank, Col n CL=2 DonÕt Care Bank, Col o DI o tDQSS min DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n CK CK COMMAND ADDRESS DQS DQ DM 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=2.5 DonÕt Care min tDQSS DI o DM Bank, Col o DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n 5HDGWR:ULWH5HTXLUHG&$6/DWHQFLHV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

5HDGWR:ULWH5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=3 DonÕt Care Bank, Col o min tDQSS DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5HDGWR3UHFKDUJH5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=2 DonÕt Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=2.5 DonÕt Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n 5HDGWR3UHFKDUJH5HTXLUHG&$6/DWHQFLHV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

5HDGWR3UHFKDUJH5HTXLUHG&$6/DWHQFLHV CK CK COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=3 DonÕt Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWH&RPPDQG CK CK CKE CS RAS CAS WE CA A0 - A8 A10 DonÕt Care HIGH EN AP DIS AP BABA0,1 CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWH0D['466 CK CK COMMAND WRITE NOP NOP NOP Bank A, Col nADDRESS DQS DQ tDQSS DonÕt Care DM T0 T1 T2 T3 T4 T5 T6 T7 max DI n DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWH0LQ'466 CK CK COMMAND WRITE NOP NOP NOP Bank A, Col nADDRESS DQS DQ tDQSS DM T0 T1 T2 T3 T4 T5 T6 min DI n DonÕt Care DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWH%XUVW1RP0LQDQG0D[W'466 CK CK COMMAND WRITE NOP NOP NOP Bank , Col nADDRESS DQS DQ tDQSS (nom) DonÕt Care DM T0 T1 T2 T3 T4 T5 T6 T7 DI n T8 T9 T10 T11 NOP NOP DQS DQ tDQSS (min) DM DI n DQS DQ tDQSS (max) DM DI n DI n = Data In for column n 3 subsequent elements of Data are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) DM=UDM & LDM 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH :ULWHWR:ULWH0D[W'466 CK CK COMMAND WRITE NOP WRITE NOP Bank , Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP DQS DQ tDQSS (max) DM DI n Bank , Col o DI o DonÕt Care DI n , etc. = Data In for column n,etc. 3 subsequent elements of Data In are applied in the programmed order following DI n Non-interrupted bursts of 4 are shown DM= UDM & LDM 3 subsequent elements of Data In are applied in the programmed order following DI o 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

COMMAND WRITE NOP NOP WRITE Bank Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP DQS DQ tDQSS (max) DM DI n Bank Col o DI o DonÕt Care DI n, etc. = Data In for column n, etc. 3 subsequent elements of Data In are applied in the programmed order following DI n Non-interrupted bursts of 4 are shown DM= UDM & LDM 3 subsequent elements of Data In are applied in the programmed order following DI o )LJXUH:ULWHWR:ULWH0D[W'4661RQ&RQVHFXWLYH 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5DQGRP:ULWH&\\FOHV0D[W'466 CK CK COMMAND WRITE WRITE WRITE WRITE Bank Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WRITE DQS DQ tDQSS (max) DM DI n Bank Col q DI o DI n ' DI o ' DI p DI p ' DI q DI q ' Bank Col o Bank Col p Bank Col r DonÕt Care DI n, etc. = Data In for column n, etc. n', etc. = the next Data In following DI n, etc. according to the programmed burst order If burst of 4 or 8, the burst would be truncated DM= UDM & LDM Programmed Burst Length 2, 4, or 8 in cases shown Each WRITE command may be to any bank and may be to the same or different devices 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWHWR5HDG0D[W'4661RQ,QWHUUXSWLQJ CK CK COMMAND WRITE NOP NOP READ Bank Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP DQS DQ tDQSS (max) DM DI n Bank Col o T10 T11 NOP tWTR CL=3 DonÕt Care DI n, etc. = Data In for column n, etc. 1 subsequent elements of Data In are applied in the programmed order following DI n tWTR is referenced from the first positive CK edge after the last Data In Pair DM= UDM & LDM A non-interrupted burst of 2 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank T12 NOP 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWHWR5HDG0D[W'466,QWHUUXSWLQJ CK CK COMMAND WRITE NOP NOP READ Bank Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP DQS DQ tDQSS (max) DM DI n Bank Col o T10 T11 NOP tWTR CL=3 DonÕt Care DI n, etc. = Data In for column n, etc. 1 subsequent elements of Data In are applied in the programmed order following DI n tWTR is referenced from the first positive CK edge after the last Data In Pair DM= UDM & LDM An interrupted burst of 8 is shown, 2 data elements are written A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank T12 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWHWR5HDG0D[W'4662''1XPEHURI'DWD,QWHUUXSWLQJ CK CK WRITE NOP NOP READ Bank Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP DQS DQ tDQSS (max) DM DI n Bank Col o T10 T11 NOP tWTR CL=3 DonÕt Care DI n = Data In for column n tWTR is referenced from the first positive CK edge after the last Data In Pair (not the last desired Data In element) DM= UDM & LDM An interrupted burst of 8 is shown, 1 data elements are written A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank T12 COMMAND 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWHWR3UHFKDUJH0D[W'466121,QWHUUXSWLQJ CK CK COMMAND WRITE NOP NOP NOP Bank a, Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 PRE DQS DQ tDQSS (max) DM DI n Bank (a or al) T10 T11 NOP tWR tRP DonÕt Care DI n = Data In for column n 1 subsequent elements of Data In are applied in the programmed order following DI n tWR is referenced from the first positive CK edge after the last Data In Pair DM= UDM & LDM A non-interrupted burst of 2 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWHWR3UHFKDUJH0D[W'466,QWHUUXSWLQJ CK CK COMMAND WRITE NOP NOP PRE Bank a, Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP DQS DQ tDQSS (max) DM DI n T10 T11 NOP tWR tRP DonÕt Care DI n = Data In for column n tWR is referenced from the first positive CK edge after the last Data In Pair DM= UDM & LDM An interrupted burst of 4 or 8 is shown, 2 data elements are written A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point *1 *1 *1 Bank (a or all) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWHWR3UHFKDUJH0D[W'4662''1XPEHURI'DWD,QWHUUXSWLQJ CK CK COMMAND WRITE NOP NOP Bank a, Col nADDRESS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP DQS DQ tDQSS (max) DM DI n T10 T11 NOP tWR tRP*2 DonÕt Care DI n = Data In for column n tWR is referenced from the first positive CK edge after the last Data In Pair DM= UDM & LDM An interrupted burst of 4 or 8 is shown, 1 data element is written A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point *1*1*1*1 PRE Bank (a or all) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH3UHFKDUJH&RPPDQG CK CK CKE CS RAS CAS WE A0-A9, A11 A10 DonÕt Care HIGH ALL BANKS ONE BANK BABA0,1 BA= Bank Address (if A10 is LOW, otherwise don't care) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH 3RZHU'RZQ CK CK CKE VALIDCOMMAND DonÕt Care T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tn+3 Tn+4 VALID Tn+5 Tn+6 NOP NOP No column access in progress Enter power-down mode Exit power-down mode tIS tIS )LJXUH&ORFN)UHTXHQF\\&KDQJHLQ3UHFKDUJH &0' W,6 123 123 123 '// 5(6(7 123 9DOLG123 )UHTXHQF\\&KDQJH 2FFXUVKHUH 6WDEOHQHZFORFN %HIRUHSRZHUGRZQ H[LW W53 0LQPXPFORFNV 5HTXLUHGEHIRUH &KDQJLQJIUHTXHQF\\ &ORFNV &.( 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH'DWDLQSXW :ULWH 7LPLQJ DQS DQ DonÕt Care tDS DI n DM tDH tDS tDH tDQSH tDQSL DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n )LJXUH'DWD2XWSXW 5HDG 7LPLQJ CK CK DQ tCH tCL tQH tDQSQ max tQH max tDQSQ Burst Length = 4 in the case shown DQS 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

NOP PRE EMRS MRS PRE AR AR MRS ACT CODE CODE CODE RA tVDT>=0 tCH tCL tCK tIS tIH tIS tIH CODE CODE CODE RA tIS tIH tIS tIH ALL BANKS tIS tIH ALL BANKS B A 0 = H B A 1 = L B A 0 = L B A 1 = L B A 0 = L B A 1 = L BA tIS tIH High-Z High-Z LVCMOS LOW LEVEL CK CK DM A0-A9, A11 COMMAND VREF CKE A10 BA0,BA1 DQS DQ VDD VDDQ VTT (system*) *=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up. = tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable command can be applied the two auto Refresh commands may be moved to follow the first MRS but precede the second PRECHARGE ALL command. DonÕt Care Power-up: VDD and CLK stable Extended mode Register set Load Mode Register, Reset DLL (with A8=H) 200 cycles of CK Load Mode Register, (with A8=L) T=200!s tMRD tMRD tRFC tRFC **tMRDtRP )LJXUH,QLWLDOL]HDQG0RGH5HJLVWHU6HWV 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH3RZHU'RZQ0RGH CK CK CKE VALID*COMMAND DonÕt Care VALID tCK NOP NOP Enter power-down mode Exit power-down mode tCH tCL tIStIS tIHtIS tIS tIH VALID tIS tIH ADDR VALID DQS DQ DM No column accesses are allowed to be in progress at the time Power-Down is entered *=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is active Power Down. 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH$XWR5HIUHVK0RGH CK CK A0-A8 A9,A11 VALID NOPCOMMAND tIS DonÕt Care tIH NOP AR NOP AR NOP NOP ACT tIS tIH tCH tCLtCK RA CKE RAA10 BA0,BA1 DQS DQ *Bank(s) VALID NOP PRE RA ALL BANKS ONE BANKS BA tIHtIS DM tRP tRFC tRFC * = Don't Care, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks) PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC DM, DQ and DQS signals are all Don't Care/High-Z for operations shown 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH6HOI5HIUHVK0RGH CK CK CKE NOPCOMMAND DonÕt Care VALID tCK AR NOP Clock must be stable before Exiting Self Refresh mode Enter Self Refresh mode tCH tCL tIStIS tIHtIS tIS tIH ADDR VALID DQS DQ DM tIS tIH tRP* tXSNR/ tXSRD** Exit Self Refresh mode * = Device must be in the All banks idle state prior to entering Self Refresh mode ** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is required before a READ command can be applied. 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5HDGZLWKRXW$XWR3UHFKDUJH CK CK A0-A8 NOP tIS tIH PRE NOP NOP VALID VALID VALID tIS tIH tCH tCLtCK RA CKE DM DQS NOP READ RA tIHtIS DQ CL=3 tRP ACT NOP NOP NOP Col n tIS tIH RA ALL BANKS ONE BANKS Bank X tIS tIH DIS AP *Bank X Bank X tRPRE tDQSCKmin tRPST tLZ tLZ tAC min DQS DQ tRPRE tRPST tLZ tLZ max tDQSCK tHZmax tIH max max min min DonÕt Care DO n = Data Out from column n PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * =Don't Care, if A10 is HIGH at this point NOP commands are shown for ease of illustration; other commands may be valid at these times Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks DO n DO n COMMAND A9,A11 A10 BA0,BA1 max tAC Case 1: tAC/tDQSCK=min Case 2: tAC/tDQSCK=max 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH5HDGZLWK$XWR3UHFKDUJH NOP tIS tIH NOP NOP NOP VALID VALID VALID tIS tIH tCH tCLtCK RA NOP READ RA tIHtIS CL=3 tRP ACT NOP NOP NOP Col n tIS tIH RA Bank X tIS tIH EN AP Bank X tRPRE min tRPST tLZ tAC min tRPRE tRPST tLZ tLZ max tDQSCK tHZmax tIH min max max DonÕt Care DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration; other commands may be valid at these times The READ command may not be issued until tRAP has been satisfied. If Fast Autoprecharge is supported, tRAP = tRCD, else the READ may not be issued prior to tRASmin (BL*tCK/2) DO n DO n max tAC min tLZ tDQSCK CK CK A0-A8 COMMAND CKE A10 BA0,BA1 DM DQS DQ DQS DQ A9,A11 Case 2: tAC/tDQSCK=max Case 1: tAC/tDQSCK=min 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH %DQN5HDG$FFHVV NOP tIS tIH NOP NOP READ tIS tIH tCH tCLtCK NOP ACT RA tIHtIS tRC NOP PRE NOP NOP RA tIS tIH Col n ALL BANKS ONE BANKSDIS AP Bank X tRPRE min tRPST tLZ tLZ tAC ACT RA RA RA RA *Bank XBank X tIS tIH Bank X tRAS tRCD tRP tDQSCK min min tRPRE max tLZ tAC maxmax tRPST tDQSCK DonÕt Care DO n = Data Out from column n PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = Don't Care, if A10 is HIGH at this point NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting) DO n DO n min CL=3 max tLZ max tHZ DQ DQS Case 2: tAC/tDQSCK=max DQ DQS Case 1: tAC/tDQSCK=min DM BA0,BA1 COMMAND CKE CK CK A10 A9,A11 A0-A8 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

A9,A11 NOPCOMMAND tIS tIH NOP NOP NOP VALID tIS tIH tCH tCLtCK RA CKE A10 BA0,BA1 DQS NOP WRITE RA tIHtIS DQ tDSH PRE NOP NOP ACT Col n tIS tIH RA ALL BANKS ONE BANKS Bank X tIS tIH DIS AP *Bank X BA tWPRES Case 1: tDQSS=min DI n tIH tDQSS tDSH tDQSH tDQSL tWPST tWPRE DM DQS DQ tDSS tWPRES Case 2: tDQSS=max DI n tDQSS tDSS DM tWR tRP tDQSH tWPST tDQSLtWPRE DonÕt Care DI n = Data In from column n PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *=Don't Care, if A10 is HIGH at this point NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks )LJXUH:ULWHZLWKRXW$XWR3UHFKDUJH 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

A9,A11 NOPCOMMAND tIS tIH NOP NOP NOP VALID tIS tIH tCH tCLtCK RA CKE A10 BA0,BA1 DQS NOP WRITE RA tIHtIS DQ tDSH NOP NOP NOP ACT Col n tIS tIH RA Bank X DIS AP BA tWPRES Case 1: tDQSS=min DI n tDQSS tDSH tDQSH tDQSL tWPST tWPRE DM DQS DQ tDSS tWPRES Case 2: tDQSS=max DI n tDQSS tDSS DM tDAL tDQSH tWPST tDQSL VALID VALID tWPRE DonÕt Care DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DI n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge )LJXUH:ULWHZLWK$XWR3UHFKDUJH 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

A9,A11 NOPCOMMAND tIS tIH NOP WRITE NOP tIS tIH tCH tCLtCK CKE A10 BA0,BA1 DQS NOP ACT ALL BANKS tIHtIS DQ tDSH NOP NOP NOP PRE RA tIS tIH Bank X DIS AP *Bank X tWPRES Case 1: tDQSS=min DI n tDQSS tDSH tDQSH tDQSL tWPST DM DQS DQ Case 2: tDQSS=max tDQSS tDSS DM tRAS tDQSH tWPST Col n RA RA ONE BANK tIS tIH Bank X tWRtRCD tWPRE tDSS tDQSLtWPRES tWPRE DI n DonÕt Care DI n = Data In from column n PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *=Don't Care, if A10 is HIGH at this point NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks LJXUH%DQN:ULWH$FFHVV) 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

)LJXUH:ULWH'02SHUDWLRQ CK CK A0-A8 A9,A11 NOPCOMMAND tIS tIH NOP NOP NOP VALID tIS tIH tCH tCLtCK RA CKE A10 BA0,BA1 DQS NOP WRITE RA tIHtIS DQ tDSH PRE NOP NOP ACT Col n tIS tIH RA ALL BANKS ONE BANKS Bank X tIS tIH DIS AP *Bank X BA tWPRES Case 1: tDQSS=min DI n tDQSS tDSH tDQSH tDQSL tWPST tWPRE DM DQS DQ tDSS tWPRES Case 2: tDQSS=max DI n tDQSS tDSS DM tWR tRP tDQSH tDQSLtWPRE tWPST DonÕt Care DI n = Data In from column n PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *=Don't Care, if A10 is HIGH at this point NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks 128M DDR1 -AS4C8M16D1 &RQILGHQWLDO 5HY 0D\\

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