Power Management

125CDMCCDS-4R7MC

Texas Instruments

TPS55288 36-V, 16-A Buck-boost Converter with I2C Interface

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ADVANCE□INFORMATION DR1L VIN TPS55288 ILIM VIN = 2.7V to 36V MODE PGND COMP VOUT VOUT =0.8V to 22V BOOT1 OFF ON 4.7µH SW2 BOOT2DR1H AGND SCL SDA VCCC3 4.7µF FSW EN/UVLO SW1 CDC DITH/SYNC ISP ISN 10P 0.1µF0.1µF FB/INT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS55288 SLVSF01 –MARCH 2020 TPS5528836-V,16-ABuck-boostConverterwithI2CInterface

1 Features

1• Input voltage range: 2.7 V to 36 V

Output voltage range: 0.8 V to 21.26 V
97% efficiency at VIN = 12 V, VOUT = 20 V and IOUT = 3 A
Programmable average inductor current limit up to 16 A
Adjustable switching frequency 200 kHz to

2.4 MHz

Adjustable output voltage compensation for voltage droop over the cable
Programmable PFM and FPWM mode at light load
Programmable output voltage up to 21.26 V
Programmable output current limit
±1% reference voltage accuracy
Fixed 4-ms soft-start time
I2C Interface
Output over-voltage protection
Hiccup mode for output short-circuit protection
Thermal shutdown protection
4.0-mm × 3.5-mm Hotrod™ QFN package

2 Applications

USB PD
Car charger
Docking station
Industrial PC

3 Description

The TPS55288 is a synchronous buck-boost converter optimized for converting battery voltage or adaptor voltage into power supply rails. The TPS55288 integrates two 16-A MOSFETs of the boost leg to balance the solution size and efficiency for USB Power Delivery (USB PD) application. The TPS55288 has up to 36 V input voltage capability. It can output 15 A when working in buck mode. When working in boost mode, the device delivers 100 W from 8 V input or 60 W from 5 V input. When the input is a single cell Li-ion battery, the device outputs 45 W with input voltage down to 3.1 V. The switching frequency is programmable from 200 kHz to 2.4 MHz through an external resistor. Through the I2C interface, the output voltage of the TPS55288 can be programmed from 0.8 V to 21.26 V with a 20-mV step. The default output voltage is 5 V when the device is enabled. The TPS55288 has output over-voltage protection, cycle-by-cycle switch peak-current limit, and output short-circuit protection. The TPS55288 can use a small inductor and small capacitors with high switching frequency. It is available in 4.0-mm × 3.5-mm QFN package. Device Information(1) PART NUMBER PACKAGE BODY SIZE TPS55288 VQFN-HR 4.00 mm × 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit

11.2 Receiving Notification of Documentation Updates 39

12 Mechanical, Packaging, and Orderable

4 Revision History

March 2020 * Advance Information release.

ADVANCE□INFORMATION CDC AGND SCL VIN EN/UVLO FSW BOOT1 SW2 DR1H FB/INT ILIM MODE DR1L BOOT2 VOUT VCC COMP PGND ISP SW1 SDA ISNDITH/SYNC SW2 PGND VOUT TPS55288 www.ti.com SLVSF01 –MARCH 2020 Product Folder Links: TPS55288 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

5 Pin Configuration and Functions

NO. NAME 1 DR1L O Gate driver output for low-side MOSFET in buck side. 2 DR1H O Gate driver output for high-side MOSFET in buck side. 3 VIN PWR Power supply to the IC from input voltage.

4 EN/UVLO I

Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at EN/UVLO pin is above the logic high voltage of 1.1 V, this pin acts as programmable UVLO input with 1.23 V internal reference. 5 SCL I Clock of I2C interface. 6 SDA I/O Data of I2C interface.

7 DITH/SYNC I

Dithering frequency and synchronous clock input. Use a capacitor between this pin and ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is no dithering function. An external clock can be applied at this pin to synchronize the switching frequency. 8 FSW I The switching frequency is programmed by a resister between this pin and the AGND pin. 9, 24 PGND PWR Power ground of the IC. It is connected to the source of the low-side MOSFET. 10 AGND PWR Signal ground of the IC. 11, 26 VOUT PWR Output of the buck-boost converter.

12 ISP I

Positive input of the current sense amplifier. An optional current sense resistor connected between ISP pin and ISN pin can limit the average output current. If the sensed voltage reaches 50 mV (or current limit setting value in the register), a slow constant current control loop becomes active and starts to regulate the drop voltage across ISP and ISN pin to 50 mV. Short the ISP and ISN together to disable this feature.

13 ISN I

Negative input of the current sense amplifier. An optional current sense resistor connected between ISP pin and ISN pin can limit the average output current. If the sensed voltage reaches 50 mV (or current limit setting value in the register), a slow constant current control loop becomes active and starts to regulate the drop voltage across ISP and ISN pin to 50 mV. Short the ISP and ISN together to disable this feature.

14 FB/INT I/O

When configured as an output voltage feedback, connect to the center tape of a resistor divider to program the output voltage. When the device is set to use internal feedback, this pin is a fault indicator output. When there is internal fault happening, this pin outputs logic low level.

15 MODE I

Setting the operation modes of the TPS55288 to select PFM mode or forced PWM mode in light load condition, to select the internal LDO or external 5 V for VCC, and to select different I2C address by a resistor between this pin and AGND.

16 CDC O

Voltage output in proportional to the sensed voltage between ISP pin and ISN pin. Use a resistor between this pin and AGND to increase the output voltage to compensate voltage droop across the cable caused by the cable resistance. 17 ILIM O Adjustable switch peak current limit. Connect an external resister between this pin and the AGND pin. 18 COMP I Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin. 19 VCC O Output of the internal regulator. A ceramic capacitor of more than 4.7 uF is required between this pin and AGND. 20 BOOT2 O Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be connected between this pin and the SW2 pin. 21, 25 SW2 I The switching node pin of the boost side. It is connected to the drain of the internal low-side power MOSFET and the source of internal high-side power MOSFET. 22 BOOT1 I Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be connected between this pin and the SW1 pin. 23 SW1 I The switching node pin of the buck side. It is connected to the drain of the external low-side power MOSFET and the source of external high-side power MOSFET.

ADVANCE□INFORMATION TPS55288 www.ti.com SLVSF01 –MARCH 2020 Product Folder Links: TPS55288 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage range at terminals (2) VIN, SW1 –0.3 40 V DRH1, BOOT1 SW1–0.3 SW1+6 V VCC, DRL1, SCL, SDA, ILIM, FSW, COMP, FB/INT, MODE, CDC, DITH/SYNC –0.3 6 V VOUT, SW2, ISP, ISN –0.3 25 V ISP, ISN VOUT-6 VOUT+6 V EN -0.3 20 V BOOT2 SW2–0.3 SW2+6 V DRL1, SCL, SDA, ILIM, FSW, COMP, FB/INT, MODE, CDC, DITH/SYNC –0.3 VCC+0.3 V TJ Operating Junction, TJ –40 150 °C Tstg Storage temperature –65 150 °C

6.2 Handling Ratings

V(ESD) (1) Electrostatic discharge Human body model (HBM) ESD stress voltage(2) ±2000 VCharged device model (CDM) ESD stress voltage(3) ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage range 2.7 36 V VOUT Output voltage range 0.8 22 V L Effective inductance range 1 4.7 10 µH CIN Effective input capacitance range 4.7 22 µF COUT Effective output capacitance range 10 100 1000 µF TJ Operating junction temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPS55288 UNITVQFN-HR (RPM)

26 PINS

RθJA Junction-to-ambient thermal resistance 47.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 23.8 °C/W RθJB Junction-to-board thermal resistance 12.8 °C/W ΨJT Junction-to-top characterization parameter 0.5 °C/W YJB Junction-to-board characterization parameter 12.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.8 °C/W RθJA(EVM) Junction-to-ambient thermal resistance on EVM 35.2 °C/W

6.5 Electrical Characteristics

TJ = -40°C to 125°C, VIN = 8 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VIN Input voltage range 2.7 36 V VVIN_UVLO Under voltage lockout threshold VIN rising 2.8 2.9 3.0 V VIN falling 2.6 2.65 2.7 V IQ Quiescent current into VIN pin IC enabled, no load, no switching. VIN = 2.9V to 24V, VOUT = 0.8V, VFB = VREF + 0.1V, FSW=100kΩ, Tj up to 125°C 650 800 µA Quiescent current into VOUT pin IC enabled, no load, no switching, VIN = 2.9V, VOUT = 3V to 20V, VFB = VREF + 0.1V, FSW=100kΩ, Tj up to 125°C 650 800 µA ISD Shutdown current into VIN pin IC disabled, VIN = 2.9V to 14V, Tj up to 125°C 6.8 10 µA VCC Internal regulator output IVCC = 50mA, VIN = 8V, VOUT = 20V 5.0 5.2 5.4 V VCC_DO VCC dropout VIN = 5.0V, VOUT = 20V IVCC = 60mA 150 300 mV VIN = 14V, VOUT = 5.0V, IVCC = 60mA 75 150 mV EN/UVLO VEN_H EN Logic high threshold VCC = 2.7V to 5.5V 1.15 V VEN_L EN Logic low threshold VCC = 2.7V to 5.5V 0.4 V VEN_HYS Enable threshold hysteresis VCC = 2.7V to 5.5V 0.08 V VUVLO UVLO rising threshold at the EN/UVLO VUVLO_HYS UVLO threshold hysteresis VCC = 3.0V to 5.5V 8 12 18 mV IUVLO Sourcing current at the EN/UVLO pin VUVLO = 1.3V 4.7 5 5.3 µA OUTPUT VOUT Output voltage range 0.8 22 V VOVP Output overvoltage protection threshold 22.5 23.5 24.5 V VOVP_HYS Over voltage protection hysteresis 1 V IFB_LKG Leakage current at FB pin Tj up to 125°C 100 nA ISW_LKG Leakage current into SW pin IC disabled, Tj up to 125°C TBD µA IVOUT_LKG Leakage current into VOUT pin IC disabled, VOUT = 5V, VSW2 = 0V, Tj up to 125°C 1 TBD µA IVOUT_LKG Leakage current into VOUT pin IC disabled, VOUT = 20V, VSW2 = 0V, Tj up to 125°C 1 TBD µA IDISCHG Output discharge current VOUT = 20V, VCC = 5.2V 40 100 160 mA INTERNAL REFERENCE DAC Resolution of reference voltage DAC 10 bits INL Integral non-linearity –4 4 LSB DNL Differential non-linearity –1 2 LSB VOUT_FULL Internal feedback register set to 20V VOUT DAC=03C0H, VDAC=1.129V -1% 20 1% V Internal feedback register set to 15V VOUT DAC=03C0H, VDAC=1.129V -1% 15 1% V Internal feedback register set to 10V VOUT DAC=03C0H, VDAC=1.129V -1% 10 1% V Internal feedback register set to 5V VOUT DAC=03C0H, VDAC=1.129V -1% 5 1% V

ADVANCE□INFORMATION TPS55288 www.ti.com SLVSF01 –MARCH 2020 Product Folder Links: TPS55288 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = -40°C to 125°C, VIN = 8 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT_ZERO Internal feedback register set to 20V VOUT DAC=0000H, VDAC=45mV 0.78 0.8 0.82 V Internal feedback register set to 15V VOUT DAC=0000H, VDAC=45mV 0.58 0.6 0.62 V Internal feedback register set to 12V VOUT DAC=0000H, VDAC=45mV 0.38 0.4 0.42 V Internal feedback register set to 5V VOUT DAC=0000H, VDAC=45mV 0.18 0.2 0.22 V REFERENCE VOLTAGE VREF Reference voltage at the FB/INT pin when using external feedback External feedback with DAC=03C0H 1.117 1.129 1.141 V External feedback with DAC=02C6H 0.837 0.846 0.855 V External feedback with DAC=019AH 0.502 0.508 0.514 V External feedback with DAC=00D2H 0.276 0.282 0.288 V POWER SWITCH RDS(on) Low-side MOSFET on resistance on boost side VOUT = 20V, VCC=5.2V 7 mΩ High-side MOSFET on resistance on boost side VOUT = 20V, VCC=5.2V 7 mΩ INTERNAL CLOCK fSW Switching frequency RFSW =100k 180 200 220 kHz RFSW =9.09k 2000 2200 2400 kHz tOFF_min Min. off time Boost mode 90 120 ns tON_min Min. on-time Buck mode 90 120 ns VSW Voltage at FSW pin 1 V CURRENT LIMIT ILIM_AVG Average inductor current limit RILIM = 20kΩ, VIN = 8V, VOUT = 20V, FSW = 500kHz, FPWM 14 16.5 19 A RILIM = 20kΩ, VIN = 8V, VOUT = 20V, FSW = 500kHz, PFM 14 16.5 19 A RILIM = 60kΩ, VIN = 5V, VOUT = 14V, FSW = 2.2MHz, FPWM 4 5.5 A RILIM = 60kΩ, VIN = 5V, VOUT = 14V, FSW = 2.2MHz, PFM 4 5.5 A ILIM_PK Peak inductor current limit at high side RILIM = 20kΩ, VIN = 8V, VOUT = 20V, FSW = 500kHz, FPWM 1.5x ILIM_AVG A RILIM = 20kΩ, VIN = 8V, VOUT = 20V, FSW = 500kHz. PFM 1.5x ILIM_AVG A VILIM Voltage at ILIM pin VOUT = 3V 0.6 V VSNS Current loop regulation voltage between ISP and ISN pin VISN = 2V to 21V 48.5 50 51.5 mV VISN = 2V to 21V 29 30 31 mV CABLE VOLTAGE DROP COMPENSATION VCDC Voltage at the CDC pin RCDC = 20kΩ or floating, VISP – VISN = 50mV 0.97 1 1.03 V RCDC = 20kΩ or floating, VISP – VISN = 2mV 10 40 70 mV

ADVANCE□INFORMATION TPS55288 SLVSF01 –MARCH 2020 www.ti.com Product Folder Links: TPS55288 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = -40°C to 125°C, VIN = 8 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT_CDC VOUT increase for cable drop compensation Internal output feedback, CDC[2:0]=111, VISP – VISN = 50mV 650 700 750 mV Internal output feedback, CDC[2:0]=111, VISP – VISN = 2mV 0 30 60 mV Internal output feedback, CDC[2:0]=001, VISP – VISN = 50mV 70 100 130 mV Internal output feedback, CDC[2:0]=001,, VISP – VISN = 10mV 0 20 40 mV IFB_CDC FB/INT pin sinking current External output feedback, RCDC = 20kΩ, VISP – VISN = 50mV 7.23 7.5 7.87 µA External output feedback, RCDC = 20kΩ, VISP – VISN = 0mV 0 0 0.1 µA External output feedback, RCDC = floating, VISP – VISN = 50mV 0 0 0.1 µA ERROR AMPLIFIER ISINK COMP pin sink current VFB = VREF + 400mV, VCOMP=1.5V, VCC=5V 20 µA ISOURCE COMP pin source current VFB = VREF - 400mV, VCOMP=1.5V, VCC=5V 60 µA VCCLPH High clamp voltage at the COMP pin 1.2 V VCCLPL Low clamp voltage at the COMP pin 0.6 V GEA Error amplifier transconductance 190 µA/V SOFT START tSS Soft-start time 3 4 5 ms DR1H GATE DRIVER VDR1H_L Low-state voltage drop VDR1H – VSW1, 100-mA sinking 0.07 V VDR1H_H High-state voltage drop VBOOT1 – VDR1H, 100-mA sourcing 0.18 V IDR1H_Source Peak sourcing current 1.0 A IDR1H_Sink Peak sinking current 1.8 A DR1L GATE DRIVER VDR1L_L Low-state voltage drop 100-mA sinking 0.05 V VDR1L_H High-state voltage drop VCC – VDR1L, 100-mA sourcing 0.18 V IDR1L_Source Peak sourcing current 1.0 A IDR1L_Sink Peak sinking current 1.8 A SPREAD SPECTRUM IDITH_CHG Dithering charge current VDITH/SYNC = 1.0V; RFSW=49.9kΩ; voltage rising from 0.85V 2 µA IDITH_DIS Dithering discharge current VDITH/SYNC = 1.0V; RFSW=49.9kΩ; voltage falling from 1.15V 2 µA VDITH_H Dither high threshold 1.1 V VDITH_L Dither low threshold 0.9 V SYNCHRONOUS CLOCK VSNYC_H Sync clock high voltage threshold 1.2 V VSYNC_L Sync clock low voltage threshold 0.4 V tSYNC_MIN Minimum sync clock pulse width 50 ns HICCUP tHICCUP Hiccup off time 78 ms MODE RESISTANCE DETECTION IMODE Sourcing current from MODE pin VMODE = 2.5V 9 10 11 µA

6.6 I2C Timing Characteristics

TJ = -40°C to 125°C, VIN = 5 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C TIMING fSCL SCL clock frequency 100 1000 kHz tBUF Bus free time between a STOP and START condition Fast mode plus 0.5 µs tHD(STA) Hold time (repeated) START condition 260 ns tLOW Low period of the SCL clock 0.5 µs tHIGH High period of the SCL clock 260 ns tSU(STA) Setup time for a repeated START condition 260 ns tSU(DAT) Data setup time 50 ns tHD(DAT) Data hold time 0 µs tRCL Rise time of SCL signal 120 ns tRCL1 Rise time of SCL signal after a repeated START condition and after an ACK bit 120 ns tFCL Fall time of SCL signal 120 ns tRDA Rise time of SDA signal 120 ns tFDA Fall time of SDA signal 120 ns tSU(STO) Setup time of STOP condition 260 ns CB Capacitive load for SDA and SCL 200 pF

7 Detailed Description

7.1 Overview

The TPS55288 is a 16-A buck-boost DC-to-DC converter with integrated two MOSFETs of the boost leg. The TPS55288 can operate over a wide range of 2.7 V to 36 V input voltage and an output voltage of 0.8 V to 21.26 V. It can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage and setting output. The TPS55288 operates in the buck mode when the input voltage is greater than the output voltage and in the boost mode when the input voltage is less than the output voltage. When the input voltage is close to the output voltage, the TPS55288 operates in one-cycle buck and one-cycle boost mode alternately. The TPS55288 uses an average current mode control scheme. Current mode control provides simplified loop compensation, rapid response to the load transients and inherent line voltage rejection. An error amplifier compares the feedback voltage of the output voltage with the internal reference voltage. The output of the error amplifier determines the average inductor current. An internal oscillator can be configured to operate over a wide range of frequency from 200 kHz to 2.4 MHz. The internal oscillator can also synchronize to an external clock applied to the DITH/SYNC pin. To minimize EMI, the TPS55288 can dither the switching frequency ranging at ±10% of the setting frequency. The TPS55288 works in fixed-frequency PWM mode at moderate to heavy load currents. In the light load condition, the TPS55288 can be configured to automatically transition to PFM mode or be forced in PWM mode by either connecting a resistor at the MODE pin or setting the corresponding bit in an internal register. User can adjust the output voltage of the device by setting the internal register through I2C interface. An internal 10-bit DAC adjusts the reference voltage related to the value writing into the DAC register. The device can also limit the output current by placing a current sense resistor in the output path. These two functions support the programmable power supply (PPS) feature of the USB-PD. The TPS55288 provides average inductor current limit set by a resistor at the ILIM pin. In addition, it provides cycle-by-cycle peak inductor current limit during transient to protect the device against the current condition beyond the capability of the device. A precision voltage threshold of 1.23 V with 5-µA sourcing current at the EN/UVLO pin supports programmable input undervoltage lockout (UVLO) with hysteresis. The output over-voltage protection (OVP) feature turns off the high-side FETs to prevent damage to the devices powered by the TPS55288. The device provides hiccup mode option to reduce the heating in the power components when the output short circuit happens. When the hiccup mode is enabled, the TPS55288 turns off for 78 ms and restarts at soft start- up.

ADVANCE□INFORMATION SW2 ILIM VIN UVLO VOUT Gm BOOT2 DL VOUT FSW I_limit Vref Vref LDO VIN Current Sense CDC ISP ISN Iref Buck-Boost Control SW1 I_limit VCC PGND Logic Core SDA SCL EN/UVLO 1.0V VOUT OVP Thermal VIN VOUT SYNC/DITH fMOD VSYNC/DITH VCC IrefDAC DAC COMP DH ADC MODE VIN AGND I-V BOOT1 VOUT FB/INTGm BUCK BOOST TPS55288 www.ti.com SLVSF01 –MARCH 2020 Product Folder Links: TPS55288 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 VCC Power Supply

An internal LDO to supply the TPS55288 outputs regulated voltage at 5.2 V at VCC pin with 60-mA output current capability. When VIN is higher than VOUT and VOUT is less than 5.9 V, or when VIN is less than VOUT and VIN is higher than 6.2 V, the internal LDO is powered from VIN. When VIN is higher than VOUT and VOUT is higher than 6.2 V, or when VIN is less than VOUT and VIN is lower than 5.9 V, the internal LDO is powered from VOUT. To minimize the power dissipation of the internal LDO when both input voltage and output voltage are high, an external 5-V power source can be applied at the VCC pin to supply the TPS55288. The external 5-V power supply must have at least 200-mA output current capability and must be within 5 V±5% regulation range. To use an external power supply for VCC, a proper resistance must be connected to the MODE pin.

7.3.2 Operation Mode Setting

By placing different resistors between the MODE pin and the AGND pin, the TPS55288 selects the internal power supply or external power supply for VCC, selects one of two different I2C addresses, selects the PFM mode or forced PWM mode in light load conditions. Table 1 shows the resistance values for each selection. After the TPS55288 is enabled, an I2C master device can control these three operating modes by writing the corresponding value into the internal registers regardless the resistance settings at the MODE pin. See details in Register Maps.

Table 1. VCC Source, I2C Slave Address and PFM/PWM Programming

0 Internal 74H PWM

6.19 Internal 74H PFM

14.3 Internal 75H PWM

24.9 Internal 75H PFM

51.1 External 74H PWM

75.0 External 74H PFM

105 External 75H PWM

7.3.3 Input Undervoltage Lockout

TPS55288 can be enabled by pulling the EN pin to a high voltage above 1.3 V.

7.3.4 Enable and Programmable UVLO

supply for VCC, the I2C slave address, and the PFM or FPWM mode for light load condition accordingly. By using resistor divider as shown in Figure 1, the turnon threshold is calculated using Equation 1.

VUVLO is the UVLO threshold of 1.23 V at the EN/UVLO pin (1) The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by the Equation 2 where
IUVLO_HYS is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above VUVLO (2)

Figure 1. Programmable UVLO With Resistor Divider at EN/UVLO pin Figure 2. Logic Enable and Programmable UVLO

7.3.5 Soft Start

7.3.6 Shutdown and Load Discharge

disabled. All internal registers are reset to default values. discharges the output voltage below 0.8 V by an internal constant current.

7.3.7 Switching Frequency

resistance by a given switching frequency.

RFSW is the resistance at the FSW pin (3) For noise sensitive applications, the TPS55288 can be synchronized to an external clock signal applied to the DITH/SYNC pin. The duty cycle of the external clock is recommended in the range of 30% to 70%. The resistor also must be connected to the FSW pin when the TPS55288 is switching by the external clock. The external clock frequency at the DITH/SYNC pin must have lower than 0.4-V low level voltage and must be within ±30% of the corresponding frequency set by the resistor. Figure 3 is a recommended configuration.

Figure 3. External Clock Configuration

7.3.8 Switching Frequency Dithering

normally is below 1 kHz. Equation 4 calculates the capacitance required to set the modulation frequency, FMOD.

RFSW is the switching frequency setting resistance (Ω) at the FSW pin
FMOD is the modulation frequency (Hz) of the dithering (4) Connecting the DITH/SYNC pin below 0.4 V or above 1.2 V disables switching frequency dithering. The dithering function also is disabled when an external synchronous clock is used.

Figure 4. Switching Frequency Dithering

7.3.9 Inductor Current Limit

desired average inductor current limit.

IAVG_LIMITis the average inductor current limit
RILIMis the resistance (Ω) between the ILIM pin and analog ground (5) Besides the average current limit, a peak current limit protection is implemented during transient to protect the device against over current condition beyond the capability of the device.

7.3.10 Internal Charge Path

the TPS55288 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is constantly on. bootstrap capacitor to VCC so that the high-side MOSFET remains on.

7.3.11 Output Voltage Setting

There are two ways to set the output voltage, changing the feedback ratio and changing the reference voltage. to 1, the output voltage feedback ratio is set by an external resistor divider. mV, 15 mV, 10 mV and 5 mV, accordingly. the output voltage with the reference voltage at the FB/INT pin.

Figure 5. Output Voltage Setting by External Resistor Divider programmable from 45 mV to 1.2 V by writing a 10-bit data into the register 00H and 01H.

7.3.12 Output Current Indication and Cable Voltage Drop Compensation

compensation setting by placing a resistor at the CDC pin. voltage. Write the value into the bit CDC [2:0] in the register 05H can get the desired voltage compensation. resistor at the CDC pin. It is recommended to use 100-kΩ resistance for the up resistor of the resistor divider. resistor of the output voltage feedback resistor divider.

RFB_UP is the up resistor of the resistor divider between the output and the FB/INT pin
RCDC is the resistor at the CDC pin (8) When RFB_UP is 100 kΩ, the output voltage rise versus the sensed output current and the resistor at the CDC pin is shown in Figure 6

Figure 6. Output Voltage Rise vs Output Current

7.3.13 Integrated Gate Drivers

the DR1L remains continuously low voltage to turn off the low side MOSFET of the buck side. In DCM buck mode operation, the DR1L turns off when the inductor current drops to zero. CBOOT1, which is between the BOOT1 pin and SW1 pin.

7.3.14 Output Current Limit

voltage step between the ISP pin and ISN pin is 0.5 mV. Connecting the ISP pin and ISN pin together disables the current limit function.

7.3.15 Overvoltage Protection

circuits connected to the output from excessive overvoltage.

7.3.16 Output Short Circuit Protection

restarts the soft-start repeatedly. The hiccup mode helps to reduce the total power dissipation on the TPS55288.

7.3.17 Thermal Shutdown

temperature drops below the thermal shutdown hysteresis of 20°C below the thermal shutdown threshold.

7.4 Device Functional Modes

In light load condition, the TPS55288 can work in PFM or forced PWM mode to meet different application requirements. The PFM mode decreases switching frequency to reduce the switching loss thus it gets high efficiency at light load condition. The FPWM mode keeps the switching frequency unchanged to avoid undesired low switching frequency but the efficiency becomes lower than that of PFM mode.

7.4.1 PWM Mode

In FPWM mode, the TPS55288 keeps the switching frequency unchanged in light load condition. When the load current decreases, the output of the internal error amplifier decreases as well to make the average inductor current down so as to deliver less power from input to output. When the output current further reduces, the current through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned off even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to zero. The power follow is from output side to input side. The efficiency is low in this condition. However, with the fixed switching frequency, there is no audible noise or other problems that might be caused by low switching frequency in light load condition.

7.4.2 Power Save Mode

The TPS55288 improves the efficiency at light load condition with the PFM mode. By connecting an appropriate resistor at the MODE pin or enabling the PFM function in the internal register, the TPS55288 can work in PFM mode at light load condition. When the TPS55288 operates at light load condition, the output of the internal error amplifier decreases to make the inductor peak current down to deliver less power to the load. When the output current further reduces, the current through the inductor will decrease to zero during the switch-off time. When the TPS55288 works in buck mode, once the inductor current becomes zero, the low side switch of the buck side is turned off to prevent the reverse current from output to ground. When the TPS55288 works in boot mode, once the inductor current becomes zero, the high side switch of the boost side is turned off to prevent the reverse current from output to input. The TPS55288 resume switching until the output voltage drops. Thus the PFM mode reduces switching cycles and eliminates the power loss by the reverse inductor current to get high efficiency at the light load conditions.

7.5 I2C Serial Interface

The TPS55288 uses I2C interface for flexible converter parameter programming. I2C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). I2C devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered as a slave. The TPS55288 operates as a slave device with address 74H and 75H set by different resistor at the MODE pin. Receiving control inputs from the master device like a micro controller or a digital signal processor reads and writes the internal registers 00H through 07H. The I2C interface of the TPS55288 supports both standard mode (up to 100 kbit/s) and fast mode plus (up to 1000 kbit/s). Both SDA and SCL must be connected to the positive supply voltage via current sources or pull-up resistors. When the bus is free, both lines are in high voltage.

7.5.1 Data Validity

The data on the SDA line must be stable during the high level period of the clock. The high level or low level state of the data line can only change when the clock signal on the SCL line is low level. One clock pulse is generated for each data bit transferred.

Figure 7. I2C Data Validity

7.5.2 START and STOP Conditions

SDA line when the SCL is at high level defines a STOP condition. condition, and free after the STOP condition. Figure 8. I2C START and STOP Conditions

7.5.3 Byte Format

then continues when the slave is ready for another byte of data and release the clock line SCL. Figure 9. Byte Format

7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)

acknowledge 9th clock pulse, are generated by the master. to low level and it remains stable low level during the high level period of this clock pulse. then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

7.5.5 Slave Address and Data Direction Bit

bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). Figure 10. Slave Address and Data Direction

7.5.6 Single Read and Write

Figure 11. Single-byte Write Figure 12. Single-byte Read If the register address is not defined, the TPS55288 sends back NACK and goes back to the idle state.

7.5.7 Multi-Read and Multi-Write

Figure 13. Multi-byte Write Figure 14. Multi-byte Read The TPS55288 supports multi-read and multi-write.

7.6 Register Maps

Table 2 should be considered as reserved locations, and the register contents should not be modified. Table 2. Device Registers access types in this section. Table 3. Device Access Type Codes

7.6.1 REF Register (Address = 0h, 1h) [reset = 11010010h, 00000000h]

REF is shown in Figure 15 and Figure 16 described in Table 4. reference voltage is 45mV. When the register value is 00000011 11000000B, the reference voltage is 1.129V. or set by an external resistor divider.. Figure 15. REF_LSB Figure 16. REF_MSB Table 4. REF Register Field Descriptions

7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]

IOUT_LIMIT is shown in Figure 17 and described in Table 5. Figure 17. IOUT_LIMIT Register Table 5. IOUT_LIMIT Register Field Descriptions 7 Current_Limit_EN R/W 1b Enable of disable current limit.

7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]

VOUT_SR is shown in Figure 18 and described in Table 6. exceeds the setting output current limit. so that the TPS55288 immediately limits the output current. The SR [1:0] bits set 2.5mV/us, 5mV/us, 10mV/us and 20mV/us slew rate for output voltage change. Figure 18. VOUT_SR Register Table 6. VOUT_SR Register Field Descriptions 1-0 SR R/W 01b Sets slew rate for output voltage change.

7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]

VOUT_FS is shown in Figure 19 and described in Table 7. voltage between the ISP pin and ISN pin. Figure 19. VOUT_FS Register Table 7. VOUT_FS Register Field Descriptions 7 FB R/W 0b Output feedback voltage. 1-0 INTFB R/W 11b Internal feedback ratio. Table 8. Output Voltage VS Internal Reference

7.6.5 CDC Register (Address = 5h) [reset = 11100000h]

CDC is shown in Figure 20 and described in Table 9. between the ISP pin and ISN pin. Figure 20. CDC Register Table 9. CDC Register Field Descriptions 7 SC_MASK R/W 1b Short circuit mask. 6 OCP_MASK R/W 1b Over current mask. 5 OVP_MASK R/W 1b Over voltage mask.

4 RESERVED R/W 0b Reserved

7.6.6 MODE Register (Address = 6h) [reset = 00110000h]

MODE is shown in Figure 21 and described in Table 10. MODE controls the operating mode of the TPS55288. Figure 21. MODE Register Table 10. MODE Register Field Descriptions 6 FSW R/W 0b Switching frequency. 5 HICCUP R/W 1b Hiccup mode. 0b = Disable the hiccup during output short circuit protection. 4 DISCHG R/W 1b Output discharge. 2 I2CADD R/W 0b I2C address.

7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]

STATUS is shown in Figure 22 and described in Table 11. corresponding bit is set again. Figure 22. STATUS Register Table 11. STATUS Register Field Descriptions 7 SCP R 0b Short circuit protection. 6 OCP R 0b Over current protection. 5 OVP R 0b Over voltage protection.

4 RESERVED R 0b Reserved

3 RESERVED R 0b Reserved

2 RESERVED R 0b Reserved

1-0 STATUS R 11b Operating status.

7.6.8 Register Summary

The below summarizes the default settings of the registers in the TPS55288. Table 12. Default Settings of Registers

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

recommended to set the lower switch current limit for good thermal performance.

8.2 Typical Application

Figure 23. USB-PD Power Supply With 4.5-V to 14-V Input Voltage

8.2.1 Design Requirements

Table 13. Design Parameters

8.2.2 USB-PD Power Supply Detailed Design Procedure

8.2.2.1 Switching Frequency

1% standard resistor of 50 kΩ is selected for 400 kHz switching frequency for this application.

8.2.2.2 Output Voltage Setting

desired output voltage by writing the proper data into the reference voltage registers through I2C bus.

8.2.2.3 Inductor Selection

specifications, inductance, saturation current, and DC resistance. based on consideration of both buck and boost modes of operation. inductance and the inductor ripple current.

VIN(MAX) is the maximum input voltage
VOUT is the output voltage
ΔIL(P-P) is the peak to peak ripple current of the inductor
fSW is the switching frequency (9) For a certain inductor, the inductor ripple current achieves maximum value when VOUT equals to half of the maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller inductance gets larger inductor current ripple. For the boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum inductor current at the maximum output voltage. In CCM, the Equation 10 shows the relationship between the inductance and the inductor ripple current. where
VIN is the input voltage
VOUT(MAX) is the maximum output voltage
ΔIL(P-P) is the peak to peak ripple current of the inductor
fSW is the switching frequency (10)

ADVANCE□INFORMATION IL(P) = IL(DC)+ ¨IL(P-P) ¨IL(P-P)=VIN×:VOUT-VIN; L×fSW×VOUT IL(DC) = VOUT×IOUT VIN× TPS55288 SLVSF01 –MARCH 2020 www.ti.com Product Folder Links: TPS55288 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated For a certain inductor, the inductor ripple current achieves maximum value when VIN equals to the half of the maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller inductance gets larger inductor current ripple. For this application example, a 4.7-µH inductor is selected, which produces approximate maximum inductor current ripple of 60% of the highest average inductor current in buck mode and 45% of the highest average inductor current in boost mode. In buck mode, the inductor DC current equals to the output current. In the boost mode, the inductor DC current can be calculated with the Equation 11. where

VOUT is the output voltage
IOUT is the output current
VIN is the input voltage
η is the power conversion efficiency (11) For a given maximum output current of the buck-boost converter TPS55288, the maximum inductor DC current happens at the minimum input voltage and maximum output voltage. Set the inductor current limit of the TPS55288 higher than the calculated maximum inductor DC current to make sure the TPS55288 has the desired output current capability. In boost mode, the inductor ripple current is calculated with the Equation 12 where
ΔIL(P-P) is the inductor ripple current
L is the inductor value
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage (12) Therefore, the inductor peak current is calculated with the Equation 13 (13) Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. The selected inductor must have higher saturation current than the calculated peak current. The conversion efficiency is dependent on the resistance of its current path, the switching loss associated with the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the inductor DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss. Table 14 lists recommended inductors for the TPS55288. In this application example, the Coilcraft inductor XAL1060-472 is selected for its small size, high saturation current and small DCR.

Table 14. Recommended Inductors(1)

8.2.2.4 Input Capacitor

ICIN(RMS) is the RMS current through the input capacitor
IOUT is the output current
D is the switching duty cycle (14) The maximum RMS current occurs at VOUT is half of the input voltage, which gives ICIN(RMS) = IOUT / 2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. Total 20-µF effective capacitance is a good starting point for this application.

8.2.2.5 Output Capacitor

the minimum VIN and maximum VOUT correspond to the maximum capacitor current (15) In this example, the maximum output ripple RMS current is 6 A. The ESR of the output capacitor causes an output voltage ripple given by the Equation 16 in boost mode. where
RCOUT is the ESR of the output capacitance (16) The capacitance also causes a capacitive output voltage ripple given by the Equation 17 in boost mode. When input voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest output voltage ripple caused by the capacitance. (17) Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR, high ripple current and small output voltage ripple. From the required output voltage ripple, use Equation 16 and Equation 17 to calculate the minimum required effective capacitance of the COUT.

ADVANCE□INFORMATION GC(s) = GEA×REA×VREF VOUT l1+ s 2N×fCOMZ p l1+ s 2N×fCOMP1 p × l1 + s 2N×fCOMP2 p fRHPZ = ROUT×:1-D;2 2N×L fESRZ = 1 2N×RCOUT×COUT fP = 2 2N×RLOAD×COUT GPS(s) = RLOAD×:1-D; 2×RSENSE l1+ s 2N×fESRZ p× l1- s 2N×fRHPZ p 1+ s 2N×fP RSNS = VSNS IOUT_LIMIT TPS55288 SLVSF01 –MARCH 2020 www.ti.com Product Folder Links: TPS55288 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

8.2.2.6 Output Current Limit Sense Resistor

The output current limit is implemented by putting a current sense resistor between the ISP and ISN pins along with setting a limit voltage between the ISP pin and ISN pin through the register 02H. The maximum value of the limit voltage between the ISP and ISN pins is 63.5 mV. The default limit voltage is 50 mV. The current sense resistor between the ISP and ISN pins should be selected to ensure that the output current limit is set high enough for output. The output current limit setting resistor is given by the Equation 18 where

VSNS is the current limit setting voltage between the ISP and ISN pin
IOUT_LIMIT is the desired output current limit (18) Because the power dissipation is large, make sure the current sense resistor has enough power dissipation capability with large package.

8.2.2.7 Loop Stability

The TPS55288 uses average current control scheme and requires external compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation network comprised of resistor and ceramic capacitors is connected to the COMP pin. The TPS55288 operates in buck mode or boost mode. Therefore both buck and boost operating modes require loop compensations. The restrictive one of both compensations is selected as the overall compensation from a loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ). The power stage in boost mode can be modeled by the Equation 18. where

RLOAD is the output load resistance
D is the switching duty cycle in boost mode
RSENSE is the equivalent internal current sense resistor, which is TBD Ω (19) The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use Equation 20 to Equation 22 to calculated them (20) (21) (22) The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the control portion of the loop. The transfer function of the control portion is shown by the Equation 23 where
GEA is the transconductance of the error amplifier
REA is the output resistance of the error amplifier
VREF is the reference voltage input to the error amplifier

VOUT is the output voltage
fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network
fCOMZ is the zero’s frequency of the compensation network (23) The total open-loop gain is the product of GPS(s) and GC(s). The next step is to choose the loop crossover frequency, fC, at which the total open-loop gain is zero. The higher in frequency that the loop gain stays above zero before crossing over, the faster the loop response. It is generally accepted that the loop gain cross over zero at the frequency no higher than the lower of either 1/10 of the switching frequency, fSW or 1/5 of the RHPZ frequency, fRHPZ. Then set the value of RC, CC and CP by Equation 24 to Equation 26. where
fC is the selected crossover frequency (24) (25) (26) If the calculated CP is less than 10 pF, it can be left open. Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.

8.2.3 Application Curves

Figure 24. Figure 25.

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V to 36 V. This input supply must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum electrolytic capacitor with a value of 100 μF.

10 Layout

10.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents, layout is an important design step. If layout is not carefully done, the regulator could suffer from instability and noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation of high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW1 and SW2 pins, and always use a ground plane under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN pin and PGND pin in order to reduce the input supply current ripple. The most critical current path for buck converter portion is from the switching FET, through the rectifier FET at the buck side to the PGND, then the input capacitors, and back to the input of the switching FET. This high current path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the input capacitor for power stage must be close to the input of the switching FET and the PGND terminal of the rectifier FET. The most critical current path for boost converter portion is from the switching FET, through the rectifier FET, then the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the output capacitor needs not only to be close to the VOUT pin, but also to the PGND pin to reduce the overshoot at the SW2 pin and VOUT pin. The traces from the output current sensing resistor to the ISP pin and ISN pin must be in parallel and close to each other to avoid noise coupling. The PGND plane and AGND plane are connected at the terminal of the capacitor at the VCC pin. Thus the noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal control circuit. To get good thermal performance, it is recommended to use thermal vias beneath the TPS55288 connecting PGND pin and VOUT pin to the PGND plane and a large VOUT area separately.

10.2 Layout Example

Figure 26. Layout Example

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

11.3.1 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws.

11.4 Trademarks

Hotrod is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4224618/A 10/2018 www.ti.com VQFN-HR - 1 mm max height PLASTIC QUAD FLATPACK-NO LEAD RPM0026A A 0.08 C B PKG PKG PIN 1 INDEX AREA 4.1 3.9 3.6 3.4 1.0 0.8 0.05 0.00 SEATING PLANE C (0.1) TYP

0.1 C A B

0.05 C 6X 0.525±0.1 6X 0.4±0.1 6X 0.25±0.05 6X 0.25±0.05 5X 0.25±0.05 0.425±0.1 2X 0.475±0.1 2X 0.25±0.05 3X 0.375±0.05 1.425±0.1 0.05 C 0.05 C 0.05 C 2X 0.35±0.05 0.05 C 2X 0.4±0.05 2X (0.175 X 0.150) TYP 0.05 C 2X (0.150 X 0.150) TYP 2X 0.225±0.05 2X 0.225±0.05 2X 1.6752X 1.1252X 0.6250.125 2X 1.4875 2X 1.625 2X 1.4875 2X 1.05 2X 0.252X 0.625 2X 1 2X 0.5 7 13 24 25 26 tI ADVANCE□INFORMATION TPS55288 www.ti.com SLVSF01 –MARCH 2020 Product Folder Links: TPS55288 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

13.1 Package Outline

ADVANCE□INFORMATION NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . EXAMPLE BOARD LAYOUT 4224618/A 10/2018 www.ti.com VQFN-HR - 1 mm max heightRPM0026A PLASTIC QUAD FLATPACK-NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAIL NON SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING

0.05 MAX

6X (0.725) 6X (0.6) 6X (0.25) 6X (0.25) 5X (0.25) 5X (0.625) 2X (0.675) 2X (0.25) 3X (0.375) 3X (1.425) 2X (0.35) 2X (0.4) 2X (0.225) 2X (0.225) (1.675) (1.125) (0.625)0.125 2X (1.4875) 2X (1.625) 2X (1.4875) 2X (1) 2X (0.5) 24 25 26 2X (1.9) (R0.05) TYP (3.675) (3.8) (1.65) (1.6125) (1.6375) tI TPS55288 SLVSF01 –MARCH 2020 www.ti.com Product Folder Links: TPS55288 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

13.2 Land Pattern

ADVANCE□INFORMATION NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224618/A 10/2018 www.ti.com VQFN-HR - 1 mm max heightRPM0026A PLASTIC QUAD FLATPACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 20X PKG PKG 6X (0.725) 6X (0.6) 6X (0.25) 6X (0.25) 5X (0.25) 5X (0.625) 2X (0.675) 2X (0.25) 3X (0.375) 3X (1.425) 2X (0.35) 2X (0.4) 2X (0.225) 2X (0.225) (1.675) (1.125) (0.625)0.125 2X (1.4875) 2X (1.625) 2X (1.4875) 2X (1) 2X (0.5) 24 25 26 (R0.05) TYP (3.675) (3.8) (1.65) (1.6125) (1.6375) tI TPS55288 www.ti.com SLVSF01 –MARCH 2020 Product Folder Links: TPS55288 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

13.3 Solder Paste

www.ti.com 17-Mar-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS55288RPMR ACTIVE VQFN-HR RPM 26 3000 TBD Call TI Call TI -40 to 150 TPS55288RPMR PREVIEW VQFN-HR RPM 26 3000 TBD Call TI Call TI -40 to 150 TPS55288RPMT PREVIEW VQFN-HR RPM 26 250 TBD Call TI Call TI -40 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated

Product Information

125CDMCCDS-4R7MC specifications and overview.

Summary

TPS55288 36-V, 16-A Buck-boost Converter with I2C Interface

Description

TPS55288 36-V, 16-A Buck-boost Converter with I2C Interface

Source title 125CDMCCDS-4R7MC Datasheet(PDF) - Texas Instruments

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