125932-HMC674LC3C

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9.3 GHz Latched Comparator

Data Sheet HMC674LC3C/HMC674LP3E Rev. K Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Equivalent input bandwidth: 9.3 GHz typical Propagation delay: 85 ps typical Overdrive and slew rate dispersion: 10 ps typical Input signal minimum pulse width: 60 ps typical Resistor programmable hysteresis Differential latch control Power dissipation: 140 mW typical 16-terminal, 3 mm × 3 mm, ceramic leadless chip carrier (LCC) 16-lead lead frame chip scale package (LFCSP)

APPLICATIONS

Automatic test equipment (ATE) applications High speed instrumentation Digital receiver systems Pulse spectroscopy High speed trigger circuits Clock and data restoration FUNCTIONAL BLOCK DIAGRAM 4 9 65 7 8 16 15 14 13 VTP 50Ω 50Ω INP INN VTN VCCO VEE HYS RTN VCCI Q Q VCCO VCCI LE LE NIC VEE PACKAGE BASE HMC674LC3C/HMC674LP3E 14861-001 Figure 1. HMC674LC3C/HMC674LP3E Functional Block Diagram

HMC674LC3C/HMC674LP3E Data Sheet Rev. K | Page 2 of 14 TABLE OF CONTENTS

REVISION HISTORY

Two Hittite Mircrowave product data sheets have been reformatted to the styles and standards of Analog Devices, Inc., and combined into one data sheet. 12/2016—v12.0616 (HMC674LC3C and HMC674LP3E) to Rev. K Changes to Title, Features Section, and General Description Changed Operational Description Section to Theory of

Data Sheet HMC674LC3C/HMC674LP3E Rev. K | Page 3 of 14 SPECIFICATIONS TA = 25°C, VCCI = 3.3 V , VCCO = 2.0 V , VEE = −3 V, VTT = 0 V , unless otherwise noted. Table 1. Parameter Min Typ Max Unit INPUT Voltage Range −2 +2 V Differential Voltage −1.75 +1.75 V Offset Voltage (VOS) ±5 mV Temperature Coefficient 15 µV/°C Bias Current 15 µA Temperature Coefficient 50 nA/°C Offset Current 4 µA Impedance 50 Ω Common-Mode 350 kΩ Differential 15 kΩ Active Gain 48 dB Common-Mode Rejection Ratio (CMRR) 80 dB Hysteresis, RHYS = Infinity ±1 mV LATCH ENABLE (LE/LE) SPECIFICATIONS Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LATCH ENABLE (LE/LE) Input Impedance 8 kΩ Each pin To Output Delay tPLOL, tPLOH 85 ps Input overdrive voltage (VOD) = 200 mV Minimum Pulse Width tPL 20 ps VOD = 200 mV Input Range 1.6 2.4 V VOD = 200 mV LATCH ENABLE (LE/LE) TIME Setup tS 45 ps VOD = 200 mV Hold tH −42 ps DC OUTPUT SPECIFICATIONS VCCO = 2.00 V , VTT = 0 V, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit OUTPUT VOLTAGE High Level VOH 1.03 1.09 1.14 V Low Level VOL 0.65 0.71 0.81 V Differential Swing 440 760 980 mV p-p

HMC674LC3C/HMC674LP3E Data Sheet Rev. K | Page 4 of 14 AC SPECIFICATIONS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments PROPAGATION DELAY (tPDL, tPD, tPDH) 80 85 110 ps VOD = 500 mV Temperature Coefficient 0.45 ps/°C Skew (Rising to Falling Transition) 10 ps VOD = 500 mV VOD 1 DISPERSION 10 ps 50 mV < VOD < 1 V PROPAGATION DELAY (tPD) vs. INPUT COMMON-MODE V O LTAGE (VCM) DISPERSION 8 ps VOD = 500 mV, NOISE (RETURN TO INPUT, RTI) 5.9 nV/√Hz EQUIVALENT INPUT BANDWIDTH (BWEQ)2 8.6 9.3 12 GHz JITTER 10 Gbps with ±100 mV overdrive Deterministic 2 ps p-p Random 0.2 ps rms INPUT SIGNAL MINIMUM PULSE WIDTH 60 ps VCM = 0 V, ±100 mV overdrive Q/Q TIME From 20% to 80% Rise 24 ps Fall 15 ps 1 VOD is the input overdrive voltage, for example, (VINP − VINN − VOS), where VOS is the input offset voltage.

2 Equivalent input bandwidth is calculated by

)( 22 EQ TRINTRCOMP BW −0.22/ = where: TRIN is the 20%/80% transition time of a quasi Gaussian signal applied to the comparator input. TRCOMP is the effective transition time digitized by the comparator. POWER SUPPLY SPECIFICATIONS Table 5. Parameter Symbol Min Typ Max Unit V O LTAGE Power Supply Voltage Input Stage VCCI 3.135 3.3 3.465 V Power Supply Voltage Output Stage VCCO 1.8 3.3 3.465 V Negative Power Supply (−3 V) VEE −3.15 −3.0 −2.85 V CURRENT Supply Input ICCI 9 mA Supply Output ICCO 45 mA VEE IEE 19 mA POWER DISSIPATION PD 140 mW POWER SUPPLY REJECTION RATIO PSRR VCCI 38 dB VEE 38 dB

(± the input offset voltage) to the 50% point of an output low to high transition. (± the input offset voltage) to the 50% point of an output high to low transition. signal high to low transition to the 50% point of an output low to high transition. signal high to low transition to the 50% point of an output high to low transition. that the input signal must remain unchanged to be acquired and held at the outputs. that an input signal change must be present to be acquired and held at the outputs. Input Overdrive Voltage VOD The difference between the input voltages (VINP and VINN). Figure 2. Timing Diagram

HMC674LC3C/HMC674LP3E Data Sheet Rev. K | Page 6 of 14 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating Supply Voltage Input (VCCI to GND) −0.5 V to +4 V Output (VCCO to GND) −0.5 V to +4 V Positive Differential (VCCI to VCCO) −0.5 V to +3.3 V VEE Supply to GND −3.3 V to +0.5 V Input Voltage −2 V to +2 V Differential −2 V to +2 V Latch Enable (LE/LE) −0.5 V to VCCI + 0.5 V Applied Voltage (HYS) VEE to GND Current Maximum Input ±20 mA Output 40 mA Continuous Power Dissipation (PDISS), TA = 85°C Derate 43.5 mW/°C Above 85°C (HMC674LP3E) 1.74 W Derate 20.4 mW/°C Above 85°C (HMC674LC3C) 0.816 W Junction Temperature 125°C Maximum Peak Reflow Temperature1 MSL1 and MSL3 260°C Thermal Resistance (θJC) HMC674LP3E 23°C/W HMC674LC3C 49°C/W Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C ESD Sensitivity, Human Body Model (HBM) Class 1A 1 See the Ordering Guide section. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

HMC674LC3C/HMC674LP3E Data Sheet Rev. K | Page 10 of 14 THEORY OF OPERATION The HMC674LC3C/HMC674LP3E are latched comparators with a 9.3 GHz equivalent input bandwidth. These devices are comprised of three blocks: an input amplifier, a latch, and an output buffer. The latching circuit is level sensitive and consists of a single, high speed latch. The HMC674LC3C/HMC674LP3E comparators support 10 Gbps operation. The input signal minimum pulse width is 60 ps. The HMC674LC3C/HMC674LP3E operate in either track (transparent) mode, where the output follows the logical value of the input, or latch (hold) mode, where the output value is held to the logical value of the comparison result of the input just prior to (LE − LE) going high. Select track mode operation by either setting (LE − LE) low or by floating the LE and LE inputs. Select latch mode by setting (LE − LE) high. The input impedance of the LE and LE inputs is 8 kΩ; however, these inputs can be terminated with 50 Ω external resistors, if desired. When the clock inputs are dc-coupled, they operate at an input common-mode voltage of 2 V . In this case, any termination resistors ideally return to 2 V . If the clock inputs are ac-coupled to the HMC674LC3C/HMC674LP3E, return the input termination resistors to ground. POWER SEQUENCING As long as the input signal is not near the −2 V extreme, either VCC or VEE can be powered on first. However, if the input voltage is more negative than −1.8 V , use the following power-up sequence: 1. VEE 2. VCCI and VCCO (if VCCO = VCCI) 3. VCCO (if different than ground) Note that the power-down sequence is the reverse of this sequence. It is recommended to power up the HMC674LC3C or the HMC674LP3E before applying the input signal and to remove the input signal prior to powering either down. These recommendations are important if any of the inputs are more negative than −1.8 V .

Data Sheet HMC674LC3C/HMC674LP3E Rev. K | Page 13 of 14 OUTLINE DIMENSIONS TOP VIEW SIDE VIEW SEATING PLANE

0.92 MAX

3.03 2.90 SQ 2.77 PIN 1 (0.32 × 0.32) EXPOSED PAD 0.36 0.30 0.24 1.60 1.50 SQ 1.40 0.50 BSC BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 1.50 REF

2.10 BSC

Figure 17. 16-Terminal Ceramic Leadless Chip Carrier [LCC]

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

PKG-000000 COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4. Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP]

Description

HMC674LC3C −40°C to +85°C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 H674 XXXX HMC674LC3CTR −40°C to +85°C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 H674 XXXX HMC674LC3CTR-R5 −40°C to +85°C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 H674 XXXX

HMC674LC3C/HMC674LP3E Data Sheet Rev. K | Page 14 of 14 Model 1 Temperature Range Package Body Material Lead Finish MSL Rating 2 Package HMC674LP3E −40°C to +85°C Low Stress, Injection Molded Plastic 100% Matte Sn MSL1 16-Lead LFCSP HCP-16-1 H674 XXXX HMC674LP3ETR −40°C to +85°C Low Stress, Injection Molded Plastic 100% Matte Sn MSL1 16-Lead LFCSP HCP-16-1 H674 XXXX 125932-HMC674LC3C HMC674LC3C Evaluation Board 125932-HMC674LP3E HMC674LP3E Evaluation Board 1 The HMC674LC3C, the HMC674LC3CTR, the HMC674LC3CTR-R5, the HMC674LP3E, and the HMC674LP3ETR are RoHS Compliant Parts. 2 See the Absolute Maximum Ratings section. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14861-0-12/16(K)