KAI-04070 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Superior Smear Rejection
- Up to 82 dB Linear Dynamic Range
- Bayer Color Pattern, TRUESENSE Sparse Color Filter Pattern, and Monochrome Configurations
- Progressive Scan & Flexible Readout Architecture
- High Frame Rate
- High Sensitivity − Low Noise Architecture
- Package Pin Reserved for Device Identification Application
- Industrial Imaging and Inspection
- Traffic
- Surveillance www.onsemi.com
Figure 1. KAI−04070 Interline CCD
ORDERING INFORMATION
KAI−04070 www.onsemi.com The sensor is available with the TRUESENSE Sparse Color Filter Pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The sensor shares common pin-out and electrical configurations with a full family of Truesense Imaging Interline Transfer CCD image sensors, allowing a single camera design to be leveraged in support of multiple devices. Table 2. ORDERING INFORMATION − KAI−04070 IMAGE SENSOR *Note recommended for new designs. Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Figure 2. Block Diagram
16 Dark
16 Buffer
1 Dummy
1 Dummy (Last VCCD Phase = V1 /C0224 H1S)
dark reference regions are classified as active buffer pixels. Power-Up and Power-Down Sequence section.
Figure 5. Package Pin Designations − Top View Table 4. PACKAGE PIN DESCRIPTION
1 V3B Vertical CCD Clock, Phase 3, Bottom
3 V1B Vertical CCD Clock, Phase 1, Bottom
4 V4B Vertical CCD Clock, Phase 4, Bottom
5 VDDa Output Amplifier Supply, Quadrant a
6 V2B Vertical CCD Clock, Phase 2, Bottom
7 GND Ground
8 VOUTa Video Output, Quadrant a
9 Ra Reset Gate, Standard (High) Gain, Quadrant a
10 RDab Reset Drain, Quadrants a & b
11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
12 OGa Output Gate, Quadrant a
13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a
16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a
17 R2ab Reset Gate, Low Gain, Quadrants a & b
18 SUB Substrate
19 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b
20 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b
21 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
Table 4. PACKAGE PIN DESCRIPTION (continued)
22 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b
23 H2SLb Horizontal CCD Clock, Phase 1, Storage, Last Phase, Quadrant b
24 OGb Output Gate, Quadrant b
25 Rb Reset Gate, Standard (High) Gain, Quadrant b
26 RDab Reset Drain, Quadrants a & b
27 GND Ground
28 VOUTb Video Output, Quadrant b
29 VDDb Output Amplifier Supply, Quadrant b
30 V2B Vertical CCD Clock, Phase 2, Bottom
31 V1B Vertical CCD Clock, Phase 1, Bottom
32 V4B Vertical CCD Clock, Phase 4, Bottom
33 V3B Vertical CCD Clock, Phase 3, Bottom
34 ESD ESD Protection Disable
35 V3T Vertical CCD Clock, Phase 3, Top
36 DevID Device Identification
37 V1T Vertical CCD Clock, Phase 1, Top
38 V4T Vertical CCD Clock, Phase 4, Top
39 VDDd Output Amplifier Supply, Quadrant d
40 V2T Vertical CCD Clock, Phase 2, Top
41 GND Ground
42 VOUTd Video Output, Quadrant d
43 Rd Reset Gate, Standard (High) Gain, Quadrant d
44 RDcd Reset Drain, Quadrants c & d
45 H2SLd Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d
46 OGd Output Gate, Quadrant d
47 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d
48 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d
49 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d
50 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d
51 R2cd Reset Gate, Low Gain, Quadrants c & d
52 SUB Substrate
53 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c
54 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c
55 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c
56 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c
57 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c
58 OGc Output Gate, Quadrant c
59 Rc Reset Gate, Standard (High) Gain, Quadrant c
60 RDcd Reset Drain, Quadrants c & d
61 GND Ground
62 VOUTc Video Output, Quadrant c
63 VDDc Output Amplifier Supply, Quadrant c
64 V2T Vertical CCD Clock, Phase 2, Top
65 V1T Vertical CCD Clock, Phase 1, Top
66 V4T Vertical CCD Clock, Phase 4, Top
67 V3T Vertical CCD Clock, Phase 3, Top
68 ESD EDS Protection Disable
- Liked named pins are internally connected and should have a common drive signal.
Table 5. TYPICAL OPERATIONAL CONDITIONS
- For monochrome sensor, only green LED used.
Table 6. PERFORMANCE SPECIFICATIONS
KAI−04070 www.onsemi.com Table 6. PERFORMANCE SPECIFICATIONS (continued)
Description
(/C0053C) Sampling PlanUnitMax.Nom.Min.Symbol KAI−04070−ABA AND KAI−04070−PBA AND KAI−04070−QBA CONFIGURATIONS Peak Quantum Efficiency QEMAX − 52 − % Design Peak Quantum Efficiency Wavelength /C0108QE − 500 − nm Design KAI−04070−FBA AND KAI−04070−QBA GEN2 COLOR CONFIGURATIONS Peak Quantum Efficiency Blue Green Red QEMAX % Design Peak Quantum Efficiency Wavelength Blue Green Red /C0108QE 460 535 610 nm Design KAI−04070−CBA AND KAI−04070−PBA GEN1 COLOR CONFIGURATIONS (Note 7) Peak Quantum Efficiency Blue Green Red QEMAX % Design Peak Quantum Efficiency Wavelength Blue Green Red /C0108QE 470 540 620 nm Design 1. Per color. 2. Value is over the range of 10% to 90% of linear signal level saturation. 3. The operating value of the substrate voltage, V AB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 440 mV. This value is determined while operating the device in the low gain mode. VAB value assigned is valid for both modes; high gain or low gain. 4. At 40 MHz. 5. Uses 20LOG (P Ne /n e−T). 6. Assumes 5 pF load. 7. This color filter set configuration (Gen1) is not recommended for new designs. Linear Signal Range Figure 6. High Gain Linear Signal Range Figure 7. Low Gain Linear Signal Range
Table 7. OPERATION CONDITIONS FOR DEFECT TESTING AT 40/C0053C
- For monochrome sensor, only the green LED is used.
Table 8. DEFECT DEFINITIONS FOR TESTING AT 40/C0053C but no more than 2 adjacent defect horizontally. pixels along a single column.
- For the color devices (KAI−04070−CBA and KAI−04070−PBA), a bright field defective pixel deviates by 12% with respect to pixel s of the
- Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ).
Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 27/C0053C
- For monochrome sensor, only the green LED is used.
Table 10. DEFECT DEFINITIONS FOR TESTING AT 40/C0053C but no more than 2 adjacent defect horizontally. pixels along a single column.
- For the color devices (KAI−04070−CBA and KAI−04070−PBA), a bright field defective pixel deviates by 12% with respect to pixel s of the
- Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ).
Figure 22 for the location of pixel 1, 1.
is overclocked in both the vertical and horizontal directions. Figure 22. Regions of Interest
16 Dark Rows
24 Dark Columns
16 Buffer Rows
16 Buffer Columns
This test is performed under dark field conditions. level of each of the 256 sub regions of interest is calculated.
KAI−04070 www.onsemi.com Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mV. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. The average signal level of each of the 256 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] /C0043(ROI Average in Counts /C0042 /C0042Horizontal Overclock Average in Counts) /C0064 /C0064mV per Count Where i = 1 to 256. During this calculation on the 144 sub regions of interest, the maximum and minimum signal levels are found. The global peak to peak uniformity is then calculated as: Global Uniformity /C0043100 /C0064/C0466Max. Signal /C0042Min. Signal Active Area Signal /C0467 Units : % pp Center Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mV . Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels of the sensor. Center uniformity is defined as: Center ROI Uniformity /C0043100 /C0064/C0466Center ROI Standard Deviation Center ROI Signal /C0467 Center ROI Signal = Center ROI Average − Dark Colum Average Units : % rms Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the “Detect Definitions” section. Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 924 mV . Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mV . The average signal level of all active pixels is found. The bright and dark thresholds are set as: Dark Defect Threshold = Active Area Signal /C0064Threshold Bright Defect Threshold = Active Area Signal /C0064Threshold The sensor is then partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified.
- Example for major bright field defective pixels:
- Average value of all active pixels is found to be 924 mV
- Dark defect threshold: 924 mV ⋅ 12% = 111 mV
- Bright defect threshold: 924 mV ⋅ 12% = 111 mV
- Region of interest #1 selected. This region of interest is pixels 17, 17 to pixels 144, 144 ♦ Median of this region of interest is found to be 920 mV ♦ Any pixel in this region of interest that is ≤ (920 − 111 mV) 809 mV in intensity will be marked defective ♦ Any pixel in this region of interest that is ≥ (920 + 111 mV) 1,031 mV in intensity will be marked defective
- All remaining 144 sub regions of interest are analyzed for defective pixels in the same manner
at these values will reduce MTTF. Table 11. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- Noise performance will degrade at higher temperatures.
- T = 25 °C. Excessive humidity will degrade MTTF.
- Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 12. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
- /C0097 denotes a, b, c or d.
- Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
- To operate in accordance with a system designed for KAI−08050, the target substrate voltage should be set to be 2.0V higher than the value recorded on the KAI−04070 shipping container. This setting will cause the charge capacity to be limited to 20 ke − (or 660 mV)
- On the KAI−04070, pins 17 (R2ab) and 51 (R2cd) should be left floating per the KAI−08050 Device Performance Specification
- The KAI−04070 will operate in only the high gain mode (33 /C0109V/e−)
- All timing and voltages are taken from the KAI−08050 specification sheet
- The number of horizontal and vertical CCD clock cycles is reduced as appropriate In addition, if the intent is to operate the KAI−04070 image sensor in a camera designed for the KAI−08050 sensor that has been modified to accept and process the full 40,000 e − (1,320 mV) output, the following changes to the RD bias must be made: Table 13. Pins Names KAI−08050 KAI−04070 10, 26, 44, 60 RDa, RDb, RDc, RDd 12.0 V per the Specification Increase to 12.6 V To make use of the low or dual gains modes the KAI−04070 voltages and timing specifications must be used.
Table 14. DC BIAS OPERATING CONDITIONS
- /C0097 denotes a, b, c or d.
- The maximum DC current is for one output. I DD = IOUT + ISS. See Figure 27.
- The operating value of the substrate voltage, V AB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
- An output load sink must be applied to each VOUT pin to activate each output amplifier.
- Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.
- Adherence to the power-up and power-down sequence is critical. See Sequence section.
- ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V.
- Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
- 12.0 V may be used if the total output signal desired is 20,000 e
10.Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application. Figure 27. Output Amplifier
KAI−04070 www.onsemi.com AC Operating Conditions Table 15. CLOCK LEVELS (Note 1) Symbol Level Min. Nom. Max. Unit Vertical CCD Clock, Phase 1 V1B, V1T V1_L Low −8.2 −8.0 −7.8 V V1_M Mid −0.2 0.0 0.2 V1_H High 11.5 12.0 12.5 Vertical CCD Clock, Phase 2 V2B, V2T V2_L Low −8.2 −8.0 −7.8 V V2_H High −0.2 0.0 0.2 Vertical CCD Clock, Phase 3 V3B, V3T V3_L Low −8.2 −8.0 −7.8 V V3_H High −0.2 0.0 0.2 Vertical CCD Clock, Phase 4 V4B, V4T V4_L Low −8.2 −8.0 −7.8 V V4_H High −0.2 0.0 0.2 Horizontal CCD Clock, Phase 1 Storage H1S/C0097H1S_L Low −5.2 −4.0 −3.8 V H1S_A Amplitude (Note 3) 3.8 4.0 5.2 Horizontal CCD Clock, Phase 1 Barrier H1B/C0097H1B_L Low −5.2 −4.0 −3.8 V H1B_A Amplitude (Note 3) 3.8 4.0 5.2 Horizontal CCD Clock, Phase 2 Storage H2S/C0097H2S_L Low −5.2 −4.0 −3.8 V H2S_A Amplitude (Note 3) 3.8 4.0 5.2 Horizontal CCD Clock, Phase 2 Barrier H2B/C0097H2B_L Low −5.2 −4.0 −3.8 V H2B_A Amplitude (Note 3) 3.8 4.0 5.2 Horizontal CCD Clock, Last Phase (Note 2) H2SL/C0097H2SL_L Low −5.2 −5.0 −4.8 V H2SL_A Amplitude (Note 3) 4.8 5.0 5.2 Reset Gate R1/C0097 R_L Low −3.2 −3.0 −2.8 V R_A Amplitude 6.0 − 6.4 Reset Gate 2 R2/C0097 R2_L Low −2.0 −1.8 −1.6 V R2_A Amplitude 6.0 − 6.4 Electronic Shutter (Note 4) SUB VES High 29.0 30.0 40.0 V 1. /C0097 denotes a, b, c or d. 2. Use separate clock driver for improved speed performance. 3. The horizontal clock amplitude should be set such that the high level reaches 0.0 V. Examples: 4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. Figure 28. DC Bias and AC Clock Applied to the SUB Pin
Table 16. CAPACITANCE
- Tables show typical cross capacitance between pins of the device.
- Capacitance is total for all like pins.
- Capacitance values are estimated.
Table 17. DEVICE IDENTIFICATION
- Nominal value subject to verification and/or change during release of preliminary specifications.
- If the Device Identification is not used, it may be left disconnected.
- After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor. Note that V1 must be a different value than V2. Figure 29. Device Identification Recommended Circuit
Table 18. REQUIREMENTS AND CHARACTERISTICS
- Refer to Figure 47: VCCD Clock Rise Time, Fall Time, and Edge Alignment.
- Relative to the VCCD Transfer pulse width, t V.
NV , are shown in the following table. Table 19. VALUES FOR NH AND NV WHEN OPERATING THE SENSOR IN THE VARIOUS MODES OF RESOLUTION
- The time to read out one line t LINE = Line Timing + NH / (Pixel Frequency).
- The time to read out one frame t FRAME = NV ⋅ tLINE + Frame Timing.
- Line Timing: See Table 21: Line Timing.
- Frame Timing: See Table 20: Frame Timing.
- XLDR: eXtended Linear Dynamic Range.
Figure 30. Timing Flow when Electronic Shutter is Not Used
Figure 31. Timing Flow Chart using the Electronic Shutter for Exposure Control NOTE: NEXP: Exposure time in increments of number of lines.
Table 20. FRAME TIMING
- This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interli ne Transfer
- SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
- This note intentionally left empty.
- Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
- Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
Figure 37 for line timing diagrams. Table 21. LINE TIMING
- This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interli ne Transfer
- SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
- The notation 2 × L1B means repeat the L1B timing twice for every line. This sums two rows into the HCCD.
- Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
- Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
This timing is for transferring one pixel from the HCCD to the output amplifier. Table 22. PIXEL TIMING
- This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interli ne Transfer
- SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
- This note intentionally left empty.
- Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
- Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
integration time ends on the falling edge of the +12 V pulse. Figure 32. Frame Timing Diagram Quadrant and Dual VOUTa/VOUTc Readout Modes NOTE: See Table 20 for pin assignments.
Figure 33. Frame Timing Diagram Single and Dual VOUTa/VOUTb Readout Modes NOTE: See Table 20 for pin assignments.
Figure 34. Line Timing Diagram − Full Resolution − Quadrant and Dual VOUTa/VOUTc Readout Modes NOTE: See Table 21 for pin assignments.
Figure 35. Line Timing Diagram − Full Resolution − Single and Dual VOUTa/VOUTb Readout Modes NOTE: See Table 21 for pin assignments.
Figure 36. Line Timing Diagram − 1/4 Resolution − Quadrant and Dual VOUTa/VOUTc Readout Modes NOTE: See Table 21 for pin assignments.
Figure 37. Line Timing Diagram − 1/4 Resolution − Single and Dual VOUTa/VOUTb Readout Modes NOTE: See Table 21 for pin assignments.
not applied to the image sensor. Figure 40. Pixel Timing Diagram − Full Resolution − High Gain
Use this pixel timing to read out every pixel at low gain. applied to the image sensor. Figure 41. Pixel Timing Diagram − Full Resolution − Low Gain
applied to the image sensor. pixels to be summed on the output amplifier sense node. Figure 42. Pixel Timing Diagram − 1/4 Resolution − High Gain
pins can be set to any DC voltage between +3 V and +5 V . and SHDQ pulses are not applied to the image sensor. Figure 43. Pixel Timing Diagram − 1/4 Resolution − Low Gain
Figure 45. Pixel Timing Diagram − 1/4 Resolution − XLDR − Constant HCCD Timing
Figure 46. Pixel Timing Diagram − 1/4 Resolution − XLDR − Variable HCCD Timing
Figure 47. VCCD Clock Rise Time, Fall Time and Edge Alignment
Figure 50. Cover Glass
- Substrate = Schott D263T eco.
- Dust, Scratch, Inclusion Specification: 10 /C0109m maximum size in Zone A.
Figure 51. Cover Glass Transmission
KAI−04070 www.onsemi.com REFERENCES For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For information on environmental exposure, please download the Using Interline CCD Image Sensors in High Intensity Lighting Conditions Application Note (AND9183/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidia ries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 KAI−04070/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative