11C90DCQR

11C90 NSC | Alldatasheet

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11C90/11C91 650 MHz Prescalers Not Intended For New Designs August 1992 11C90/11C91

650 MHz Prescalers

The 11C90 and 11C91 are high-speed prescalers designed specifically for communication and instrumentation applica- tions. All discussions and examples in this data sheet are applicable to the 11C91 as well as the 11C90. The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6, both over a frequency range from DC to typically 650 MHz. The division ratio is controlled by the Mode Control. The divide-by-10 or -11 capability allows the use of pulse swal- lowing techniques to control high-speed counting modulos by lower-speed circuits. The 11C90 may be used with either ECL or TTL power supplies. In addition to the ECL outputs Q and Q , the 11C90 contains an ECL-to-TTL converter and a TTL output. The TTL output operates from the same V CC and V EE levels as the counter, but a separate pin is used for the TTL circuit V EE. This mini- mizes noise coupling when the TTL output switches and also allows power consumption to be reduced by leaving the separate V EE pin open if the TTL output is not used. To facilitate capacitive coupling of the clock signal, a 400 X resistor (V REF) is connected internally to the V BB reference. Connecting this resistor to the Clock Pulse input (CP) auto- matically centers the input about the switching threshold. Maximum frequency operation is achieved with a 50% duty cycle. Each of the Mode Control inputs is connected to an internal 2k X resistor with the other end uncommitted (RM 1 and RM2). An M input can be driven from a TTL circuit operating from the same V CC by connecting the free end of the asso- ciated 2 k X resistor to V CCA. When an M input is driven from the ECL circuit, the 2 k X resistor can be left open or, if required, can be connected to V EE to act as a pull-down resistor. Logic Symbol TL/F/9892–2 Pin Names Description CE Count Enable Input (Active LOW) CP Clock Pulse Input M n Count Modulus Control Input MS Asynchronous Master Set Input Q, Q ECL Outputs QTTL TTL Output RMn 2k X Resistor to M n VREF 400X Resistor to V BB Connection Diagram 16-Pin DIP TL/F/9892–1 C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Above which the useful life may be impaired If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Maximum Junction Temperature (T J) a150§C Supply Voltage Range b7.0V to GND Input Voltage (DC) V EE to GND Output Current (DC Output HIGH) b50 mA Operating Range b5.7V to b4.7V Lead Temperature (Soldering, 10 sec.) 300 §C Recommended Operating Conditions Min Typ Max Ambient Temperature (T A) Commercial 0 §C a75§C Military b55§C a125§C Supply Voltage (V EE) Commercial b5.7V b5.2V b4.7V Military b5.7V b5.2V b4.7V TTL Input/Output Operation Over Operating Temperature and Voltage Range unless otherwise noted, Pins 12 and 13 e GND Symbol Parameter Min Typ Max Units Conditions(Note 3) VIH Input HIGH Voltage 4.1 V Guaranteed Input HIGH Threshold M1 and M 2 Inputs Voltage (Note 4), V CC e VCCA e 5.0V VIL Input LOW Voltage 3.3 V Guaranteed Input LOW Threshold M1 and M 2 Inputs Voltage (Note 4), V CC e VCCA e 5.0V VOH Output HIGH Voltage 2.3 3.3 V VCC e VCCA e Min, QTTL Output I OH eb 640 mA VOL Output LOW Voltage 0.2 0.5 V VCC e VCCA e Min, QTTL Output I OL e 20.0 mA IIL Input LOW Current b2.3 b5.0 mA VCC e VCCA e Max, M1 and M 2 Inputs V IN e 0.4V, Pins 6, 7 e VCC ISC Output Short Circuit b20 b35 b80 mA VCC e VCCA e Max, Current V OUT e 0.0V, Pin 14 e VCC VCC e VCCA e 5.0V Nominal, V EE e GND, T A ea 25§C Symbol Parameter Min Typ Max Units Conditions tPLH Propagation Delay, (50% to 50%) 61 0 1 4 n s See Figure 1 tPHL CP to QTTL tPLH Propagation Delay, (50% to 50%) 12 17 nsMS to QTTL ts Mode Control Setup Time 4 2 ns th Mode Control Hold Time 0 b2n s tTLH Output Rise Time 10 ns(20% to 80%) tTHL Output Fall Time 2n s(80% to 20%) fMAX Count Frequency 550 650 MHz b55§Ct o a125§C 600 650 0 §Ct o a75§C Clock Input AC Coupled 350 mV Peak-to-Peak Sinewave (Note 5)

ECL OperationÐCommercial Version VCC e VCCA e GND, V EE eb 5.2V Symbol Parameter Min Typ Max Units T A Conditions VOH Output HIGH Voltage b1060 b995 b905 0 §C Load e 50X to b2V Q and Q b1025 b960 b880 mV a25§C b980 b910 b805 a75§C VOL Output LOW Voltage b1820 b1705 b1620 mV 0§Ct o Q and Q a75§C VIH Input HIGH Voltage b1135 b840 0 §C Guaranteed Input HIGH b1095 b810 mV a25§C Signal (Note 6) b1035 b720 a75§C VIL Input LOW Voltage b1870 b1500 0 §C Guaranteed Input LOW b1850 b1485 mV a25§C Signal b1830 b1460 a75§C IIH Input HIGH Current V IN e VIHA CP Input (Note 1) 400 a25§C MS Input 400 mA a25§C M1 and M 2 Input 250 a25§C IIL Input LOW Current 0.5 mA a25§CV IN e VILB IEE Power Supply Current b110 b75 mA 0§C to Pins 6, 7, 13 not connected b119 a75§C VEE Operating Supply b5.7 b5.2 b4.7 V 0§Ct o Voltage Range a75§C VREF Reference Voltage b1550 b1150 mV a25§C VRM1 e VRM2 eb 5.2V IN eb 10.0 mA TA e 0§Ct o a75§C, V CC e VCCA e GND, V EE eb 5.2V Symbol Parameter 0§C a25§C a75§C Units ConditionsTyp Min Typ Max Typ tPHL (50% to 50%) CP to Q R L e 50X to b2.0V ts Setup Time, M to CP 2.0 4.0 2.0 2.0 ns (20% to 80%) th Hold Time, M to CP b2.0 0.0 b2.0 b2.0 ns See Figure 1 tTLH Output Rise Time 1.0 1.0 2.0 1.0 ns(20% to 80%) tTHL Output Fall Time 1.0 1.0 2.0 1.0 ns(80% to 20%) fMAX Maximum Clock Frequency AC Coupled Input 350 mV 650 600 650 625 MHz Peak-to-Peak. f MAX is Guaranteed to be 575 MHz Min at 0 §Ct o a75§C.

ECL OperationÐMilitary Version VCC e VCCA e GND, V EE eb 5.2V Symbol Parameter Min Typ Max Units T A Conditions VOH Output HIGH Voltage b1100 b1030 b900 b55§C Load e 100X to b2V Q and Q b980 b910 b820 mV a25§C b910 b820 b670 a125§C VOL Output LOW Voltage b1820 b1705 b1620 mV b55§Ct o Q and Q a125§C VIH Input HIGH Voltage b1190 b905 b55§C Guaranteed Input HIGH b1095 b810 mV a25§C Signal (Note 6) b975 b690 a125§C VIL Input LOW Voltage b1890 b1525 b55§C Guaranteed Input LOW b1850 b1485 mV a25§C Signal b1800 b1435 a125§C IIH Input HIGH Current V IN e VIHA CP Input (Note 1) 400 a25§C MS Input 400 mA a25§C M1 and M 2 Input 250 a25§C IIL Input LOW Current 0.5 mA a25§CV IN e VILB IEE Power Supply Current b110 b75 mA a25§C Pins 6, 7, 13 not connected b119 mA b55§Ct o a125§C VEE Operating Supply b5.7 b5.2 b4.7 V b55§Ct o Voltage Range a125§C VREF Reference Voltage b1550 b1150 mV a25§C VRM1 e VRM2 eb 5.2V IN eb 10.0 mA TA eb 55§Ct o a125§C, V CC e VCCA e GND, V EE eb 5.2V Symbol Parameter b55§C a25§C a125§C Units ConditionsTyp Min Typ Max Typ tPHL (50% to 50%) CP to Q R L e 50X to b2.0V tPLH Propagation Delay, 3.5 4.0 6.0 5.0 ns(50% to 50%) MS to Q Input: ts Setup Time, M to CP 2.0 4.0 2.0 2.0 ns tri e tfi e 2.0 g0.1 ns th Hold Time, M to CP b2.0 0.0 b2.0 b2.0 ns (20% to 80%) tTLH Output Rise Time 1.0 1.0 2.0 1.0 ns See Figure 1 (20% to 80%) tTHL Output Fall Time 1.0 1.0 2.0 1.0 ns(80% to 20%) fMAX Maximum Clock Frequency AC Coupled Input 350 mV 700 600 650 600 MHz Peak-to-Peak. f MAX is Guaranteed to be 550 MHz Min at b55§Ct o a125§C. Note 1: Conditions for testing, not shown in the Table, are chosen to guarantee operation under ‘‘worst case’’ conditions. Note 2: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these ‘‘worst case’’ values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 3: Typical limits are at V CC e 5.0V and T A ea 25§C. Note 4: The M 1 and M 2 threshold specifications are normally referenced to the V CC potential, as shown in the ECL operation tables. Using V EE (GND) as the signal swing about threshold of g0.4V is adequate, which gives the state V IH and V IL values. The internal 2 k X resistors are intended to pull TTL outputs up to the required V IH range, as discussed in the Functional Description and shown in Figure 5. Note 5: TTL Output Signal swing is guaranteed at f MAX over temperature range. Note 6: M1 or M 2 can be tied to V CC for fixed divide-by-ten operation.

Note 7: Use high impedance to test QTTL. Note 8: For High frequency test use AC coupled input as in Figure 3 . Adjust input amplitude to 350 mV peak-to-peak. FIGURE 1. AC Test Circuit

Functional Description (Continued) The ECL outputs have no pull-down resistors and can drive series or parallel terminated transmission lines. For short interconnections that do not require impedance matching, a 270X to 510 X resistor to V EE can be used to establish the VOL level. Both V CC pins must always be used and should be connected together as close to the package as possible. Pin 12 must always be connected to the V EE side of the supply, while pin 13 is required only if the TTL output is used. Low impedance V CC and V EE distribution and RF by- pass capacitors are recommended to prevent crosstalk. Logic Diagram 11C90 TL/F/9892–6 Note: This diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many internal functions are achieved more efficiently than shown. Count Sequence Table 11C90 TL/F/9892–7 Note: A HIGH on MS forces all Qs HIGH. Operating Mode Table 11C90 Inputs Output MS CE M1 M2 Response H X X X Set HIGH L H X X Hold LLLL d11 LLH X d10 LLX H d10 H e HIGH Voltage Level L e LOW Voltage Level X e Don’t Care

TL/F/9892–8 Count Sequence Table 11C91 TL/F/9892–9 Note: A HIGH on MS forces all Qs HIGH. Operating Mode Table 11C91 Inputs Output MS CE M1 M2 Response H X X X Set HIGH L H X X Hold LLLL LLX H d5 LLH X d5 H e HIGH Voltage Level L e LOW Voltage Level X e Don’t Care

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 11C90/91 D C QR Device Number Special Variations (basic) QR e Commercial grade device with burn-inPackage Code D e Ceramic Dual In-Line Temperature Range C e Commercial (0 §Ct o a85§C)

11C90/11C91 650 MHz Prescalers Physical Dimensions inches (millimeters)

16 Lead Ceramic Dual-In-Line Package (D)

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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