11C83

11C83 FAIRCHILD | Alldatasheet

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1 GHz DIVIDE-BY-248/256 PRESCALER

GENERAL DESCRIPTION ~ The 11C83 Prescaler is guaranteed to operate above 950 TOGic SYMBOL MiHz over the 0°C to +75°C temperature range and with a Veg variation from +4.78 to +5.5 V. The circuit requires only one supply voltage and the clock input signal can be either de or ac coupled. The prescaler divides by either 248 or 256, as determined by the signal applied to the Mode Control (M) input. This feature makes it possible to use the 11C83 in conjunction with other logic to achieve a broad range of overall divide 12 ratios, either fixed or programmable. For example, a divide ratio of 1000 can be achieved by one 11C83 and one 9LS161 modulo-16 counter. ‘ Ef ° © DC TO 950 MHz OPERATION - GUARANTEED OVER 0°C To +75°C © DC OR AC COUPLED INPUT © USES STANDARD TTL OR CMOS POWER SUPPLY ‘© OUTPUT DRIVES TTL OR CMOS © DIVIDE BY 248/256 MODE CONTROL Veo" Pint Veca = Pin 14 FUNCTIONS GND = Pin 7 = ie CP ~ Clock pulse input O= Output w/2k pull-up M~ Mode Conta input R= 10k to GND. for optional CP offset Low = = 248 Vper ~ Internal reference voltage, for HIGH = + 256 ac coupled clocking FUNCTIONAL BLOCK DIAGRAM CONNECTION DIAGRAM 14-PIN DIP (TOP VIEW) “sy rena ? FE 1 \\

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FAIRCHILD 11C0O SERIES e 11C83 FUNCTIONAL DESCRIPTION — The 11C83 contains a 3-stage modulo-8 divider whose output drives a 5-stage modulo-31/32 divider. The 5-stage circuit has a natural divide ratio of 32, buta LOW signal on the Mode Control input causes it to skip one state and thus divide by 31. Referred to the CP input, this changes the overalll divide ratio from 256 to 248. Both dividers are designed with ECL circuitry and the divide-by-31/32 drives an ECL-to-TTL translator. The translator has a2k0 pull-up resistor returned to Vcc through a diode and thus will pull up high enough to drive CMOS as well as, TTL inputs. In the LOW state, the output can sink 10 mA at a Vor level of 0.5 V or less. The relationship between the output waveform, the divide ratio and the Mode Control input signal are outlined in Figure 2. The trigger pulses shown are those which operate the divide-by-31/32 circuit. Although these pulses cannot be monitored, they are convenient to use as timing references in discussing delay time, setup time and, by extension, timing constraints on any external logic used to generate Mode Control signals. As shown, the output is LOW for 16 pulse periods regardless of the state of M. The duration of the output HIGH state, however, can be either 15 or 16 pulse periods. The pulse edge that makes Q go HIGH is identified as to. The 15th following pulse edge causes Q to go LOW if Mis LOW at least 3 ns before ts. If Mis HIGH at this time, Qwill go low after the 16th pulse edge following to. The mutual constraints between the maximum operating frequency and the total delay in generat- ing the M input signal can be deduced by considering an example. Figure 3 shows an 11C83 driving the clock input of a 9LS161 Modulo-16 Counter. The table shows that the 9LS161 counts up from to B and then presets back to 5 to repeat the sequence. Its Q2 and Qs outputs drive the Preset Enable of the 9LS161 and the M input of the 11C83. The clock input of the 9LS161 responds to the positive- going edge of the 11C83 output and, thus, it is appropriate to evaluate delays from to of Figure 2. The indicated tH consists of a worst-case deiay of 25 ns, plus the time to rise to the 1.3 V level at the 9LS161 input. For a stray capacitance of 10 pF, this rise will not exceed 10 ns. Thus the te. in Figure 2 will be 35 ns or less. The worst-case tpLH of the 9LS161, from CP to Q, is 20 ns with a 15 pF load and is measured to the 1.3 Vlevel on the rising output. The Qs output must rise further, however, to reach the Vix level of the M input, which is approximately 1.5 V below Vcc. This extra rise takes about 8 ns. Note that an external 2 kM pull-up resistor is shown in Figure 3. This provides additional HIGH state noise margin and also helps the Qs rise rate. This resistor also tends to increase the teu. of the 9LS161, as, measured at the 1.3 V level, but this is not a critical timing factor because the falling Qe output is effectively in the LOW state as soon as it passes through the Vi level of the 11C83M input, at about 26 V. For this example, the cumulative delays from to of Figure 2 are 35 ns tpy to the 9LS161 CP input plus 28 ns to the 11C83 M input. Adding 3 ns setup time for M preceding t)s gives a minimum time of 66 ns for the period of 15 pulses into the divide-by-31/32 circuit. But at a frequency of 1 GHz into the divide-by-6 circuit, the pulse frequency into the divide-by-31/32 is 125 MHz and 15 pulse periods constitute 120 ns. Thus the frequency limit for Figure 3 is that of the 11C83 input, rather than the delays in the Mode Control feedback loop. A different result is obtained by replacing the 9LS161 with the F40161 CMOS equivalent. CMOS delays are measured between the 50% points, or 2.5 V with a 5 V supply. Thus the 1183 output rise time is measured to the 2.5 V level rather than 1.3 V, which takes approximately 25 ns rather than 10 ns. The worst-case tp.y of the F40161 is 185 ns to the 2.5 V level and the output rise from 2.5 V to 3.5 V takes another 5 ns. Substituting these numbers in the previous example gives 243 ns minimum for the period of 120 pulses into the divide-by-8. This gives an upper frequency limit of about 495 MHz. The frequency limit can be extended by using a logic inverter between the 11C83 output and the clock input of the F40161. This makes the F40161 trig- ger when the 11C83 output goes negative, rather than positive, which precedes ty by the period of 128 pulses into the divide-by-8. Since the 11C83 output falls to 2.5 V much faster than it rises, a CMOS inverter increases the total delay to only about 260 ns. This is the minimum period for 248 pulses into the divide-by-8, which translates to a maximum frequency of 955 MHz. Note that the 2 kQ pull-up resistor of Figure 3 is not required with the CMOS counter, nor is it desirable from the standpoint of loading the Q2 output in the LOW state. If an application requires a prescaler output HIGH signal level more positive than +5 V, it will be necessary to use a discrete transistor or some other type of interface circuit. The use of an external pull-up resistor returned to a higher voltage is not recommended, due to the possibility of causing latch-up in the output transistor. This voltage limitation is one of the trade-offs necessary to achieve transistors with the bandwidth required for 1 GHz counting 9-33

FAIRCHILD 11C0OO SERIES e 11083 The 11C83 clock input is one side of a differential switch whose other side is connected to an internally generated reference voltage. A 400 2 internal resistor is connected between the clock input and reference voltage, as shown in Figure 1. This biases the input in the middie of the threshold region, which maximizes the input sensitivity and eliminates the need for external biasing resistors with capacitively coupled clocking. Also provided is a 10 kf resistor returned to Vee. For ac coupled applications in which a clock signal is not always present, this resistor(pin 3) should be ‘connected to the clock pin. This offsets the input sufficiently to avoid extreme sensitivity to noise when no signal is present, Otherwise, noise triggering can lead to oscillation at about 300 MHz. For dc coupled clocking the input signal levels should be designed to provide the specified Vin and Vi_ levels, which are nominally 2.5 V and 3.3 V below Vcc, respectively. For a sinusoidal input waveform the minimum frequency of operation is about 50 MHz, due to edge rate limitations. Operation down to dc is possible Provided that the input pulse edges have a slew rate of 50 V/us or better. Minimum peak-to-peak trigger amplitude as a function of frequency is shown in Figure 4. Maximum recommended trigger amplitude is 1200 mV pk-pk. An rf bypass capacitor should be connected between Vrer (pin 6) and ground to maintain input sensitivity and to make the input impedance independent of internal ‘switching. Input impedance is 54 0 resistive at 1 GHz and has a capacitive component at lower frequencies, as shown in Figure 5. The 11C83 uses separate Vcc pins for the faster and slower parts of the circuit to prevent any interaction through the medium of lead inductance. The two Vec pins should be connected together as close to the package as possible. Low impedance Vcc and Vee (GND) distribution and rf bypass capacitors are recommended to prevent crosstalk with other circuits. eee rd 19083 ove i 4} Fig. 2. Effect of M on Output Duty Cycle [es Ey mitt LY 20 Oy 03 Oy xem | Fig.3 Divide-by-1000 Obtained by Pulse-Swallowing | = © 1200) ~ i t benine \\ aa i | SE Noe ir oes eS En t } \\ ae : 7 xan Fig. 4 AC Coupled Triggering Characteristics Fig. 5 High Frequency Input Characteristics 9-34

FAIRCHILD 11C00 SERIES ¢ 11C83 OC CHARACTERISTICS: Over operating temperature and voltage range unless otherwise specified: Pins 1 and 14 = Vcc. Pin 7= GND symgot | CHARACTERISTIC z = uns | conpitions Vou Output HIGH Voltage 27 36 v Veo = 4.75 V, Igy = 240 uA 35 42 v Voc = 4.75 V. loy = 10 wa Vou Output LOW Voltage 04 v Vee = 4.75 V. lo, = 10 mA 0.33 v Voc = 4.75 V, Io, = 5.0 mA Vin Input HIGH Voltage at CP input 2.40 v Tq = 75°C (Note 3) 2.50 v Ta = 25°C 2.55 v Ta =0°C Vie Input LOW Voltage at CP Input 1.60 v Ta = 75°C (Note 3) 1.70 v Ta = 25°C 1.75 v Ta =0°C Vin Input HIGH Voltage at M Input 358 Vee v Voc = 5.0 V. Ta = 75°C (Note 3) 3.40 Vee v Vec = 8.0 V. Ta = 25°C 3.34 Vee v Voc = 5.0 V, Ta = 0°C Vit Input LOW Voltage at M Input 278 v Voc = 50 V, Ta = 75°C (Note 3) 2.60 v Vec ~ 5.0 V, Ta = 25°C 254 v Voc = 50V. Ta = 0° los. | Ovtbut Shon: Greut Curt a es noTes 1 The actual testing procedures used to guarantee the Electrical Characteristics are contained in a detalled Customer Sample Specification. a copy of which may be obteined trom Fowehild ECL Product Marketing, Mountain View, Ca. 2. Typical values Bre at Vcc ~ 50 V and Tq = 25°C AC CHARACTERISTICS: Ta = 0°C to +75°C, Pins 1 and 14 = +5.0V, Pin 7= GND | | LIMITS: SYMBOL CHARACTERISTIC UNITS: CONDITIONS a [om Ta | fcount | Maximum Sinusoidal Input Frequency 950 Miz | ac coupied input, 800 mV pk-pk fount | Minimum Sinusoidal Input Frequency MHz | Note 1 noves 1. Input drive shall not exceed 1.2 V pk-pk. 2. Operston at very low frequency is possible, provided that sufficient slew rate of the input pulse edge 1s maintained 9-95