1191

MAX1191 MAXIM | Alldatasheet

Document overview

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Technical content

Features

12mW (Normal Operation: 7.5Msps) 0.3µW (Shutdown Mode) o Excellent Dynamic Performance 48.7dB SNR at fIN = 1.875MHz 69dBc SFDR at fIN = 1.875MHz o 2.7V to 3.6V Single Analog Supply o 1.8V to 3.6V TTL/CMOS-Compatible Digital Outputs o Fully Differential or Single-Ended Analog Inputs o Internal/External Reference Option o Multiplexed CMOS-Compatible Tri-State Outputs o 28-Pin Thin QFN Package o Evaluation Kit Available (Order MAX1193EVKIT) MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC MAX1191 5mm x 5mm THIN QFN TOP VIEW INA+ EXPOSED PADDLE INA- GND CLK GND INB+ INB- VDD REFP REFN COM REFIN PD0 PD1 A/B D6D7 OV DD OGNDGNDVDDVDD Pin Configuration

Ordering Information

19-2836; Rev 1; 9/03 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE MAX1191ETI-T -40 °C to +85°C 28 Thin QFN-EP* (5mm x 5mm) *EP = Exposed paddle.

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, f CLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin Thin QFN (derated 20.8mW/°C above +70°C) ...1667mW PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Bits Integral Nonlinearity INL ±0.15 ±1.00 LSB Differential Nonlinearity DNL No missing codes over temperature ±0.13 ±1.00 LSB ≥+25°C ±4Offset Error <+25°C ±6 %FS Gain Error Excludes REFP - REFN error ±2 %FS DC Gain Matching ±0.01 ±0.2 dB Gain Temperature Coefficient ±30 ppm/ °C Offset (VDD ±5%) ±0.2Power-Supply Rejection Gain (VDD ±5%) ±0.05 LSB ANALOG INPUT Differential Input Voltage Range V DIFF Differential or single-ended inputs ±0.512 V Common-Mode Input Voltage Range VCOM VDD / 2 V Input Resistance R IN Switched capacitor load 720 k Ω Input Capacitance C IN 5p F CONVERSION RATE Maximum Clock Frequency f CLK 7.5 MHz Channel A 5.0Data Latency Channel B 5.5 Clock cycles DYNAMIC CHARACTERISTICS (differential inputs, 4096 point FFT) fIN = 1.875MHz 47 48.7Signal-to-Noise Ratio (Note 2) SNR fIN = 3.75MHz 48.6 dB fIN = 1.875MHz 47 48.6Signal-to-Noise and Distortion (Note 2) SINAD fIN = 3.75 48.5 dB

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, f CLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS fIN = 1.875MHz 59 69Spurious-Free Dynamic Range (Note 2) SFDR fIN = 3.75MHz 68.7 dBc fIN = 1.875MHz 72.0Thi r d - H ar m oni c D i stor ti on ( N ote 2) HD3 fIN = 3.75MHz -70.0 dBc Intermodulation Distortion IMD fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS -66 dBc Third-Order Intermodulation IM3 fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS -70 dBc fIN = 1.875MHz -68.0 -57.0Total Harmonic Distortion (Note 2) THD fIN = 3.75MHz -67.0 dBc Small-Signal Bandwidth SSBW Input at -20dB FS 440 MHz Full-Power Bandwidth FPBW Input at -0.5dB FS 440 MHz Aperture Delay t AD 1.5 ns Aperture Jitter t AJ 1dB SNR degradation at Nyquist 2 ps RMS Overdrive Recovery Time 1.5 × full-scale input 2 ns INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally) REFP Output Voltage V REFP - VCOM 0.256 V REFN Output Voltage V REFN - VCOM -0.256 V COM Output Voltage V COM VDD / 2 - 0.15 VDD / 2 VDD / 2 + 0.15 V Differential Reference Output V REF VREFP - VREFN 0.512 V Differential Reference Output Temperature Coefficient VREFTC ±30 ppm/ °C Maximum REFP/REFN/COM Source Current ISOURCE 2m A Maximum REFP/REFN/COM Sink Current ISINK 2m A BUFFERED EXTERNAL REFERENCE (VREFIN = 1.024V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage V REFIN 1.024 V COM Output Voltage V COM VDD / 2 - 0.15 VDD / 2 VDD / 2 + 0.15 V Differential Reference Output V REF VREFP - VREFN 0.512 V Maximum REFP/REFN/COM Source Current ISOURCE 2m A

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum REFP/REFN/COM Sink Current ISINK 2m A REFIN Input Resistance >500 k Ω REFIN Input Current -0.7 µA UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied REFP Input Voltage V REFP - VCOM 0.256 V REFN Input Voltage V REFN - VCOM -0.256 V COM Input Voltage V COM VDD / 2 V Differential Reference Input Voltage VREF VREFP - VREFN 0.512 V REFP Input Resistance R REFP Measured between REFP and COM 4 k Ω REFN Input Resistance R REFN Measured between REFN and COM 4 k Ω DIGITAL INPUTS (CLK, PD0, PD1) CLK 0.7 x VDD Input High Threshold V IH PD0, PD1 0.7 x OVDD V CLK 0.3 x VDD Input Low Threshold V IL PD0, PD1 0.3 x OVDD V Input Hysteresis V HYST 0.1 V CLK at GND or VDD ±5Digital Input Leakage Current DI IN PD0 and PD1 at OGND or OVDD ±5 µA Digital Input Capacitance DC IN 5p F DIGITAL OUTPUTS (D7–D0, A/B) Output Voltage Low V OL ISINK = 200µA 0.2 x OVDD V Output Voltage High V OH ISOURCE = 200µA 0.8 x OVDD V Tri-State Leakage Current I LEAK ±5 µA Tri-State Output Capacitance C OUT 5p F POWER REQUIREMENTS Analog Supply Voltage V DD 2.7 3.0 3.6 V Digital Output Supply Voltage OV DD 1.8 V DD V MAX1191 Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, f CLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Normal operating mode, fIN = 1.875MHz at -0.5dB FS, CLK input from GND to VDD 4.0 5.0 Idle mode (tri-state), fIN = 1.875MHz at - 0.5dB FS, CLK input from GND to VDD 4.0 Standby mode, CLK input from GND to V DD 2.2 mA Analog Supply Current I DD Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 0.1 5.0 µA Normal operating mode, fIN = 1.875MHz at -0.5dB FS, CL ≈ 10pF 1.0 mA Idle mode (tri-state), DC input, CLK = GND or VDD, PD0 = OVDD, PD1 = OGND 0.1 5.0 Standby mode, DC input, CLK = GND or VDD, PD0 = OGND, PD1 = OVDD 0.1 Digital Output Supply Current (Note 3) IODD Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 0.1 5.0 µA TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid tDOA 50% of C LK to 50% of d ata, Fi g ur e 5 ( N ote 4) 1 6 8.5 ns CLK Fall to CHB Output Data Valid tDOB 50% of C LK to 50% of d ata, Fi g ur e 5 ( N ote 4) 1 6 8.5 ns CLK Rise/Fall to A/B Rise/Fall Time tDA/B 50% of C LK to 50% of A/B, Fi g ur e 5 ( N ote 4) 1 6 8.5 ns PD1 Rise to Output Enable t EN PD0 = OVDD 5n s PD1 Fall to Output Disable t DIS PD0 = OVDD 5n s CLK Duty Cycle 50 % CLK Duty-Cycle Variation ±10 % Wake-Up Time from Shutdown Mode tWAKE, SD (Note 5) 20 µs Wake-Up Time from Standby Mode tWAKE, ST (Note 5) 5.5 µs Digital Output Rise/Fall Time 20% to 80% 2 ns INTERCHANNEL CHARACTERISTICS Crosstalk Rejection fIN,X = 1.875MHz at -0.5dB FS, fIN,Y = 0.3MHz at -0.5dB FS (Note 6) -75 dB Amplitude Matching f IN = 1.875MHz at -0.5dB FS (Note 7) ±0.03 dB Phase Matching f IN = 1.875MHz at -0.5dB FS (Note 7) ±0.03 Degrees ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, f CLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1191 toc01 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 1.000747MHz fINB = 3.020553MHz AINA = AINB = -0.5dB FS fINBHD3HD2 FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1191 toc02 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 1.000747MHz fINB = 3.020553MHz AINA = AINB = -0.5dB FS fINA HD3 HD2 FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1191 toc03 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 3.020553MHz fINB = 1.000747MHz AINA = AINB = -0.5dB FS fINB HD3HD2 FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1191 toc04 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 3.020553MHz fINB = 1.000747MHz AINA = AINB = -0.5dB FS fINAHD3HD2 TWO-TONE IMD PLOT (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1191 toc05 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fIN2fIN1 fCLK = 7.500567MHz fIN1 = 1.8MHz fIN2 = 2.3MHz AIN = -7dB FS Typical Operating Characteristics (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, f CLK = 7.5MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the amplitude of the digital output. SNR and THD are calculated using HD2 through HD6. Note 3: The power consumption of the output driver is proportional to the load capacitance (CL). Note 4: Guaranteed by design and characterization. Not production tested. Note 5: SINAD settles to within 0.5dB of its typical value. Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as power ratio of the first and second channel FFT test tone bins. Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and phase of the fundamental bin on the calculated FFT.

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) MAX1191 toc06 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 1.000747MHz fINB = 3.020553MHz AINA = AINB = -0.5dB FS fINBHD3HD2 FFT PLOT CHANNEL B (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) MAX1191 toc07 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 1.000747MHz fINB = 3.020553MHz AINA = AINB = -0.5dB FS fINA HD3HD2 FFT PLOT CHANNEL B (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) MAX1191 toc09 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 3.020553MHz fINB = 1.000747MHz AINA = AINB = -0.5dB FS fINA HD3HD2 FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) MAX1191 toc08 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fCLK = 7.500567MHz fINA = 3.020553MHz fINB = 1.000747MHz AINA = AINB = -0.5dB FS fINB HD3HD2 TWO-TONE IMD PLOT (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD) MAX1191 toc10 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -80 -70 -60 -50 -40 -30 -20 -10 -90 04 . 0 fIN2fIN1 fCLK = 7.500567MHz fIN1 = 1.8MHz fIN2 = 2.3MHz AIN = -7dB FS Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY MAX1191 toc11 ANALOG INPUT FREQUENCY (MHz) SNR (dB) 01 0 0 CHANNEL A CHANNEL B SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY MAX1191 toc12 ANALOG INPUT FREQUENCY (MHz) SNR (dB) 0 100 CHANNEL A CHANNEL B TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1191 toc13 ANALOG INPUT FREQUENCY (MHz) THD (dB) -80 -75 -70 -65 -55 -60 -50 -45 -85 0 100 CHANNEL A CHANNEL B SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1191 toc14 ANALOG INPUT FREQUENCY (MHz) SFDR (dB) 0 100 CHANNEL A CHANNEL B Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER MAX1191 toc15 ANALOG INPUT POWER (dB FS) SNR (dB) -10 -5-15-25 -20 -30 0 fIN = 2.017059MHz SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER MAX1191 toc16 ANALOG INPUT POWER (dB FS) SINAD (dB) -10-20 -30 0 fIN = 2.017059MHz TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER MAX1191 toc17 ANALOG INPUT POWER (dB FS) THD (dBc) -10 -5-15-25 -20 -60 -70 -50 -40 -30 -30 0 fIN = 2.017059MHz SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER MAX1191 toc18 ANALOG INPUT POWER (dB FS) SFDR (dBc) -10 -5-15-25 -20 -30 0 fIN = 2.017059MHz Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE MAX1191 toc19 fCLK (MHz) SNR (dB) 15105 02 0 fIN = 2.017059MHz SIGNAL-TO-NOISE AND DISTORTION vs. SAMPLING RATE MAX1191 toc20 fCLK (MHz) SINAD (dB) 15105 02 0 fIN = 2.017059MHz TOTAL HARMONIC DISTORTION vs. SAMPLING RATE MAX1191 toc21 fCLK (MHz) THD (dBc) 15105 -75 -70 -65 -60 -55 -50 -80 02 0 fIN = 2.017059MHz SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE MAX1191 toc22 fCLK (MHz) SFDR (dBc) 15105 02 0 fIN = 2.017059MHz Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE MAX1191 toc23 CLOCK DUTY CYCLE (%) SNR (dB) 555045 40 60 fIN = 2.017059MHz SIGNAL-TO-NOISE AND DISTORTION vs. CLOCK DUTY CYCLE MAX1191 toc24 CLOCK DUTY CYCLE (%) SINAD (dB) 555045 40 60 fIN = 2.017059MHz TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE MAX1191 toc25 CLOCK DUTY CYCLE (%) THD (dBc) 555045 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -80 40 60 fIN = 2.017059MHz SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE MAX1191 toc26 CLOCK DUTY CYCLE (%) SFDR (dBc) 555045 40 60 fIN = 2.017059MHz Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY MAX1191 toc31 ANALOG INPUT FREQUENCY (MHz) GAIN (dB) 10010 -10 1 1000 SMALL-SIGNAL BANDWIDTH -20dB FS FULL-POWER BANDWIDTH -0.5dB FS VDD (V) REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1191 toc32 VREFP - VREFN (V) 0.5105 0.5110 0.5115 0.5120 0.5125 0.5130 0.5100 VDD = VREFIN TEMPERATURE (°C) 603510-15-40 85 REFERENCE VOLTAGE vs. TEMPERATURE MAX1191 toc33 VREFP - VREFN (V) 0.5105 0.5110 0.5115 0.5120 0.5125 0.5130 0.5100 VDD = VREFIN INTEGRAL NONLINEARITY MAX1191 toc27 DIGITAL OUTPUT CODE INL (LSB) 224192128 16064 9632 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 -0.5 02 5 6 DIFFERENTIAL NONLINEARITY MAX1191 toc28 DIGITAL OUTPUT CODE DNL (LSB) 224192128 16064 9632 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 OFFSET ERROR vs. TEMPERATURE MAX1191 toc29 TEMPERATURE (°C) OFFSET ERROR (% FS) 603510-15 0.30 0.25 0.20 0.15 0.10 0.05 -0.05 -0.10 -40 85 VREFIN = 1.024V CHANNEL B CHANNEL A -0.05 0.05 0.10 0.20 0.15 0.25 0.30 -0.10 GAIN ERROR vs. TEMPERATURE MAX1191 toc30 TEMPERATURE (°C) GAIN ERROR (% FS) 603510-15-40 85 VREFIN = 1.024V CHANNEL B CHANNEL A Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC SUPPLY CURRENT vs. INPUT FREQUENCY MAX1191 toc34 fIN (MHz) DIGITAL SUPPLY CURRENT (mA) ANALOG SUPPLY CURRENT (mA) 321 0.5 0.6 0.7 0.8 0.9 0.4 3.9 4.0 4.1 4.2 4.3 3.8 DIGITAL SUPPLY CURRENT ANALOG SUPPLY CURRENT SUPPLY CURRENT vs. SAMPLING RATE MAX1191 toc35 fCLK (MHz) SUPPLY CURRENT (mA) 15105 A: ANALOG SUPPLY CURRENT (IDD) - INTERNAL AND BUFFERED EXTERNAL REFERENCE MODES B: ANALOG SUPPLY CURRENT (I DD) - UNBUFFERED EXTERNAL REFERENCE MODE C: DIGITAL SUPPLY CURRENT (IODD) - ALL REFERENCE MODES 02 0 A B C fIN = 2.017059MHz Pin Description PIN NAME FUNCTION 1 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. 2 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. 3, 5, 10 GND Analog Ground. Connect all GND pins together.

4 CLK Converter Clock Input

6 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. 7 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. 8, 9, 28 V DD Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.

11 OGND Output Driver Ground

12 OV DD

Output Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 13 D7 Tri-State Digital Output. D7 is the most significant bit (MSB).

14 D6 Tri-State Digital Output

15 D5 Tri-State Digital Output

16 D4 Tri-State Digital Output

17 A/ B Channel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data (A/B = 0) is present on the output.

18 D3 Tri-State Digital Output

19 D2 Tri-State Digital Output

20 D1 Tri-State Digital Output

21 D0 Tri-State Digital Output. D0 is the least significant bit (LSB). 22 PD1 Power-Down Digital Input 1. See Table 3. Typical Operating Characteristics (continued) (VDD = 3.0V, OV DD = 1.8V, V REFIN = VDD (internal reference), C L ≈ 10pF at digital outputs, differential input at -0.5dB FS, f CLK = 7.500567MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.)

through the pipeline stages every half-clock cycle. 5.5 clock cycles for channel B. codes. Figure 2 shows the MAX1191 functional diagram. 23 PD0 Power-Down Digital Input 0. See Table 3. 24 REFIN Reference Input. Internally pulled up to V DD. 25 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. — EP Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND.

1.5 BITS

Figure 1. Pipeline Architecture—Stage Blocks Figure 2. MAX1191 Functional Diagram

DD/2) for optimum performance. MAX1191 provides three modes of reference operation. REFN, and COM each with a 0.33µF capacitor. VDD/2 + V REFIN /4, and V REFN = V DD/2 - V REFIN /4. capacitor. Bypass REFIN to GND with a 0.1µF capacitor. each with a 0.33µF capacitor. mode, see the Applications Information section. Figure 4. Unbuffered External Reference Mode Impedance each with a 0.33µF capacitor. 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. REFN, and COM each with a 0.33µF capacitor. Table 1. Reference Modes

word is placed on the digital outputs. Table 2. Output Codes vs. Input Voltage Table 3. Power Logic

pled signal source) and a high-speed ADC. IN filters high-frequency noise. DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT. VISHAY'S 4R MODEL NUMBER 300197. Figure 7. DC-Coupled Differential Input Driver

mance and minimizing intersymbol interference. GND with a 0.33µF ceramic capacitor. output driver ground (OGND) on the ADC ’s package. all signal lines short and free of 90° turns. Figure 12. Typical QAM Receiver Application

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: where V 1 is the fundamental amplitude, and V 2–V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal compo- nent) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation prod- ucts are (f1 ±f2), (2 x f1), (2 x f2), (2 x f1 ±f2), (2 x f2 ±f1). The individual input tone levels are at -7dB FS. Third-Order Intermodulation (IM3) IM3 is the power of the worst third-order intermodula- tion product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The third-order intermodulation products are (2 x f1 ±f2), (2 x f2 ±f1). The individual input tone levels are at -7dB FS. Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supplies are moved ±5%. Small-Signal Bandwidth A small -20dB FS analog input signal is applied to an ADC in such a way that the signal ’s slew rate does not limit the ADC ’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the track/hold (T/H) performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dB FS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as full- power input bandwidth frequency. THD VVVVV V log =× ++++ Chip Information TRANSISTOR COUNT: 7925 PROCESS: CMOS

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/packages.) QFN THIN.EPS (ND-1) X e e D C PIN # 1 I.D. (NE-1) X e E/2 E 0.08 C 0.10 C A A1 A3 DETAIL A

0.15 C B

0.15 C A

DOCUMENT CONTROL NO. 21-0140 PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm PROPRIETARY INFORMATION APPROVAL TITLE: C REV. E2/2

0.10 M C A B

PIN # 1 I.D. b 0.35x45 L D/2 D2/2 LC LC e e LC CL k k LL

Ultra-Low-Power, 7.5Msps, Dual 8-Bit ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/packages.) 21-0140 REV.DOCUMENT CONTROL NO.APPROVAL PROPRIETARY INFORMATION TITLE: COMMON DIMENSIONS EXPOSED PAD VARIATIONS 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. NOTES: 10. WARPAGE SHALL NOT EXCEED 0.10 mm. C PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm