11696

11696 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 19

Technical content

Features

n Rail-to-Rail Voltage Output n Power-on Reset to Zero Volts Output n SYNC Interrupt Facility n Wide power supply range (+2.7V to +5.5V) n Small Packages n Power Down Feature Key Specifications n Resolution 12 bits n DNL +0.25, -0.15 LSB (typ) n Output Settling Time 8 µs (typ) n Zero Code Error 4 mV (typ) n Full-Scale Error −0.06 %FS (typ) n Power Consumption — Normal Mode 0.64mW (3.6V) / 1.43mW (5.5V) typ — Pwr Down Mode 0.14µW (3.6V) / 0.39µW (5.5V) typ

Applications

n Battery-Powered Instruments n Digital Gain and Offset Adjustment n Programmable Voltage & Current Sources n Programmable Attenuators Pin Configuration 20114901 20114902

Ordering Information

Order Numbers Temperature Range Package Top Mark DAC121S101CIMM −40˚C ≤ TA ≤ +105˚C MSOP X60C DAC121S101CIMMX −40˚C ≤ TA ≤ +105˚C MSOP Tape-and-Reel X60C DAC121S101CIMK −40˚C ≤ TA ≤ +105˚C TSOT X61C DAC121S101CIMKX −40˚C ≤ TA ≤ +105˚C TSOT Tape-and-Reel X61C DAC121S101EVAL Evaluation Board SPI™ is a trademark of Motorola, Inc. June 2005 DAC121S101 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output © 2005 National Semiconductor Corporation DS201149 www.national.com

(SOT-23) Pin No. MSOP Pin No. Symbol Description 14 V OUT DAC Analog Output Voltage. 2 8 GND Ground reference for all on-chip circuitry. 31V A Power supply and Reference input. Should be decoupled to GND.

47 D IN

Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. 5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. 6 5 SYNC Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2, 3 NC No Connect. There is no internal connection to these pins. DAC121S101 www.national.com 2

(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, V A 6.5V Voltage on any Input Pin −0.3V to (V A + 0.3V) Input Current at Any Pin (Note 3) 10 mA Package Input Current (Note 3) 20 mA Power Consumption at T A = 25˚C See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model 2500V 250V Soldering Temperature, Infrared,

10 Seconds (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C Operating Ratings (Notes 1, 2) Operating Temperature Range −40˚C ≤ TA ≤ +105˚C Supply Voltage, VA +2.7V to 5.5V Any Input Voltage (Note 7) −0.1 V to (V A + 0.1 V) Output Load 0 to 1500 pF SCLK Frequency Up to 30 MHz Package Thermal Resistances Package θJA 8-Lead MSOP 240˚C/W 6-Lead TSOT 250˚C/W

Electrical Characteristics

Values shown in this table are design targets and are subject to change before product release. The following specifica- tions apply for V A = +2.7V to +5.5V, R L =2 kΩ to GND, CL = 200 pF to GND, f SCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for T MIN ≤ TA ≤ TMAX: all other limits T A = 25˚C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) STATIC PERFORMANCE Resolution 12 Bits (min) Monotonicity 12 Bits (min) INL Integral Non-Linearity Over Decimal codes 48 to 4047 ±2.6 ±8 LSB (max) DNL Differential Non-Linearity VA = 2.7V to 5.5V +0.25 +1.0 LSB (max) −0.15 −0.7 LSB (min) VA = 4.5V to 5.5V (Note 10) ±0.11 ±0.5 LSB (max) ZE Zero Code Error I OUT =0 + 4 +15 mV (max) FSE Full-Scale Error I OUT = 0 −0.06 −1.0 %FSR (max) GE Gain Error All ones Loaded to DAC register −0.10 ±1.0 %FSR ZCED Zero Code Error Drift −20 µV/˚C TC GE Gain Error Tempco VA = 3V −0.7 ppm/˚C VA = 5V −1.0 ppm/˚C OUTPUT CHARACTERISTICS Output Voltage Range (Note 10) 0 VA V (min) V (max) ZCO Zero Code Output VA = 3V, IOUT = 10 µA 1.8 mV VA = 3V, IOUT = 100 µA 5.0 mV VA = 5V, IOUT = 10 µA 3.7 mV VA = 5V, IOUT = 100 µA 5.4 mV FSO Full Scale Output VA = 3V, IOUT = 10 µA 2.997 V VA = 3V, IOUT = 100 µA 2.990 V VA = 5V, IOUT = 10 µA 4.995 V VA = 5V, IOUT = 100 µA 4.992 V Maximum Load Capacitance RL = ∞ 1500 pF RL =2 kΩ 1500 pF DC Output Impedance 1.3 Ohm DAC121S101 www.national.com3

Electrical Characteristics (Continued) Values shown in this table are design targets and are subject to change before product release. The following specifica- tions apply for V A = +2.7V to +5.5V, R L =2 kΩ to GND, CL = 200 pF to GND, f SCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for T MIN ≤ TA ≤ TMAX: all other limits T A = 25˚C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) IOS Output Short Circuit Current VA = 5V, VOUT = 0V, Input code = FFFh −63 mA VA = 3V, VOUT = 0V, Input code = FFFh −50 mA VA = 5V, VOUT = 5V, Input code = 000h 74 mA VA = 3V, VOUT = 3V, Input code = 000h 53 mA LOGIC INPUT IIN Input Current (Note 10) ±1 µA (max) VIL Input Low Voltage (Note 10) VA =5 V 0.8 V (max) VA =3 V 0.5 V (max) VIH Input High Voltage (Note 10) VA =5 V 2.4 V (min) VA =3 V 2.1 V (min) CIN Input Capacitance (Note 10) 3 pF (max) POWER REQUIREMENTS IA Supply Current (output unloaded) Normal Mode fSCLK =3 0M H z VA = 5.5V 260 312 µA (max) VA = 3.6V 177 217 µA (max) Normal Mode fSCLK =2 0M H z VA = 5.5V 224 279 µA (max) VA = 3.6V 158 197 µA (max) Normal Mode fSCLK =0 VA = 5.5V 153 µA (max) VA = 3.6V 118 µA (max) All PD Modes, fSCLK =3 0M H z VA = 5.0V 84 µA (max) VA = 3.0V 42 µA (max) All PD Modes, fSCLK =2 0M H z VA = 5.0V 56 µA (max) VA = 3.0V 28 µA (max) All PD Modes, fSCLK = 0 (Note 10) VA = 5.5V 0.07 1.0 µA (max) VA = 3.6V 0.04 1.0 µA (max) PC Power Consumption (output unloaded) Normal Mode fSCLK =3 0M H z VA = 5.5V 1.43 1.72 mW (max) VA = 3.6V 0.64 0.78 mW (max) Normal Mode fSCLK =2 0M H z VA = 5.5V 1.23 1.53 mW (max) VA = 3.6V 0.57 0.71 mW (max) Normal Mode fSCLK =0 VA = 5.5V 0.84 µW (max) VA = 3.6V 0.42 µW (max) All PD Modes, fSCLK =3 0M H z VA = 5.0V 0.42 µW (max) VA = 3.0V 0.13 µW (max) All PD Modes, fSCLK =2 0M H z VA = 5.0V 0.28 µW (max) VA = 3.0V 0.08 µW (max) All PD Modes, fSCLK = 0 (Note 10) VA = 5.5V 0.39 5.5 µW (max) VA = 3.6V 0.14 3.6 µW (max) IOUT /I A Power Efficiency I LOAD = 2mA VA =5 V 9 1 % VA =3 V 9 4 % DAC121S101 www.national.com 4

A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifica- tions apply for V A = +2.7V to +5.5V, R L =2 kΩ to GND, CL = 200 pF to GND, f SCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for T MIN ≤ TA ≤ TMAX: all other limits T A = 25˚C, unless otherwise specified. Symbol Parameter Conductions Typical Limits Units (Limits) fSCLK SCLK Frequency 30 MHz (max) ts Output Voltage Settling Time (Note 10) 400h to C00h code change, RL =2 kΩ CL ≤ 200 pF 8 10 µs (max) CL = 500 pF 12 µs 00Fh to FF0h code change, RL =2 kΩ CL ≤ 200 pF 8 µs CL = 500 pF 12 µs SR Output Slew Rate 1 V/µs Glitch Impulse Code change from 800h to 7FFh 12 nV-sec Digital Feedthrough 0.5 nV-sec t WU Wake-Up Time VA = 5V 1.6 µs VA = 3V 1.9 µs 1/fSCLK SCLK Cycle Time 33 ns (min) tH SCLK High time 5 13 ns (min) tL SCLK Low Time 5 13 ns (min) tSUCL Set-up Time SYNC to SCLK Rising Edge −15 0 ns (min) tSUD Data Set-Up Time 2.5 5 ns (min) tDHD Data Hold Time 2.5 4.5 ns (min) tCS SCLK fall to rise of SYNC VA =5 V 0 3 ns (min) VA =3 V − 2 1 ns (min) tSYNC SYNC High Time 2.7 ≤ VA ≤ 3.6 9 20 ns (min) 3.6 ≤ VA ≤ 5.5 5 10 ns (min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than V A), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two . Note 4: The absolute maximum junction temperature (T Jmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by T Jmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula P DMAX = (TJmax − TA)/ θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven be yond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to V A + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions. 20114904 Note 8: To guarantee accuracy, it is required that V A be well bypassed. Note 9: Typical figures are at T J = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production. DAC121S101 www.national.com5

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is V REF /4 0 9 6=V A / 4096. DIGITAL FEEDTHROUGH is a measure of the energy in- jected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is mea- sured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of V A x 4095 / 4096. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full- Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is L S B=V REF /2 n where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the DAC121S101. MAXIMUM LOAD CAPACITANCE is the maximum capaci- tance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of V POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. WAKE-UP TIME is the time for the output to settle to within 1/2 LSB of the final value after the device is commanded to the active mode from any of the power down modes. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. DAC121S101 www.national.com 6

Typical Performance Characteristics fSCLK = 30 MHz, T A = 25C, Input Code Range 48 to 4047, unless otherwise stated DNL at VA = 3.0V DNL at V A = 5.0V 20114952 20114953 INL at VA = 3.0V INL at V A = 5.0V 20114954 20114955 TUE at VA = 3.0V TUE at V A = 5.0V 20114956 20114957 DAC121S101 www.national.com 8

Typical Performance Characteristics fSCLK = 30 MHz, T A = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) DNL vs. VA INL vs. VA 20114922 20114923 3V DNL vs. f SCLK 5V DNL vs. f SCLK 20114950 20114951 3V DNL vs. Clock Duty Cycle 5V DNL vs. Clock Duty Cycle 20114924 20114925 DAC121S101 www.national.com9

Typical Performance Characteristics fSCLK = 30 MHz, T A = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) 3V DNL vs. Temperature 5V DNL vs. Temperature 20114926 20114927 3V INL vs. f SCLK 5V INL vs. f SCLK 20114928 20114929 3V INL vs. Clock Duty Cycle 5V INL vs. Clock Duty Cycle 20114930 20114931 DAC121S101 www.national.com 10

Typical Performance Characteristics fSCLK = 30 MHz, T A = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) 3V INL vs. Temperature 5V INL vs. Temperature 20114932 20114933 Zero Code Error vs. f SCLK Zero Code Error vs. Clock Duty Cycle 20114934 20114935 Zero Code Error vs. Temperature Full-Scale Error vs. f SCLK 20114936 20114937 DAC121S101 www.national.com11

Typical Performance Characteristics fSCLK = 30 MHz, T A = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature 20114938 20114939 Supply Current vs. V A Supply Current vs. Temperature 20114944 20114945 5V Glitch Response Power-On Reset 20114946 20114947 DAC121S101 www.national.com 12

Typical Performance Characteristics fSCLK = 30 MHz, T A = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) 3V Wake-Up Time 5V Wake-Up Time 20114948 20114949 DAC121S101 www.national.com13

1.0 Functional Description

1.1 DAC SECTION

1.2 RESISTOR STRING

tion guarantees that the DAC is monotonic.

1.3 OUTPUT AMPLIFIER

1.4 SERIAL INTERFACE

gram for information on a write sequence. A write sequence begins by bringing the SYNC line low. the 16-bit serial input register on the falling edges of SCLK. falling edge of SYNC can initiate the next write cycle. quences to minimize power consumption.

1.5 INPUT SHIFT REGISTER

falling edge of SCLK. See Timing Diagram, Figure 2.

1.6 POWER-ON RESET

there until a valid write sequence is made to the DAC.

1.7 POWER-DOWN MODES

TABLE 1. Modes of Operation or is in a high impedance state, as described in Table 1. FIGURE 3. DAC Resistor String FIGURE 4. Input Register Contents

1.0 Functional Description (Continued)

2.0 Applications Information

The simplicity of the DAC121S101 implies ease of use. have essentially zero PSRR (Power Supply Rejection Ratio).

2.1 DSP/MICROPROCESSOR INTERFACING

2.1.1 ADSP-2101/ADSP2103 Interfacing

comes from a bit-programmable pin on the microcontroller. taken low when data is to transmitted to the DAC121S101. first while the DAC121S101 requires data with the MSB first. figure), similar to the 80C51/80L51.

2.1.4 Microwire Interface

rising edges of the SCLK signal.

2.2 USING REFERENCES AS POWER SUPPLIES

their power supply voltage as a reference voltage. also be used for the power supply of the DAC121S101.

2.2.1 LM4130

FIGURE 5. ADSP-2101/2103 Interface FIGURE 6. 80C51/80L51 Interface FIGURE 7. 68HC11 Interface FIGURE 8. Microwire Interface

2.2.2 LM4050

2.2.3 LP3985

5-pin SOT23 and 5-bump micro SMD packages.

2.2.4 LP2980

is available in 3.0V, 3.3V and 5V versions, among others. FIGURE 9. The LM4130 as a power supply FIGURE 10. The LM4050 as a power supply FIGURE 11. Using the LP3985 regulator FIGURE 12. Using the LP2980 regulator

2.3 BIPOLAR OPERATION

TABLE 2. Some Rail-to-Rail Amplifiers

2.4 LAYOUT, GROUNDING, AND BYPASSING

these planes should be located in the same board layer. ways have a continuous return path below their traces. clock and data lines should have controlled impedances. FIGURE 13. Bipolar Operation

Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead MSOP Order Numbers DAC121S101CIMM 6-Lead TSOT Order Numbers DAC121S101CIMK DAC121S101 www.national.com 18

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DAC121S101 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output