1127AS-2R2M

SC284P SEMTECH | Alldatasheet

Document overview

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Technical content

Features

VIN Range — 2.75 – 5.5V VOUT Selectable — .0 - 3.3V Up to 2A Output Current for Each Channel Package with Ultra-Small Footprint : 3 x 3 x 0.6(mm) Switching Frequency — 2.5MHz Efficiency Up to 94% High Light-load Efficiency via Automatic PSAVE Mode Low Output Noise in CCM Excellent Transient Response Start Up into Pre-Biased Output 00% Duty-Cycle Low Dropout Operation Shutdown Current — <µA Internal Soft-Start Input Under-Voltage Lockout Output Over-Voltage, Current Limit Protection Over-Temperature Protection VOUT Further Adjustable Using External Resistors PGOOD Feature Lead-free, Halogen-free, and RoHS/WEEE Compliant

Applications

Wireless Access Point/Router/Modem Femtocell Set-Top Box Point-Of-Sale Projector

Description

The SC284P is a dual channel 2A synchronous step-down regulator designed to operate with an input voltage range of 2.75 to 5.5 Volts. Each channel offers seven pre-determined output voltages via three control pins programmable from .0 to 3.3 Volts. The control pins allow for on-the-fly voltage changes, enabling system designers to implement dynamic power savings. The SC284P is also capable of adjusting the output voltage via an external resistor divider. The SC284P is optimized for maximum efficiency over a wide range of load currents. During full load operation, the device operates in PWM mode with fixed 2.5MHz oscillator frequency, allowing the use of small surface mount external components. As the load decreases, the regulator will transition into Power Save mode maintaining high efficiency. Connecting CTL0 — CTL2 to logic low forces the device into shutdown mode reducing the supply current to less than µA. Connecting any of the control pins to logic high enables the converter and sets the output voltage according to Table . Other features include under- voltage lockout, soft-start to limit inrush current, and over-temperature protection. Typical Application Circuit Revision 2. SC284P CTL0A CTL1A CTL2A PGOODA CTL0A CTL1A CTL2A PGOODA CTL0B CTL1B CTL2B PGOODB CTL0B CTL1B CTL2B PGOODB AVINA VINA CAVINA 10nF RAVINA 1Ω PVINA AVINB VINB CAVINB 10nF RAVINB 1Ω PVINB PGNDBAGNDB PGNDA AGNDA CINA 10µF CINB 10µF COUTA 22µF LXA VOUTA VOUTA LA 2.2µH LB 2.2µH COUTB 22µF LXB VOUTB VOUTB

Pin Configuration Ordering Information Device Package SC284PULTRC()(2) 3 x 3 x 0.6(mm) MLPQ-UT20 SC284PEVB Evaluation Board Notes: () Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. Table 1 – Output Voltage Settings CTL2[A/B] CTL1[A/B] CTL0[A/B] Output Voltage 0 0 0 Disabled 0 0 .0V 0 0 .V 0 .2V 0 0 .5V 0 .8V 0 2.5V 3.3V 3 x 3 x 0.6(mm) MLPQ-UT20 θJA= 40°C/W Marking Information 284P = Part Number Code yyww = Date Code xxxx = Semtech Lot Number TOP VIEW T PVINA PGOODA AGNDA AVINA 6 7 8 9 10 PGNDB PVINB PGOODB AGNDB AVINB CTL0B15 1617181920 CTL0A LXB VOUTB CTL2A CTL1A CTL1B PGNDA LXA CTL2B VOUTA

Electrical Characteristics

Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. Notes: () Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. (2) Tested according to JEDEC standard JESD22-A4-B. Unless specified: VINA= VINB= 5.0V, VOUTA= VOUTB= .5V, CINA= CINB=0µF, COUTA=COUTB= 22µF, L= 2.2µH, -40°C ≤ (TA = TJ )≤ +25 °C. Unless otherwise noted typical values are TA= +25 °C. Parameter Symbol Conditions Min Typ Max Units Input Voltage Range VINA/B 2.75 5.5 V Under-Voltage Lockout UVLO Rising VINA ,VINB 2.55 2.65 2.75 V Hysteresis 200 mV Quiescent Current IQ Channel A & B, PWM mode excluding IOUT, per channel 6 mA IOUT = 0mA, CTLX = VIN 60 µA Shutdown Current ISHDN CTL0-2= GND, Per channel 0 µA Soft-Start Time tSS Channel A & B; IOUT= 2A, VOUT =90% of final value 700 µs Output Voltage Range VOUT .0 3.3 V Output Voltage Tolerance() ΔVOUT Channel A & B; IOUT=400mA, PWM Mode -2.0 +2.0 PSAVE Mode .75 CTL Settings Regulation ΔVCTL-REG Channel A & B; Relative to VOUT at CTL=00, IOUTA=400mA; IOUTB=400mA; PWM Mode ± % Line Regulation ΔVLINE-REG Channel A & B; VIN= 2.75 – 5.5V; PWM Mode ±0.2 %/V Load Regulation ΔVLOAD-REG Channel A & B; VIN = 5.0V; IOUT=mA – 2A ±0.3 %/A Absolute Maximum Ratings Recommended Operating Conditions Thermal Information Thermal Resistance, Junction to Ambient () (°C/W) . . . . 40

Parameter Symbol Conditions Min Typ Max Units Current Limit Threshold ILIMIT Channel A & B; Peak LX current 2.25 3.0 3.75 A Oscillator Frequency fOSC Channel A & B 2.0 2.5 3.0 MHz LX Leakage Current(2) ILK(LX) Channel A & B; VIN = 5.5V; LX = 0V; CTL0-2= GND -0 - µA Channel A & B; VIN = 5.5V; LX = 5.0V; CTL0-2= GND 0 Foldback Holding Current ICL_HOLD Average LX Current, VOUT =.5V 600 mA High Side Switch Resistance(3) RDSON_P Channel A & B; ILX= 00mA, TJ= 25 °C 95 mΩ Low Side Switch Resistance RDSON_N Channel A & B; ILX= -00mA, TJ= 25 °C 65 CTLx Input Current(2) ICTL_ Channel A & B; CTL0-2=VIN or GND -2.0 2.0 µA CTLx Input High Threshold VCTLx_HI Channel A & B .6 V CTLx Input Low Threshold VCTLx_LO Channel A & B 0.4 V Impedence of PGOOD Low RPGOOD_LO 8 Ω PGOOD Threshold VPG_TH VOUT rising 90 % PGOOD Delay VPG_DLY Asserted 2 ms PGOOD= Low 20 μs VOUT Over Voltage Protection VOVP Channel A & B 5 % Thermal Shutdown Temperature(4) TSD Channel A & B 60 °C Thermal Shutdown Hysteresis(4) TSD_HYS Channel A & B 0 °C Electrical Characteristics (continued) Notes: () The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature. (2) A negative current means the current flows from the pin and a positive current means the current flows into the pin. (3) Measured from VINA/B to LXA/B. (4) Thermal shutdown protection is independent for each channel.

Efficiency vs. Load Current Total Loss (Per Channel) vs. Load Current UVLO Rising Threshold Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). UVLO Hysteresis 100 0.001 0.01 0.1 1 10 Efficiency (%) Load Current (A) VIN = 5V, VOUT = 3.3V VIN = 5V, VOUT = 1.5V VIN = 3.3V, VOUT = 1.5V Loss (mW) 1000 800 Vin=3.3V,Vo=1.5V 600 400 Vin=5V,Vo=3.3V 200 Vin=5V,Vo=1.5V 0 0.5 1.0 1.5 2.0 Load Current (A) TA=25℃ 2.60 2.62 2.64 2.66 2.68 2.70 -50 -25 0 25 50 75 100 125 150 Input Voltage (V) Ambient Temperature (0C) 170 175 180 185 190 195 200 -50 -25 0 25 50 75 100 125 150 UVLO Hysteresis (mV) Ambient Temperature (0C) Steady State (PSAVE) Operation ( IOUT=200mA) Steady State (PWM) Operation (IOUT=2A) IOUT 200mA/div 500ns/divVIN = 5V VOUT = .5V ILX 500mA/div 500ns/divVIN = 5V VLX 2V/div VOUT = .5V IOUT 2A/div ILX A/div VLX 2V/div

Load Regulation, Vout=1.0V Load Regulation, Vout=1.2V Load Regulation, Vout=1.5V Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). Load Regulation, Vout=1.8V 0.90 0.95 1.00 1.05 1.10 Output Voltage (V) Load Current (A) 1250C 250C -400C 1250C 250C -400C 1.12 1.15 1.17 1.20 1.22 1.25 1.27 Output Voltage (V) Load Current (A) 1.40 1.45 1.50 1.55 1.60 Output Voltage (V) Load Current (A) 1250C 250C -400C 1.70 1.75 1.80 1.85 1.90 Output Voltage (V) Load Current (A) 1250C 250C -400C Load Regulation, Vout=2.5V Load Regulation, Vout=3.3V 2.35 2.40 2.45 2.50 2.55 2.60 2.65 Output Voltage (V) Load Current (A) 1250C 250C -400C 3.15 3.20 3.25 3.30 3.35 3.40 3.45 Output Voltage (V) Load Current (A) 1250C 250C -400C

Line Regulation, Vout=1.0V, Iout=500mA Line Regulation, Vout=1.2V, Iout=500mA Line Regulation, Vout=1.5V, Iout=500mA Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). Line Regulation, Vout=1.8V, Iout=500mA 1250C 250C -400C 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 Output Voltage (V) Input Voltage (V) 1.14 1.16 1.18 1.20 1.22 1.24 1.26 Output Voltage (V) Inout Voltage (V) 1250C 250C -400C 1.44 1.46 1.48 1.50 1.52 1.54 1.56 1.58 Output Voltage (V) Input Voltage (V) 1250C 250C -400C 1.71 1.73 1.75 1.77 1.79 1.81 1.83 1.85 1.87 1.89 Output Voltage (V) Input Voltage (V) 1250C 250C -400C Line Regulation, Vout=2.5V, Iout=500mA Line Regulation, Vout=3.3V, Iout = 500mA 2.38 2.42 2.46 2.50 2.54 2.58 2.62 Output Voltage (V) Input Voltage (V) 1250C 250C -400C 1250C 250C -400C 3.14 3.18 3.22 3.26 3.30 3.34 3.38 3.42 3.46 Output Voltage (V) Input Voltage (V)

Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, L= 2.2uH (TOKO: 27AS-2R2M). 50us/divVIN = 5V IOUT = 0.4A to 2A 50us/divVIN = 5V IOUT = 0.4A to 2A Shutdown (Disable)(VOUT=1.5V) Start Up (Power up VIN=VCTLx) (VOUT=3.3V) VIN 2V/div 200us/divVIN = 5V IOUT = 2A VOUT V/div 200us/divVIN = 5V IOUT = 2A VOUT V/div VIN 5V/div 50us/divVIN = 5V ROUT = .65Ω(2A) VCTL 2V/div VOUT V/div Start Up (Enable) (VOUT=3.3V) VIN 5V/div Start Up (Power up VIN=VCTLx) (VOUT=1.5V) Start Up (Enable) (VOUT=1.5V) Shutdown (Disable)(VOUT=3.3V) VIN 5V/div VCTL 2V/div VOUT V/div VCTL 2V/div VOUT V/div VIN 5V/div VCTL 2V/div VIN 2V/div VOUT V/div

Switching Frequency Vs Temperature, Vout=1.0V Switching Frequency Vs Temperature, Vout=1.2V Switching Frequency Vs Temperature, Vout=1.5V Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). Switching Frequency Vs Temperature, Vout=1.8V 2.535 2.54 2.545 2.55 2.555 2.56 2.565 2.57 2.575 -40 -15 10 35 60 85 110 135 Switching Frequency (MHz) Ambient Temperature (0C) 2.535 2.54 2.545 2.55 2.555 2.56 2.565 2.57 2.575 -40 -15 10 35 60 85 110 135 Switching Frequency (MHz) Ambient Temperature (0C) 2.535 2.54 2.545 2.55 2.555 2.56 2.565 2.57 2.575 -40 -15 10 35 60 85 110 135 Switching Frequency (MHz) Ambient Temperature (0C) 2.535 2.54 2.545 2.55 2.555 2.56 2.565 2.57 2.575 -40 -15 10 35 60 85 110 135 Switching Frequency (MHz) Ambient Temperature (0C) Switching Frequency Vs Temperature, Vout=2.5V Switching Frequency vs Temperature, Vout=3.3V 2.535 2.54 2.545 2.55 2.555 2.56 2.565 2.57 2.575 -40 -15 10 35 60 85 110 135 Switching Frequency (MHz) Ambient Temperature (0C) 2.535 2.54 2.545 2.55 2.555 2.56 2.565 2.57 2.575 -40 -15 10 35 60 85 110 135 Switching Frequency (MHz) Ambient Temperature (0C)

Switching Frequency Vs Input Voltage, Vout=1.0V Switching Frequency Vs Input Voltage, Vout=1.2V Switching Frequency Vs Input Voltage, Vout=1.5V Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 27AS-2R2M). Switching Frequency Vs Input Voltage, Vout=1.8V 2.45 2.5 2.55 2.6 2.65 2.5 3 3.5 4 4.5 5 5.5 Switching Frequency (MHz) Input Voltage (V) 2.45 2.5 2.55 2.6 2.65 2.5 3 3.5 4 4.5 5 5.5 Switching Frequency (MHz) Input Voltage (V) 2.45 2.5 2.55 2.6 2.65 2.5 3 3.5 4 4.5 5 5.5 Switching Frequency (MHz) Input Voltage (V) 2.45 2.5 2.55 2.6 2.65 2.5 3 3.5 4 4.5 5 5.5 Switching Frequency (MHz) Input Voltage (V) Switching Frequency Vs Input Voltage, Vout=2.5V Switching Frequency vs Input Voltage, Vout=3.3V 2.45 2.5 2.55 2.6 2.65 2.5 3 3.5 4 4.5 5 5.5 Switching Frequency (MHz) Input Voltage (V) 2.45 2.5 2.55 2.6 2.65 2.5 3 3.5 4 4.5 5 5.5 Switching Frequency (MHz) Input Voltage (V)

Circuit Conditions: CIN= 0uF/6.3V; COUT= 22uF/6.3V, L= 2.2uH (TOKO: 27AS-2R2M). VOUT 50mV/div 20us/divVIN = 5V IOUT = 0.A to 0.4A IOUT VOUT 00mV/div 20us/div VIN = 5V IOUT = 0.4A to 2A IOUT A/div Output Hard Short (VOUT=1.5V) 200us/divVIN = 5V IOUT = 2A 200us/divVIN = 5V IOUT = 2A VOUT 00mV/div VOUT V/div 50us/divVIN = 5V IOUT = 500mA ILX A/div Transient Response (Vout=1.5V, Iout=0.1A to 0.4A) Output Voltage Ripple (VOUT=1.5V) ILX 200mA/div 200mA/div ILX A/div Transient Response (Vout=1.5V, Iout=0.4A to 2A) IOUT 200mA/div ILX A/div VOUT 50mV/div IOUT 50mA/div ILX 500mA/div us/div VOUT 20mV/div VIN = 5V IOUT = 500mA

Pin # Pin Name Pin Function PVINA Channel A — Input supply voltage for the converter power stage and internal circuitry. 2 AGNDA Ground connection for internal circuitry — connect directly to PGNDA. 3 AVINA Power supply for internal circuitry — must be connected to PVINA using an R-C filter of Ω and 0nF. 4 PGOODA Power Good indicator for channel A. When the output voltage reaches the PGOODA threshold, this pin will be open drain (after the PGOOD delay), otherwise it is pulled low internally.

5 CTL0A

Channel A — Control bit 0, see Table for decoding. This pin has a MΩ internal pull-down resistor. This resis- tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout.

6 CTLA

Channel A — Control bit , see Table for decoding. This pin has a MΩ internal pull-down resistor. This resis- tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout.

7 CTL2A

Channel A — Control bit 2, see Table for decoding. This pin has a MΩ internal pull-down resistor. This resis- tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout.

8 VOUTB Output voltage sense pin of Channel B

9 PGNDB Channel B — Ground connection for converter power stage and internal circuitry. 0 LXB Switching node of Channel B — connect an inductor between this pin and the output capacitor. PVINB Channel B — Input supply voltage for the converter power stage and internal circuitry. 2 AGNDB Ground connection for internal circuitry — connect directly to PGNDB. 3 AVINB Power supply for internal circuitry — must be connected to PVINB using an R-C filter of Ω and 0nF. 4 PGOODB Power Good indicator for channel B. When the output voltage reaches the PGOODB threshold, this pin will be open drain (after the PGOOD delay), otherwise it is pulled low internally.

5 CTL0B

Channel B — Control bit 0, see Table for decoding. This pin has a MΩ internal pulld-own resistor. This resis- tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout.

6 CTLB

Channel B — Control bit - see Table for decoding. This pin has a MΩ internal pull-down resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout.

7 CTL2B

Channel B — Control bit 2, see Table for decoding. This pin has a MΩ internal pull-down resistor. This resis- tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout.

8 VOUTA Output voltage sense pin of Channel A

9 PGNDA Channel A — Ground connection for converter power stage and internal circuitry. 20 LXA Switching node of Channel A — connect an inductor between this pin and the output capacitor. PAD Thermal pad for heatsinking purposes.

The SC284P is a two channel synchronous step-down converter. Both channels of this device are designed to operate at a fixed-frequency of 2.5MHz in CCM and provide the same current capacity of up to 2A. The switching frequency is chosen to minimize the size of the external inductor and capacitors while maintaining high efficiency. Both channels of SC284P are independent. Operation During normal operation, the PMOS FET is activated on each rising edge of the internal oscillator. The voltage feedback loop uses an internal feedback resistor divider. The period is set by the internal oscillator. The device has an internal synchronous NMOS rectifier and does not require a Schottky diode on the LX pin. Programmable Output Voltage Both channels on SC284P have seven pre-determined output voltage values which can be individually selected by programming the CTL input pins (see Table — Output Voltage Settings). Each CTL pin has an active MΩ internal pull-down resistor. The MΩ resistor is switched in circuit whenever the CTL input voltage is below the input threshold, or when the part is in under-voltage lockout. It is recommended to tie all high CTL pins together and use an external pull-up resistor to VIN if there is no enable signal, or if the enable input is an open drain/collector signal. The CTL pins may be driven by a microprocessor to allow dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. Avoid all zeros being present on the CTL pins when changing programmable output voltages as this would momentarily disable the device. SC284P is also capable of regulating a different (higher) output voltage, which is not shown in the Table , via an external resistor divider. There will be a typical 2µA current flowing into the VOUT pin. The typical schematic for an ad- justable output voltage option from the standard .0V with CTLX=[00], is shown in Figure . RFBA/B and RFB2A/B are used to adjust the desired output voltage. If the R FB2A/B current is such that the 2µA VOUT pin current can be ignored, then RFBA/B can be found by the next equation. RFB2A/B need to be low enough in value for the current through the resistor chain to be at least 20µA in order to ignore the VOUT pin current. where VOSTD is the pre-determined output voltage via the CTL pins. CFF is needed to maintain good transient response performance. The correct value of CFF can be found using the following equation. To simplify the design, it is recommended to program the desired output voltage from a standard .0V as shown in Figure with the correct C FF calculated from Equation 2. For programming the output voltage from other standard voltages, R FB, R FB2 and C FF need to be adjusted to meet Equations and 2. SC284P PGOODB CTL3B CTL2B CTL1B Enable B PGOODA CTL3A CTL2A CTL1A Enable A PGNDA PGNDB RFB1B = (VOUTB-1) x RFB2B for CTLBX = 0010 (1.0V) AVINB VINB CAVINB 0.1µF RAVINB 1Ω PVINB CINB 10µF AGNDB AVINA VINA CAVINA 0.1µF RAVINA 1Ω PVINA CINA 10µF AGNDA VOUTB COUTB LXB VOUTB L RFB2B 10kΩ CFFB RFB1B VOUTA COUTA LXA VOUTA L RFB2A 10kΩ CFFA RFB1A RFB1A = (VOUTA-1) x RFB2A for CTLAX = 0010 (1.0V) PGOODA PGOODB Figure 1 — Output Voltage Programming

Applications Information (continued) Protection Features The SC284P provides the following protection features: Current Limit Over-Voltage Protection Soft-Start Thermal Shutdown Current Limit The internal PMOS power device in the switching stage is protected by a current limit feature. If the inductor current is above the PMOS current limit for 6 consecutive cycles, the part enters foldback current limit mode and the output current is limited to the current limit holding current (I CL_HOLD) of a few hundred milliampere. Under this condition, the output voltage will be the product of ICL_HOLD and the load resistance. The current limit holding current will decrease when the output voltage increases. The load presented must fall below the current limit holding current for the part to exit foldback current limit mode. Figure 4 shows how the typical current limit holding current varies with output voltage. The SC284P is capable of sustaining an indefinite short circuit without damage and will resume normal operation when the fault is removed. The foldback current limit mode is disabled during soft-start. Figure 4— Typical Current Limit Holding Current vs. Output Voltage Over-Voltage Protection In the event of a 5% over-voltage on the output, the PWM drive is disabled leaving the LX pin floating.

• ••• Soft-Start Soft-start is activated once VIN reaches the UVLO and one or more CTL pins are set high to enable the part. A thermal shutdown event will also activate the soft-start sequence. Soft-start controls the maximum current during startup thus limiting inrush current. The PMOS current limit is stepped through four soft-start levels o f approximately 20%, 25%, 40%, & 00%. Each step is maintained for 400μs following an internal reference start up duration of 00μs giving a total nominal startup period of 700μs. During startup, the chip operates by controlling the inductor current swings between 0A and current limit. If at any time VOUT reaches 86% of the target or at the end of the soft- start period, the SC284P will switch to PWM mode operation. The SC284P is capable of starting up into a pre-biased output. Shut Down When all CTL pins of a channel are low, the corresponding channel will be disabled, drawing less than μA from that input power supply. The internal switches and bandgap voltage will be immediately turned off. Thermal Shutdown The device has a thermal shutdown feature to protect the SC284P if the junction temperature exceeds 60°C. During thermal shutdown, the on-chip power devices are disabled, tri-stating the LX output. When the temperature drops by 0°C, it will initiate a soft-start cycle to resume normal operation. Inductor Selection The SC284P converter has internal loop compensation. The compensation is designed to work with an output filter corner frequency of less than 40kHz for a V IN of 5V and 50KHz for a V IN of 3.3V over any operating condition. The corner frequency of the output filter is shown in the following equation. Values outside this range may lead to instability, malfunc- tion, or out-of-specification performance. Current Limit Holding Current over Vout 100 150 200 250 300 Output Voltage (V) Current Limit Holding Current (mA) TA= 25° C VIN= 5.0V VIN= 3.6V VIN= 3.3V OUT C CL2 uS

Applications Information (continued) In general, the inductance is chosen by making the inductor ripple current to be less than 30% of maximum load current. When choosing an inductor, it is important to consider the change in inductance with DC bias current. The inductor saturation current is specified as the current at which the inductance drops a specific percentage from the nominal value. This is approximately 30%. Except for short-circuit or other fault conditions, the peak current must always be less than the saturation current specified by the manufacturer. The peak current is the maximum load current plus one half of the inductor ripple current at the maximum input voltage. Load and/or line transients can cause the peak current to exceed this level for short durations. Maintaining the peak current below the inductor saturation specification keeps the inductor ripple current and the output voltage ripple at acceptable levels. Manufacturers often provide graphs of actual inductance and saturation characteristics versus applied inductor current. The saturation characteristics of the inductor can vary significantly with core temperature. Core and ambient temperatures should be considered when examining the core saturation characteristics. When the inductance has been determined, the DC resistance (DCR) must be examined. The efficiency that can be achieved is dependent upon the DCR of the inductor. Lower values give higher efficiency. The RMS DC current rating of the inductor is associated with losses in the copper windings and the resulting temperature rise of the inductor. This is usually specified as the current which produces a 40˚C temperature rise. Most copper windings are rated to accommodate this temperature rise above maximum ambient. Magnetic fields associated with the output inductor can interfere with nearby circuitry. This can be minimized by the use of low noise shielded inductors which use the minimum gap possible to limit the distance that magnetic fields can radiate from the inductor. However shielded inductors typically have a higher DCR and are thus less efficient than a similarly sized non-shielded inductor. Final inductor selection depends upon various design considerations such as efficiency, EMI, size, and cost. Table 2 lists the manufacturers of recommended inductor options. The saturation characteristics and DC current ratings are also shown. Manufacturer Part Number L (μH) DCR Max (Ω) Rated Current (A) L at Rated Current (μH) Dimen- sions LxWxH (mm) TOKO TOKO Panasonic Table 2 – Recommended Inductors COUT Selection The internal voltage loop compensation in the SC284P limits the minimum output capacitor value to 22µF if using a 2.2µH inductor or 44µF if using a µH inductor. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. The total output capacitance should not exceed 50µF to avoid any start-up problems. For most typical applications it is recommended to use an output capacitance of 22µF to 44µF. When choosing the output capacitor’s capacitance, verify the voltage derating effect from the capacitor vendor’s data sheet. Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. The output voltage droop due to a load transient is determined by the capacitance of the ceramic output capacitor. The ceramic capacitor supplies the load current initially until the loop responds. Within a few switching cycles the loop will respond and the inductor current will increase to match the required load. The output voltage droop during the period prior to the loop responding can be related to the choice of output capacitor by the relationship from the following equation. The output capacitor RMS ripple current may be calculated 26&'5223 /2$' 287 ,& u

Applications Information (continued) from the following equation. Table 3 lists the manufac turers of recommended capacitor options. Manufacturer Part Nunber Value (μF) Type Rated Voltage (VDC) Value at 3.3V (μF) Dimensions LxWxH (mm) Murata (EIA:0805) Murata (EIA:0805) Murata (EIA:0805) Murata (EIA:206) Table 3 – Recommended Capacitors CIN Selection The SC284P source input current is a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 0μF should be used. It is important to consider the DC voltage coefficient charac - teristics when determining the actual required value. It should be noted a 0µF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.05µF. To estimate the required input capacitor, determine the acceptable input ripple voltage and calculate the minimum value required for CIN as shown by the following equation. 26& 287 287 287 I(65, u¸¸ § ' The input capacitor RMS ripple current varies with the input and output voltage. The maximum input capacitor RMS current is found from the next equation . The input voltage ripple and RMS current ripple are at a maximum when the input voltage is twice the output voltage or 50% duty cycle. The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimize stray inductance, the capaci- tor should be placed as close as possible to the VIN and GND pins of the SC284P . 287 287 506 &,1 uu u ,126& 287 0$; ,1287 506 &287 9I/ 999

Applications Information (continued) Figure 6 — Soft Start Operation Figure 5 — Current Limit Protection 6WDJH 6WDJH 6WDJH 6WDJH 6WDJH 6WDJH 6WDJH 6WDJH 6WDJH 6WDJH J M K L Stages Operation description 0 Chip is OFF. Peak current limit at 20% level PWM "ON" when inductor current of 0A PWM "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 25% level PWM "ON" when inductor current of 0A PWM "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 40% level PWM "ON" when inductor current of 500mA PWM "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 100% level PWM "ON" when inductor current of 500mA PWM "OFF" when inductor current hits peak current limit Stage duration of 400µs

5 Peak current limit at 100% level

Switch to closed-loop PWM operation. Soft Start ends. Normal PWM operation Overload protection is enabled Conditions Operation description A VIN > UVLO Threshold AND One or more CTL pin is high. AND Internal reference is ready. B End of stage 1 AND Vout<86% of target C End of stage 2 AND Vout<86% of target D End of stage 3 AND Vout<86% of target E End of stage 4 AND Vout<86% of target F Vout>86% of target G Vout>86% of target H Vout>86% of target I End of soft start time of 1700µs Stages Operation description

6 Normal PWM operation

Overload protection is enabled and peak current limit at 100% level

7 Cycle by cycle peak current limit

OCP protection is activated. Foldback peak current limit. PWM "ON" when inductor current of 0A PWM "OFF" when inductor current hits peak current limit of foldback mode. Conditions Operation description J Inductor current hits peak current limit K Peak current limit for 16 consecutive cycles L Vout ≥ 100% target M Inductor current doesn't hit peak current limit

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