74ABT821 PHILIPS | Alldatasheet

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Philips Semiconductors Product specification 74ABT82110-bit D-type flip-flop; positive-edge trigger (3-State)

11995 Sep 06 853-1616 15703

FEATURES

  • High speed parallel registers with positive edge-triggered D-type flip-flops
  • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
  • Output capability: +64mA/–32mA
  • Latch-up protection exceeds 500mA per Jedec Std 17
  • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
  • Power-up 3-State
  • Power-up Reset

DESCRIPTION

The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT821 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT821 is a buffered 10-bit wide version of the 74ABT374/74ABT534 functions. The 74ABT821 is a 10-bit, edge triggered register coupled to ten 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE ) controls all ten 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in high impedance ”off” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay CP to Qn C L = 50pF; VCC = 5V 4.6 ns C IN Input capacitance VI = 0V or VCC 4 pF C OUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 500 nA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40°C to +85°C 74ABT821 N 74ABT821 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT821 D 74ABT821 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT821 DB 74ABT821 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT821 PW 74ABT821PW DH SOT355-1 PIN CONFIGURATION 10 15 24OE D7 Q7 VCC 11 14D9 Q9 12 13GND CP TOP VIEW SA00223 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION

1 OE Output enable input

(active-Low) 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 D0-D9 Data inputs 18, 17, 16, 15, 14 Q0-Q9 Data outputs

13 CP Clock pulse input (active

rising edge)

10 GND Ground (0V)

20 VCC Positive supply voltage

Philips Semiconductors Product specification 74ABT82110-bit D-type flip-flop; positive-edge trigger (3-State)

1995 Sep 06 2

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 22 21 20 19 18 17 16 15 14 CP OE SA00224 LOGIC SYMBOL (IEEE/IEC) 22 3 32 2 42 1 52 0 61 9 71 8 81 7 91 6 10 15 11 14 2D 1 EN SA00225 FUNCTION TABLE INPUTS INTERNAL OUTPUTS OPERATING MODE OE CP Dn REGISTER Q0 – Q9 L L l h L H L H Load and read register L ↑ X NC NC Hold H H X Dn NC Dn Z Z Disable outputs H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low to High clock transition = Not a Low-to-High clock transition LOGIC DIAGRAM CP Q D CP OE CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D SA00226

Philips Semiconductors Product specification 74ABT82110-bit D-type flip-flop; positive-edge trigger (3-State)

1995 Sep 06 3

ABSOLUTE MAXIMUM RATINGS 1, 2 SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +7.0 V IIK DC input diode current VI < 0 –18 mA VI DC input voltage3 –1.2 to +7.0 V IOK DC output diode current VO < 0 –50 mA VOUT DC output voltage3 output in Off or High state –0.5 to +5.5 V IOUT DC output current output in Low state 128 mA Tstg Storage temperature range –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT Min Max VCC DC supply voltage 4.5 5.5 V VI Input voltage 0 VCC V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA Δt/Δv Input transition rise or fall rate 0 10 ns/V Tamb Operating free-air temperature range –40 +85 °C

Philips Semiconductors Product specification 74ABT82110-bit D-type flip-flop; positive-edge trigger (3-State)

1995 Sep 06 4

DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = –40°C to +85°C UNIT Min Typ Max Min Max VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VOH High-level output voltageVCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V IOFF Power-off leakage currentVCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA IPU /IPD Power-up/down 3-State output current4 VCC = 2.0V; VO = 0.5V; VI = GND or VCC ; V OE = VCC ±5.0 ±50 ±50 µA IOZH 3-State output High currentVCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low currentVCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage currentVCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 250 250 µA ICCL Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 25 38 38 mA ICCZ VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 250 250 µA ΔICC Additional supply current per input pin2 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any V CC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT Min Typ Max Typ Max fMAX Maximum clock frequency 1 125 185 125 ns tPLH tPHL Propagation delay CP to Qn 1 2.1 2.8 4.1 4.6 5.6 6.2 2.1 2.8 6.2 6.7 ns tPZH tPZL Output enable time to High and Low level 1.0 2.2 3.0 4.1 4.5 5.6 1.0 2.2 5.3 6.3 ns tPHZ tPLZ Output disable time from High and Low level 2.7 2.8 4.7 4.6 6.2 6.1 2.7 2.8 6.7 6.5 ns

Philips Semiconductors Product specification 74ABT82110-bit D-type flip-flop; positive-edge trigger (3-State)

1995 Sep 06 5

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT Min Typ Min ts(H) ts(L) Setup time, High or Low Dn to CP 2 2.1 2.1 0.5 0.3 2.1 2.1 ns th(H) th(L) Hold time, High or Low Dn to CP 2 1.3 1.3 0.0 –0.3 1.3 1.3 ns tw (H) tw (L) CP pulse width High or Low 1 2.9 3.8 1.8 2.8 2.9 3.8 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V VM tPLHtPHL VM VM VMCP Q n 1/fMAX tW (H) tW (L) SA00159 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency OE VM tPZH tPHZ Qn VM VM SA00066 VOH –0.3V Waveform 3. 3–State Output Enable Time to High Level and Output Disable Time from High Level ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ VMDn VM VM VM VM VM CP ts(H) t h(H) t s(L) t h(L) NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00107 Waveform 2. Data Setup and Hold Times OE tPZL tPLZ Qn VM VM VM SA00067 VOL +0.3V Waveform 4. 3–State Output Enable Time to Low Level and Output Disable Time from Low Level

Philips Semiconductors Product specification 74ABT82110-bit D-type flip-flop; positive-edge trigger (3-State)

1995 Sep 06 6

7.0V Test Circuit for 3-State Outputs VM VM tW AMP (V) NEGATIVE PULSE 10% 10% 90% 90% VM VM tW AMP (V) POSITIVE PULSE 90% 90% 10% 10% tTHL (tF) tTLH (tR )t THL (tF) tTLH (tR ) VM = 1.5V Input Pulse Definition DEFINITIONS R L = Load resistor; see AC CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate t W tR tF 74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open SA00012 D.U.T.